Automobile manufacturers are controlled by stringent govt. regulations for safety and fuel emissions and
motivated towards adding more advanced features and sophisticated applications to the existing electronic
system. Ever increasing customer’s demands for high level of comfort also necessitate providing even more
sophistication in vehicle electronics system. All these, directly make the vehicle software system more
complex and computationally more intensive. In turn, this demands very high computational capability of
the microprocessor used in electronic control unit (ECU). In this regard, multicore processors have
already been implemented in some of the task rigorous ECUs like, power train, image processing and
infotainment. To achieve greater performance from these multicore processors, parallelized ECU software
needs to be efficiently scheduled by the underlaying operating system for execution to utilize all the
computational cores to the maximum extent possible and meet the real time constraint. In this paper, we
propose a dynamic task scheduler for multicore engine control ECU that provides maximum CPU
utilization, minimized preemption overhead, minimum average waiting time and all the tasks meet their
real time deadlines while compared to the static priority scheduling suggested by Automotive Open Systems
Architecture (AUTOSAR).
Integrating fault tolerant scheme with feedback control scheduling algorithm ...ijics
In order to provide Quality of Service (QoS) in open and unpredictable environment, Feedback based
Control Scheduling Algorithm (FCSA) is designed to keep the processor utilization at the scheduling
utilization bound. FCSA controls CPU utilization by assigning task periods that optimize overall control
performance, meeting deadlines even if the task execution time is unpredictable and through performance
control feedback loop. Current FCSA doesn’t ensure Fault Tolerance (FT) while providing QoS in terms of
CPU utilization and resource management. In order to assure that tasks should meet their deadlines even
in the presence of faults, a FT scheme has to be integrated at control scheduling co-design level. This paper
presents a novel approach on integrating FT scheme with FCSA for real time embedded systems. This
procedure is especially important for control scheduling co-design of embedded systems.
D1.2 analysis and selection of low power techniques, services and patternsBabak Sorkhpour
Goal: SAFEPOWER has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 687902.
SAFEPOWER’s goal is to enable the development of low power mixed-criticality systems through the provision of a reference architecture, platforms and tools to facilitate the development, testing, and validation of these kinds of systems according to the market needs
It is expected that the SAFEPOWER reference architecture and platforms will enable the integration and partitioning of mixed-criticality applications on a single device while reducing the total power consumption by 50%, compared to the non-integrated multi-chip implementation. To address this goal, SAFEPOWER needs to address a number of technology development challenges, that will afterwards be applied to the main project outputs, namely the SAFEPOWER low power reference architecture, the platforms and tools for the development, testing, and validation of low power mixed criticality systems.
PROJECT PARTNER(S):IKERLAN, S. Coop.CAF Signalling, S.L.fent Innovative Software SolutionsImperas Software Ltd.Kungliga Tekniska Högskolan (Royal Institute of Technology)SAAB ABUniversität Siegen
Methods: Railway Engineering, Energy Efficiency, Multi-Core Systems, Safety-Critical Systems, Industrial Safety, Avionics, MPSOCs, NoC, Fault Tolerance, Scheduling Theory, Power Management, Dependable Systems, MIXED CRITICALITY, predictable architectures and communication, Low Power Techniques, ENERGY MINIMIZATION TECHNIQUES, Energy and Power efficiency, Low power multicore embedded systems, Fault Isolation, hypervisor
Social media links:
a.Twitter : https://twitter.com/SAFEPOWER_H2020
b.Linkdin : https://www.linkedin.com/groups/7045467
d. Website : http://safepower-project.eu/
d.ResearchGate : https://www.researchgate.net/project/SAFEPOWER
Run time dynamic partial reconfiguration using microblaze soft core processor...eSAT Journals
aydeshmukh@gmail.com
Abstract
DSP Application requires a fast computations & flexibility of the design. Partial Reconfiguration (PR) is an advanced technique,
which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the
configuration memory. In this paper we are using microblaze soft core processor & ICAP Port to reconfigure the FPGA at runtime.
ICAP is accessed through a light-weight custom IP which requires bit stream length, go, and done signal to interface to a system that
provides partial bit stream data. The partial bit stream is provided by the processor system by reading the partial bit files from the
compact flash card. Our targeted DSP application is matrix multiplication; we are reconfiguring design by changing partial modules
at run time. To change the partial bit stream we interfaces a microblaze Soft processor & using a UART interface.ISE13.1 &
PlanAhead is used for partial reconfiguration of FPGA .EDK is used for microblaze soft processor design & ICAP Interface .The
simulation is done using Chip Scope Logic Analyzer & the complete hardware implementation is done on Xilinx VIRTEX -6 ML605
Platform.
Keywords — PlanAhead, EDK, Dynamic partial reconfiguration, ICAP, Matrix multiplication, Chipscope pro analysis,
DSP application, Microblaze processor
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Integrating fault tolerant scheme with feedback control scheduling algorithm ...ijics
In order to provide Quality of Service (QoS) in open and unpredictable environment, Feedback based
Control Scheduling Algorithm (FCSA) is designed to keep the processor utilization at the scheduling
utilization bound. FCSA controls CPU utilization by assigning task periods that optimize overall control
performance, meeting deadlines even if the task execution time is unpredictable and through performance
control feedback loop. Current FCSA doesn’t ensure Fault Tolerance (FT) while providing QoS in terms of
CPU utilization and resource management. In order to assure that tasks should meet their deadlines even
in the presence of faults, a FT scheme has to be integrated at control scheduling co-design level. This paper
presents a novel approach on integrating FT scheme with FCSA for real time embedded systems. This
procedure is especially important for control scheduling co-design of embedded systems.
D1.2 analysis and selection of low power techniques, services and patternsBabak Sorkhpour
Goal: SAFEPOWER has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 687902.
SAFEPOWER’s goal is to enable the development of low power mixed-criticality systems through the provision of a reference architecture, platforms and tools to facilitate the development, testing, and validation of these kinds of systems according to the market needs
It is expected that the SAFEPOWER reference architecture and platforms will enable the integration and partitioning of mixed-criticality applications on a single device while reducing the total power consumption by 50%, compared to the non-integrated multi-chip implementation. To address this goal, SAFEPOWER needs to address a number of technology development challenges, that will afterwards be applied to the main project outputs, namely the SAFEPOWER low power reference architecture, the platforms and tools for the development, testing, and validation of low power mixed criticality systems.
PROJECT PARTNER(S):IKERLAN, S. Coop.CAF Signalling, S.L.fent Innovative Software SolutionsImperas Software Ltd.Kungliga Tekniska Högskolan (Royal Institute of Technology)SAAB ABUniversität Siegen
Methods: Railway Engineering, Energy Efficiency, Multi-Core Systems, Safety-Critical Systems, Industrial Safety, Avionics, MPSOCs, NoC, Fault Tolerance, Scheduling Theory, Power Management, Dependable Systems, MIXED CRITICALITY, predictable architectures and communication, Low Power Techniques, ENERGY MINIMIZATION TECHNIQUES, Energy and Power efficiency, Low power multicore embedded systems, Fault Isolation, hypervisor
Social media links:
a.Twitter : https://twitter.com/SAFEPOWER_H2020
b.Linkdin : https://www.linkedin.com/groups/7045467
d. Website : http://safepower-project.eu/
d.ResearchGate : https://www.researchgate.net/project/SAFEPOWER
Run time dynamic partial reconfiguration using microblaze soft core processor...eSAT Journals
aydeshmukh@gmail.com
Abstract
DSP Application requires a fast computations & flexibility of the design. Partial Reconfiguration (PR) is an advanced technique,
which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the
configuration memory. In this paper we are using microblaze soft core processor & ICAP Port to reconfigure the FPGA at runtime.
ICAP is accessed through a light-weight custom IP which requires bit stream length, go, and done signal to interface to a system that
provides partial bit stream data. The partial bit stream is provided by the processor system by reading the partial bit files from the
compact flash card. Our targeted DSP application is matrix multiplication; we are reconfiguring design by changing partial modules
at run time. To change the partial bit stream we interfaces a microblaze Soft processor & using a UART interface.ISE13.1 &
PlanAhead is used for partial reconfiguration of FPGA .EDK is used for microblaze soft processor design & ICAP Interface .The
simulation is done using Chip Scope Logic Analyzer & the complete hardware implementation is done on Xilinx VIRTEX -6 ML605
Platform.
Keywords — PlanAhead, EDK, Dynamic partial reconfiguration, ICAP, Matrix multiplication, Chipscope pro analysis,
DSP application, Microblaze processor
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
The papers for publication in The International Journal of Engineering& Science are selected through rigorous peer reviews to ensure originality, timeliness, relevance, and readability.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
ISPRS: COMPARISON OF MULTIPLE IMUs IN AN EXPERIMENTAL FLIGHT TESTLaura Samsó, MSc
Laura Samsó, Mariano Wis, Ismael Colomina
GP-IMU-Bench experiment consists of simultaneous acquisition of data from multiple inertial units under the same
dynamic and static conditions. To accomplish those conditions, all the sensors are fixed on a platform that is directly
mounted into an airplane. This configuration permits all the inertial units to be able to sense the same movements. The
aim of this experiment is to obtain a set of data that allows establishing some comparisons among the IMUs that the IG
owns. The results of this experiment are very helpful to evaluate which is the best kind of IMU to be mounted on any
remote sensor.
In order to get these datasets, a series of HW and SW modifications were applied on IG’s TAG system for acquiring
the data from the IMUs simultaneously. Therefore, this paper goes through these modifications made on the system
with a more detailed description of the experiment. Some preliminary results of the comparison are shown.
The timing behavior of the OS must be predictable - services of the OS: Upper bound on the execution time!
2. OS must manage the timing and scheduling
OS possibly has to be aware of task deadlines;
(unless scheduling is done off-line).
3. The OS must be fast
The note is compiled with reference from many sites and According to the syllabus of Real Time System (6th semester CSIT). Drive deep to the never ending knowledge.
For Induction motor is a system that works at their speed, nevertheless there are applications at which the speed operations are needed. The control of range of speed of induction motor techniques is available. The robust control is used with induction motor and the performance of the system with the controller will be improved. The mathematical model to the controller, which were coded in MATLAB. The modeling and controller will be shown by the conditions of robustness of be less than one.
Design and Development of Arm-Based Control System for Nursing Bed IJCSES Journal
This paper introduces a kind of ARM embedded system as the control systemof the nursing bed.The
embedded control system takes the ARM9 S3C2440 chip as the core of data processing. The design ofthe
control system includes hardware design, software design and PC monitoring system design.
REAL-TIME SCHEDULING ALGORITHMS FOR WIRELESS SENSOR NETWORKcsijjournal
In Recent era, researchers attention is get magnetize towards a widely used technology known as a wireless sensor networks (WSNs) used in the many of applications related to variety of fields including military, healthcare
monitoring, biological, home, vehicular monitoring, infrastructure monitoring, building energy monitoring and industrial sensing. Many of applications in WSNs are real time applications that are requested to run in real time
way. To support such real time applications we need Real Time Operating System (RTOS) which provides logically correct results and also deadline has to be met. This paper presents an overview of existing scheduling
algorithms which helps to schedule tasks in real time systems. Next, we discuss work in sensornet operating system (OS) design. Then, the specialties what sensornet OS should posses are discussed in detail. At last, we
proposed Micro Controller OS-II (µC/OS-II) with Earliest Deadline First (EDF) algorithm.
ENHANCING MULTIPLIER SPEED IN FAST FOURIER TRANSFORM BASED ON VEDIC MATHEMATICSVLSICS Design
Vedic mathematics is an ancient system of mathematics which has a unique technique of calculations based
on 16 sutras. The performance of high speed multiplier is designed based on Urdhva Tiryabhyam, Nikhilam
Navatashcaramam Dashatah, and Anurupye Vedic mathematical algorithms. These algorithms gives
minimum delay and used for multiplication of all types of numbers. The performance of high speed multiplier
is designed and compared using these sutras for various NxN bit multiplications and implemented on the
FFT of the DSP processor. Anurupye sutra on FFT is made efficient than Urdhva tiryabhyam and Nikhilam
Navatashcaramam Dashatah sutras by more reduction in computation time. This gives the method for
hierarchical multiplier design. Logic verification of these designs is verified by simulating the logic circuits
in XILINX ISE 9.1 and MODELSIM SE 5.7g using VHDL coding.
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
Analysis of pocket double gate tunnel fet for low stand by power logic circuitsVLSICS Design
For low power circuits downscaling of MOSFET has a major issue of scaling of voltage which has ceased
after 1V. This paper highlights comparative study and analysis of pocket double gate tunnel FET
(DGTFET) with MOSFET for low standby power logic circuits. The leakage current of pocket DGTFET
and MOSFET have been studied and the analysis results shows that the pocket DGTFET gives the lower
leakage current than the MOSFET. Further a pocket DGTFET inverter circuit is design in 32 nm
technology node at VDD =0.6 V. The pocket DGTFET inverter shows the significant improvement on the
leakage power than multi-threshold CMOS (MTCMOS) inverter. The leakage power of pocket DGFET and
MTCMOS inverter are 0.116 pW and 1.83 pW respectively. It is found that, the pocket DGTFET can
replace the MOSFET for low standby power circuits.
Analytical modeling of electric field distribution in dual material junctionl...VLSICS Design
In this paper, electric field distribution of the junctionless dual material surrounding gate MOSFETs
(JLDMSG) is developed. Junctionless is a device that has similar characteristics like junction based
devices, but junctionless has a positive flatband voltage with zero electric field. In Surrounding gate
MOSFETs gate material surrounds the channel in all direction , therefore it can overcome the short
channel effects effectively than other devices. In this paper, surface potential and electric field distribution
is modelled. The proposed surface potential model is compared with the existing central potential model. It
is observed that the short channel effects (SCE) is reduced and the performance is better than the existing
method.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
The papers for publication in The International Journal of Engineering& Science are selected through rigorous peer reviews to ensure originality, timeliness, relevance, and readability.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
ISPRS: COMPARISON OF MULTIPLE IMUs IN AN EXPERIMENTAL FLIGHT TESTLaura Samsó, MSc
Laura Samsó, Mariano Wis, Ismael Colomina
GP-IMU-Bench experiment consists of simultaneous acquisition of data from multiple inertial units under the same
dynamic and static conditions. To accomplish those conditions, all the sensors are fixed on a platform that is directly
mounted into an airplane. This configuration permits all the inertial units to be able to sense the same movements. The
aim of this experiment is to obtain a set of data that allows establishing some comparisons among the IMUs that the IG
owns. The results of this experiment are very helpful to evaluate which is the best kind of IMU to be mounted on any
remote sensor.
In order to get these datasets, a series of HW and SW modifications were applied on IG’s TAG system for acquiring
the data from the IMUs simultaneously. Therefore, this paper goes through these modifications made on the system
with a more detailed description of the experiment. Some preliminary results of the comparison are shown.
The timing behavior of the OS must be predictable - services of the OS: Upper bound on the execution time!
2. OS must manage the timing and scheduling
OS possibly has to be aware of task deadlines;
(unless scheduling is done off-line).
3. The OS must be fast
The note is compiled with reference from many sites and According to the syllabus of Real Time System (6th semester CSIT). Drive deep to the never ending knowledge.
For Induction motor is a system that works at their speed, nevertheless there are applications at which the speed operations are needed. The control of range of speed of induction motor techniques is available. The robust control is used with induction motor and the performance of the system with the controller will be improved. The mathematical model to the controller, which were coded in MATLAB. The modeling and controller will be shown by the conditions of robustness of be less than one.
Design and Development of Arm-Based Control System for Nursing Bed IJCSES Journal
This paper introduces a kind of ARM embedded system as the control systemof the nursing bed.The
embedded control system takes the ARM9 S3C2440 chip as the core of data processing. The design ofthe
control system includes hardware design, software design and PC monitoring system design.
REAL-TIME SCHEDULING ALGORITHMS FOR WIRELESS SENSOR NETWORKcsijjournal
In Recent era, researchers attention is get magnetize towards a widely used technology known as a wireless sensor networks (WSNs) used in the many of applications related to variety of fields including military, healthcare
monitoring, biological, home, vehicular monitoring, infrastructure monitoring, building energy monitoring and industrial sensing. Many of applications in WSNs are real time applications that are requested to run in real time
way. To support such real time applications we need Real Time Operating System (RTOS) which provides logically correct results and also deadline has to be met. This paper presents an overview of existing scheduling
algorithms which helps to schedule tasks in real time systems. Next, we discuss work in sensornet operating system (OS) design. Then, the specialties what sensornet OS should posses are discussed in detail. At last, we
proposed Micro Controller OS-II (µC/OS-II) with Earliest Deadline First (EDF) algorithm.
ENHANCING MULTIPLIER SPEED IN FAST FOURIER TRANSFORM BASED ON VEDIC MATHEMATICSVLSICS Design
Vedic mathematics is an ancient system of mathematics which has a unique technique of calculations based
on 16 sutras. The performance of high speed multiplier is designed based on Urdhva Tiryabhyam, Nikhilam
Navatashcaramam Dashatah, and Anurupye Vedic mathematical algorithms. These algorithms gives
minimum delay and used for multiplication of all types of numbers. The performance of high speed multiplier
is designed and compared using these sutras for various NxN bit multiplications and implemented on the
FFT of the DSP processor. Anurupye sutra on FFT is made efficient than Urdhva tiryabhyam and Nikhilam
Navatashcaramam Dashatah sutras by more reduction in computation time. This gives the method for
hierarchical multiplier design. Logic verification of these designs is verified by simulating the logic circuits
in XILINX ISE 9.1 and MODELSIM SE 5.7g using VHDL coding.
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
Analysis of pocket double gate tunnel fet for low stand by power logic circuitsVLSICS Design
For low power circuits downscaling of MOSFET has a major issue of scaling of voltage which has ceased
after 1V. This paper highlights comparative study and analysis of pocket double gate tunnel FET
(DGTFET) with MOSFET for low standby power logic circuits. The leakage current of pocket DGTFET
and MOSFET have been studied and the analysis results shows that the pocket DGTFET gives the lower
leakage current than the MOSFET. Further a pocket DGTFET inverter circuit is design in 32 nm
technology node at VDD =0.6 V. The pocket DGTFET inverter shows the significant improvement on the
leakage power than multi-threshold CMOS (MTCMOS) inverter. The leakage power of pocket DGFET and
MTCMOS inverter are 0.116 pW and 1.83 pW respectively. It is found that, the pocket DGTFET can
replace the MOSFET for low standby power circuits.
Analytical modeling of electric field distribution in dual material junctionl...VLSICS Design
In this paper, electric field distribution of the junctionless dual material surrounding gate MOSFETs
(JLDMSG) is developed. Junctionless is a device that has similar characteristics like junction based
devices, but junctionless has a positive flatband voltage with zero electric field. In Surrounding gate
MOSFETs gate material surrounds the channel in all direction , therefore it can overcome the short
channel effects effectively than other devices. In this paper, surface potential and electric field distribution
is modelled. The proposed surface potential model is compared with the existing central potential model. It
is observed that the short channel effects (SCE) is reduced and the performance is better than the existing
method.
Design of 6 bit flash analog to digital converter using variable switching vo...VLSICS Design
This paper presents the design of 6-bit flash analog to digital Converter (ADC) using the new variable
switching voltage (VSV) comparator. In general, Flash ADCs attain the highest conversion speed at the
cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits
significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation
result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of
1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral
nonlinearities (DNL and INL) of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.
Advanced atpg based on fan, testability measures and fault reductionVLSICS Design
A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gate of a
circuit to its minimum leakage state, when device goes into its idle state. Leakage current in CMOS VLSI
circuit has become a major constrain in a battery operated device for technology node below 90nm, as it
drains the battery even when a circuit is in standby mode. Major concern is the leakage even in run time
condition, here aim is to focus on run time leakage reduction technique of integrated Circuit. It is inherited
by stacking effect when the series transistors are maximized in OFF state condition. This method is
independent of process technology and does not require any additional power supply. This paper gives an
optimized solution of input pattern determination of some small circuit to find minimum leakage vector
considering promising and non-promising node which helps to reduce the time complexity of the algorithm.
Proposed algorithm is simulated using HSPICE simulator for 2 input NAND gate and different standard
logic cells and achieved 94.2% and 54.59 % average leakage power reduction for 2 input NAND cell and
different logics respectively.
Crdom cell re ordering based domino on-the-fly mappingVLSICS Design
This Domino logic is often the choice for designing high speed CMOS circuits. Often VLSI designers
choose library based approaches to perform technology mapping of large scale circuits involving static
CMOS logic style. Cells designed using Domino logic style have the flexibility to accommodate wide range
of functions in them. Hence, there is a scope to adopt a library free synthesis approach for circuits
designed using Domino logic. In this work, we present an approach for mapping a domino logic circuit
using an On-the-fly technique. First, we present a node mapping algorithm which maps a given Domino
logic netlist using On-the-fly technique. Next, using an Equivalence Table, we re-order the cells along the
critical path for delay, area benefit. Finally, we find an optimum re-ordering set which can obtain
maximum delay savings for a minimum area penalty. We have tested the efficacy of our approach with a
set of standard benchmark circuits. Our proposed mapping approach (CRDOM) obtained 21%
improvement in area and 17% improvement in delay compared to existing work.
Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of
VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of
retrieving input logic from an output logic because of bijective mapping between input and output. In this
manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of
the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage
outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative
study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from
full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS
transistor with less number of MOS transistor count.
Optimization of Cmos 0.18 µM Low Noise Amplifier Using Nsga-Ii for UWB Applic...VLSICS Design
A design and optimization of 3-5 GHz single ended Radio Frequency (RF) Low Noise Amplifier (LNA) for
ultra-wide-band (UWB) applications using standard UMC 0.18 μm CMOS technology is reported.
Designing of RF circuit components is a challenging job, since even after performing lengthy calculations
and finding parameter values it is less guarantee that the design performs as expected. In view of this the
optimization tool; Elitist Non-Dominated Sorting Genetic Algorithm (NSGA-II); has been employed to get
the optimized starting values of components in the proposed LNA design. The obtained NSGA-II
parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier
achieves a power gain of 22 dB and a minimum Noise Figure of 3 dB is achieved. It dissipates 12.5 mW of
power out of 1.8 V supply.
Accelerating system verilog uvm based vip to improve methodology for verifica...VLSICS Design
In this paper we present the development of Acceleratable UVCs from standard UVCs in System Verilog
and their usage in UVM based Verification Environment of Image Signal Processing designs to increase
run time performance. This paper covers development of Acceleratable UVCs from standard UVCs for
internal control and data buses of ST imaging group by partitioning of transaction-level components and
cycle-accurate signal-level components between the software simulator and hardware accelerator
respectively. Standard Co-Emulation API: Modeling Interface (SCE-MI) compliant, transaction-level
communications link between test benches running on a host system and Emulation machine is established.
Accelerated Verification IPs are used at UVM based Verification Environment of Image Signal Processing
designs both with simulator and emulator as UVM acceleration is an extension of the standard simulationonly
UVM and is fully backward compatible with it. Acceleratable UVCs significantly reduces development
schedule risks while leveraging transaction models used during simulation.
In this paper, we discuss our experiences on UVM based methodology adoption on TestBench-Xpress
(TBX) based technology step by step. We are also doing comparison between the run time performance
results from earlier simulator-only environment and the new, hardware-accelerated environment. Although
this paper focuses on Acceleratable UVC’s development and their usage for image signal processing
designs. Same concept can be extended for non-image signal processing designs.
Here we describe the design details and performance of proposed Carry Propagate Adder based on GDI
technique. GDI technique is power efficient technique for designing digital circuit that consumes less
power as compare to most commonly used CMOS technique. GDI also has an advantage of minimum
propagation delay, minimum area required and less complexity for designing any digital circuit. We
designed Carry Propagate Adder using GDI technique and compared its performance with CMOS
technique in terms of area, delay and power dissipation. Circuit designed using CADENCE EDA tool and
simulated using SPECTRE VIRTUOSO tool at 0.18m technology. Comparative performance result shows
that Carry Propagate Adder using GDI technique dissipated 55.6% less power as compare to Carry
Propagate Adder using CMOS technique.
Low power reduced instruction set architecture using clock gating techniqueVLSICS Design
Today, all the portable device’s in electronics nee
ds to be realized with low power architectures beca
use of
power consumption is a main consideration along wit
h other performance parameters. Low power
consumption helps to reduce heat dissipation, incre
ases battery life and also reliability. In this pap
er a 16-
bit Reduced Instruction set Architecture (RISA) pre
sented. This architecture can handle multiple inter
rupts
and performing serial communication effectively. It
can supported RISC (Reduced Instruction Set
Computer) concepts. A popular technique of Clock ga
ting is applied to the proposed architecture and th
en
reduces the power. This entire architecture capture
d using VerilogHDL and implemented on FPGA using
Xilinx tools
.
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very
Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area
,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic
Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs
have been proposed over last few years with different logic styles. To reduce the power consumption
several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets,
charge sharing by parasitic components while connecting source and drain of CMOS transistors There are
situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset
themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic
which are widely used in dynamic logic circuits. Overall performance of various adder designs is
evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using
Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V.
On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low
PDP among its counterparts.
A New Transistor Sizing Approach for Digital Integrated Circuits Using Firefl...VLSICS Design
Due to the fact that, the power consumption and speed of a VLSI circuit are dependent on the transistor
sizes, efficient transistor sizing is a new challenge for VLSI circuit designers. However, evolutionary
computation can be successfully used for complex VLSI transistor sizing which reduces the time to market
and enables the designer to find the optimized solutions for a non-linear and complex circuit design
process. In this paper, a new digital integrated circuit design approach is proposed based on the firefly
artificial intelligence optimization algorithm. In order to justify the effectiveness of the proposed algorithm
in the design of VLSI circuits, an inverter (NOT gate) is designed and optimized by the proposed algorithm.
As the simulation results show, the inverter circuit has a very good performance for power and delay
parameters.
Nowadays exponential advancement in reversible comp
utation has lead to better fabrication and
integration process. It has become very popular ove
r the last few years since reversible logic circuit
s
dramatically reduce energy loss. It consumes less p
ower by recovering bit loss from its unique input-o
utput
mapping. This paper presents two new gates called
RC-I and RC-II to design an n-bit signed binary
comparator where simulation results show that the p
roposed circuit works correctly and gives significa
ntly
better performance than the existing counterparts.
An algorithm has been presented in this paper for
constructing an optimized reversible n-bit signed c
omparator circuit. Moreover some lower bounds have
been proposed on the quantum cost, the numbers of g
ates used and the number of garbage outputs
generated for designing a low cost reversible sign
ed comparator. The comparative study shows that the
proposed design exhibits superior performance consi
dering all the efficiency parameters of reversible
logic
design which includes number of gates used, quantum
cost, garbage output and constant inputs. This
proposed design has certainly outperformed all the
other existing approaches.
AN EFFICIENT HYBRID SCHEDULER USING DYNAMIC SLACK FOR REAL-TIME CRITICAL TASK...ijesajournal
Task intensive electronic control units (ECUs) in automotive domain, equipped with multicore processors ,
real time operating systems (RTOSs) and various application software, should perform efficiently and time
deterministically. The parallel computational capability offered by this multicore hardware can only be
exploited and utilized if the ECU application software is parallelized. Having provided with such
parallelized software, the real time operating system scheduler component should schedule the time critical
tasks so that, all the computational cores are utilized to a greater extent and the safety critical deadlines
are met. As original equipment manufacturers (OEMs) are always motivated towards adding more
sophisticated features to the existing ECUs, a large number of task sets can be effectively scheduled for
execution within the bounded time limits. In this paper, a hybrid scheduling algorithm has been proposed,
that meticulously calculates the running slack of every task and estimates the probability of meeting
deadline either being in the same partitioned queue or by migrating to another. This algorithm was run and
tested using a scheduling simulator with different real time task models of periodic tasks . This algorithm
was also compared with the existing static priority scheduler, which is suggested by Automotive Open
Systems Architecture (AUTOSAR). The performance parameters considered here are, the % of core
utilization, average response time and task deadline missing rate. It has been verified that, this proposed
algorithm has considerable improvements over the existing partitioned static priority scheduler based on
each performance parameter mentioned above.
ENERGY EFFICIENT SCHEDULING FOR REAL-TIME EMBEDDED SYSTEMS WITH PRECEDENCE AN...IJCSEA Journal
Energy consumption is a critical design issue in real-time systems, especially in battery- operated systems. Maintaining high performance, while extending the battery life between charges is an interesting challenge for system designers. Dynamic Voltage Scaling and Dynamic Frequency Scaling allow us to adjust supply voltage and processor frequency to adapt to the workload demand for better energy management. Usually, higher processor voltage and frequency leads to higher system throughput while energy reduction can be obtained using lower voltage and frequency. Many real-time scheduling algorithms have been developed recently to reduce energy consumption in the portable devices that use voltage scalable processors. For a real-time application, comprising a set of real-time tasks with precedence and resource constraints executing on a distributed system, we propose a dynamic energy efficient scheduling algorithm with weighted First Come First Served (WFCFS) scheme. This also considers the run-time behaviour of tasks, to further explore the idle periods of processors for energy saving. Our algorithm is compared with the existing Modified Feedback Control Scheduling (MFCS), First Come First Served (FCFS), and Weighted scheduling (WS) algorithms that uses Service-Rate-Proportionate (SRP) Slack Distribution Technique. Our proposed algorithm achieves about 5 to 6 percent more energy savings and increased reliability over the existing ones.
SCHEDULING DIFFERENT CUSTOMER ACTIVITIES WITH SENSING DEVICEijait
Most periodic tasks are assigned to processors using partition scheduling policy after checking feasibility conditions. A new approach is proposed for scheduling different activities with one periodic task within the system. In this paper, control strategies are identified for allocating different types of tasks (activities) to
individual computing elements like Smartphone or microphones. In our simulation model, each periodic task generates an aperiodic tasks are taken into consideration. Different sets of periodic tasks and aperiodic tasks are scheduled together. This new approach proves that when all different activities are
scheduled with one periodic tasks leads to better performance.
CS 301 Computer ArchitectureStudent # 1 EID 09Kingdom of .docxfaithxdunce63732
CS 301 Computer Architecture
Student # 1
E
ID: 09
Kingdom of Saudi Arabia Royal Commission at Yanbu Yanbu University College Yanbu Al-Sinaiyah
Student # 2
H
ID: 09
Kingdom of Saudi Arabia Royal Commission at Yanbu Yanbu University College Yanbu Al-Sinaiyah
1
1. Introduction
High-performance processor design has recently taken two distinct approaches. One approach is to increase the execution rate by increasing the clock frequency of the processor or by reducing the execution latency of the operations. While this approach is important, much of its performance gain comes as a consequence of circuit and layout improvements and is beyond the scope of this research. The other approach is to directly exploit the instruction-level parallelism (ILP) in the program and to issue and execute multiple operations concurrently. This approach requires both compiler and microarchitecture support.
Traditional processor designs that issue and execute at most one operation per cycle are often called scalar designs. Static and dynamic scheduling techniques have been used to achieve better-than scalar performance by issuing and executing more than one operation per cycle. While Johnson[7] defines a superscalar processor as a design that achieves better-than scalar performance, popular usage of this term refers exclusively to those processors that use dynamic scheduling techniques. For clarity, we use instruction-level parallel processors to refer to the general class of processors that execute more than one operation per cycle of the computer both at the personal level, or the level of a small network of computers to do not require more of these types.
The primary static scheduling technique uses the compiler to determine sets of operations that have their source operands ready and have no dependencies within the set. These operations can then be scheduled within the same instruction subject only to hardware resource limits. Since each of the operations in an instruction is guaranteed by the compiler to be independent, the hardware is able to is- sue and execute these operations directly with no dynamic analysis. These multi-operation instructions are very long in comparison with traditional single-operation instructions and processors using .
TIME CRITICAL MULTITASKING FOR MULTICORE MICROCONTROLLER USING XMOS® KITijesajournal
This paper presents the research work on multicore microcontrollers using parallel, and time critical
programming for the embedded systems. Due to the high complexity and limitations, it is very hard to work
on the application development phase on such architectures. The experimental results mentioned in the
paper are based on xCORE multicore microcontroller form XMOS®
. The paper also imitates multi-tasking
and parallel programming for the same platform. The tasks assigned to multiple cores are executed
simultaneously, which saves the time and energy. The relative study for multicore processor and multicore
controller concludes that micro architecture based controller having multiple cores illustrates better
performance in time critical multi-tasking environment. The research work mentioned here not only
illustrates the functionality of multicore microcontroller, but also express the novel technique of
programming, profiling and optimization on such platforms in real time environments.
A tricky task scheduling technique to optimize time cost and reliability in m...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Integrating Fault Tolerant Scheme With Feedback Control Scheduling Algorithm ...ijics
In order to provide Quality of Service (QoS) in open and unpredictable environment, Feedback based
Control Scheduling Algorithm (FCSA) is designed to keep the processor utilization at the scheduling
utilization bound. FCSA controls CPU utilization by assigning task periods that optimize overall control
performance, meeting deadlines even if the task execution time is unpredictable and through performance
control feedback loop.
Reinforcement learning based multi core scheduling (RLBMCS) for real time sys...IJECEIAES
Embedded systems with multi core processors are increasingly popular because of the diversity of applications that can be run on it. In this work, a reinforcement learning based scheduling method is proposed to handle the real time tasks in multi core systems with effective CPU usage and lower response time. The priority of the tasks is varied dynamically to ensure fairness with reinforcement learning based priority assignment and Multi Core MultiLevel Feedback queue (MCMLFQ) to manage the task execution in multi core system
Time critical multitasking for multicoreijesajournal
This paper presents the research work on multicore microcontrollers using parallel, and time critical
programming for the embedded systems. Due to the high complexity and limitations, it is very hard to work
on the application development phase on such architectures. The experimental results mentioned in the
paper are based on xCORE multicore microcontroller form XMOS®. The paper also imitates multi-tasking
and parallel programming for the same platform. The tasks assigned to multiple cores are executed
simultaneously, which saves the time and energy. The relative study for multicore processor and multicore
controller concludes that micro architecture based controller having multiple cores illustrates better
performance in time critical multi-tasking environment. The research work mentioned here not only
illustrates the functionality of multicore microcontroller, but also express the novel technique of
programming, profiling and optimization on such platforms in real time environments.
LEARNING SCHEDULER PARAMETERS FOR ADAPTIVE PREEMPTIONcscpconf
An operating system scheduler is expected to not allow processor stay idle if there is any
process ready or waiting for its execution. This problem gains more importance as the numbers
of processes always outnumber the processors by large margins. It is in this regard that
schedulers are provided with the ability to preempt a running process, by following any
scheduling algorithm, and give us an illusion of simultaneous running of several processes. A
process which is allowed to utilize CPU resources for a fixed quantum of time (termed as
timeslice for preemption) and is then preempted for another waiting process. Each of these
'process preemption' leads to considerable overhead of CPU cycles which are valuable resource
for runtime execution. In this work we try to utilize the historical performances of a scheduler
and predict the nature of current running process, thereby trying to reduce the number of
preemptions. We propose a machine-learning module to predict a better performing timeslice
which is calculated based on static knowledge base and adaptive reinforcement learning based
suggestive module. Results for an "adaptive timeslice parameter" for preemption show good
saving on CPU cycles and efficient throughput time.
Learning scheduler parameters for adaptive preemptioncsandit
An operating system scheduler is expected to not al
low processor stay idle if there is any
process ready or waiting for its execution. This pr
oblem gains more importance as the numbers
of processes always outnumber the processors by lar
ge margins. It is in this regard that
schedulers are provided with the ability to preempt
a running process, by following any
scheduling algorithm, and give us an illusion of si
multaneous running of several processes. A
process which is allowed to utilize CPU resources f
or a fixed quantum of time (termed as
timeslice for preemption) and is then preempted for
another waiting process. Each of these
'process preemption' leads to considerable overhead
of CPU cycles which are valuable resource
for runtime execution. In this work we try to utili
ze the historical performances of a scheduler
and predict the nature of current running process,
thereby trying to reduce the number of
preemptions. We propose a machine-learning module t
o predict a better performing timeslice
which is calculated based on static knowledge base
and adaptive reinforcement learning based
suggestive module. Results for an "adaptive timesli
ce parameter" for preemption show good
saving on CPU cycles and efficient throughput time.
Similar to Dynamic task scheduling on multicore automotive ec us (20)
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Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
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Sr Director, Infrastructure Ecosystem, Arm.
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Generating a custom Ruby SDK for your web service or Rails API using Smithyg2nightmarescribd
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- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
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Dynamic task scheduling on multicore automotive ec us
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.6, December 2014
DOI : 10.5121/vlsic.2014.5601 1
DYNAMIC TASK SCHEDULING ON MULTICORE
AUTOMOTIVE ECUS
Geetishree Mishra1
, K S Gurumurthy2
1
BMS College of Engineering, Bangalore, India,
2
Reva Intitute of Technology, Bangalore, India
ABSTRACT
Automobile manufacturers are controlled by stringent govt. regulations for safety and fuel emissions and
motivated towards adding more advanced features and sophisticated applications to the existing electronic
system. Ever increasing customer’s demands for high level of comfort also necessitate providing even more
sophistication in vehicle electronics system. All these, directly make the vehicle software system more
complex and computationally more intensive. In turn, this demands very high computational capability of
the microprocessor used in electronic control unit (ECU). In this regard, multicore processors have
already been implemented in some of the task rigorous ECUs like, power train, image processing and
infotainment. To achieve greater performance from these multicore processors, parallelized ECU software
needs to be efficiently scheduled by the underlaying operating system for execution to utilize all the
computational cores to the maximum extent possible and meet the real time constraint. In this paper, we
propose a dynamic task scheduler for multicore engine control ECU that provides maximum CPU
utilization, minimized preemption overhead, minimum average waiting time and all the tasks meet their
real time deadlines while compared to the static priority scheduling suggested by Automotive Open Systems
Architecture (AUTOSAR).
KEYWORDS
OEM, ECU, Multicore, Scheduling, AUTOSAR.
1. INTRODUCTION
Electronic Control Units (ECUs) fulfill the objectives and requirements of a modern automobile
which is designed to be safer, more comfortable and fuel efficient. Therefore the number of ECUs
has been increased continuously over the years. Advanced functionalities demand higher
computational capabilities from ECUs. Multicore processors have emerged to be the current
processing unit not only for high-end servers but also for embedded control systems [10, 11].
Multicore processor features with parallel processing, compact chip size and lower power
consumption. Performance is improved, the amount of processes per core is reduced and better
reliability of the on-chip communication is assured by the multicore implementation. In the
current scenario, OEMs are moving towards multicore to exploit parallelism, to accommodate
more functions on one ECU and distribute them across the computational cores [1, 3]. In effect,
some of the task intensive ECUs catering to telematics, infotainment and power train are already
upgraded with multicore processors. Performance optimization of such multicore ECUs can be
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.6, December 2014
2
achieved by utilizing parallelism effectively for which, numerous runnables should be efficiently
scheduled for each core [3,4]. The operating system should have an efficient scheduling
mechanism to schedule the tasks without corrupting the shared data and without leaving any CPU
core idle at any running instant [5]. Without an optimal schedule, there can be considerable
variations in average task response times and logical correctness of the results [6]. Such
anomalies can cause instabilities in the physical system leading to performance degradation and
even safety hazards. In this paper, a hybrid dynamic scheduler is proposed for the most task
intensive engine control ECU.
2. CASE STUDY - ENGINE CONTROL UNIT
In this work, engine control unit is chosen as the target ECU for task scheduling, as it has
maximum number tasks to be executed both periodic and event driven and it has already been
implemented with multicore. Engine control unit is usually connected to a large cluster of sensors
like, intake air temperature sensor, engine coolant temperature sensor, intake manifold absolute
pressure (MAP) sensor, mass air flow sensor, throttle position sensor, crankshaft speed sensor,
camshaft sensor and knock sensor. It is connected to various actuators like idle speed motor,
electronic throttle body, fuel pressure regulator and fuel injector and delivery control. Basically
those are stepper motors and solenoids directly connected to the ECU [7]. For each sensor, there
has to be a task to receive the sensory signal after being conditioned, a task to process it as
required according to the control algorithm and another task to send appropriate signal to the
intended actuator. Each task has a large number of threads to be executed sequentially with data
dependency. Independent threads are executed in parallel by multiple cores. For each engine
ECU functionality like, air charge management, engine cooling management, battery
management, air fuel management or on-board diagnostics, a large number of inputs to be
received, parameters and local variables to be managed and many outputs are expected to be
delivered. Because of high level of interaction between the control functions, the shared data are
required to be protected efficiently [4, 6]. Three different task schedulers used are, synchronous
scheduler, asynchronous scheduler and background scheduler [7]. Synchronous scheduler is used
for tasks that need to be executed at certain crank teeth. Asynchronous scheduler also called the
time-base scheduler is executed just after the power up scheduler initialization. Background tasks
run, when the CPU is idle basically they are busy-wait loops [12, 13]. Besides that, various
interrupt service routines are executed to respond to hardware events. Right from the engine start
till stop of the vehicle, engine ECU runs with its software of several 1000 lines of code.
3. AUTOSAR ON MULTICORE SCHEDULING
According to AUTOSAR 4.0, there are certain limitations on multicore software implementation.
• The scheduling algorithms strictly assign tasks statically to cores to ensure deterministic
response for the real time critical tasks.
• The resource algorithm is not supported across cores. Resources can be shared between
tasks that are allocated to the same core but not among tasks/ISRs which are bound to
different cores.
OSEK counter and auto started alarms can be used to implement task activation mechanism. The
task synchronization issue is addressed by implementing schedule table. The Autosar schedule
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.6, December 2014
3
table shown in Figure.1. has certain defined set of expiry points. Each expiry point has certain
tasks to be activated, settings to be done for some events and offset from the start of the schedule
table [8]. OSEK counter drives the iteration over these expiry points on the schedule table. So one
tick on the counter corresponds to one tick on the schedule table. Constraints apply to the delays
between adjacent expiry points and the delay to the logical end of the schedule table. According
to Autosar, the hard real time safety critical tasks are scheduled statically to computational cores
as per the fixed priority assigned. In this static priority scheduling approach, the tasks have to be
partitioned well with the order of criticality and an appropriate priority assignment scheme has to
be adopted to assign priorities prior to run time, which is always a tedious job. The computational
cores are sometimes underutilized and the lower priority tasks often miss their deadline though
not the most safety critical ones. In this paper, a global dynamic priority approach has been
explored.
Figure.1. Schedule table for AUTOSAR ECU
4. THE PROPOSED SCHEDULER MODEL
Figure.2. Scheduler model
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.6, December 2014
4
The scheduler model shown in above Fig.2. has a combination of both global and partitioned
queue architecture. All the tasks arrive at the global queue, where the slack is calculated for each
and priorities are assigned dynamically. The task with least slack gets highest priority. Then the
three tasks pass on to three partitioned queues to utilize all the available cores. When a new task
arrives at the partitioned queue in the presence of previous task, a comparison happens between
their slack and tasks are arranged in ascending order of their slack in the queue with an effort to
meet the deadlines. In this simulation setup, a task set of 10 number of tasks are considered for an
asynchronous or timebase scheduler. The task attributes for the ith task are: {releasing instant ri,
WCET wi and period pi }, where WCET is the worst case execution time. Precedence constraint
is imposed on some of the tasks based on dependency. A tri-core processor implementation is
considered for these tasks to be scheduled for. The scheduled tasks are released for execution by
the dispatcher task which is characterized by a dispatching table of definite duration.
5. SCHEDULING PROBLEM
The scheduling problems are categorized by notation (α|β|γ) proposed by Graham and Blazewicz
[14,15]. This notation consists of three parts. The first part ‘α’ describes the processor
environment, the second part ‘β’ describes the task characteristics and constraints of the
scheduling problem and the last part ‘γ’ denotes the optimality criterion. In this simulation set up,
for a three processor environment, α=3. Since all the tasks are release time constrained and they
are periodic, period is the implied deadline for each instance and precedence constraint is also
imposed on some of the tasks, β=|release time, precedence & deadline constraint| and γ= Cmax,
the maximum completion time to achieve an optimal schedule.
6. WORKING OF THE PROPOSED MINIMUM SLACK FIRST ALGORITHM
At a new arriving instant at global queue,
• Calculate the slack of each task arrived .Where, Slack= Period-WCET.
• Sort the tasks in increasing order of their slack i,e S1< S2 <S3…….Sn.
• Assign priorities to these tasks dynamically by giving highest priority to the task with least
slack.
• If precedence constraint imposed on the task, Pass the task to a partitioned queue preferably
to the one where its precedence task has been allocated.
• If no precedence constraint, pass that task to a local queue based on early availability of that
CPU core.
• If :
the no. of tasks arrived at the global queue at a particular instant is > the no. of CPU
cores,
o Compare the total WCET of all the tasks at each partitioned queue.
o Assign the first task in the remaining list at global queue to the core that has least WCET.
• Else:
wait for the next new arriving instant.
At the local partitioned queue,
• If: new task arrives in the presence of previous task,
o If the precedence task of the new arrival is the last task waiting in the queue, no
comparison required.
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o Else
Compare the slack of the new task with the WCET of the previous task.
If: S new arrival < WCET previous task + Remaining WCET running task & Sprevious task> WCETnew
arrival ,
• Swap the waiting position of these tasks in the queue.
Else if : Snew arrival < WCETprevious task + Remaining WCETrunning task & Sprevious task<
WCETnew arrival ,
• Get the tasknew to migrate to another local queue whose CPU core is expected to
be available early, getting information from the global queue.
7. TASK ATTRIBUTES TABLE
Table.1. Task attributes table
The task attributes table given in above table. 1 has release time Ri, worst case execution time
WCET, period and static priorities assigned for each of the ten tasks considered [2, 9]. These are
the parameters used for static priority scheduling. In addition to these parameters, the precedence
constraints are considered for dynamic priority scheduling. The slack is the calculated parameter
based on which dynamic priorities are assigned. For example, at 0th
instant, four number of tasks
i,e T1, T3, T5 and T7 are released. So there could be only four levels of priorities that can be
assigned. These priorities are assigned at the global queue to dispatch the tasks to the local
partitioned queues based on their corresponding core’s early availabilities. The first instance of all
the tasks according to minimum slack based dynamic scheduling is shown in the last column of
the attributes table.
8. SEQUENCER TABLE AS PER STATIC PRIORITY
Figure.2. Sequencer table
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Fig.2 shows a sequencer table for the tasks to be executed in three computational cores in an
expected sequence as it is given. At every single unit of time the scheduler has to take the
decision in favor of three highest priority tasks among the ready list of tasks arrived as well as
tasks with remaining execution time. In the priority list, the smallest number indicates highest
priority for the most frequent task.
Figure. 3. Simulation result
9. IMPLEMENTATION OF DYNAMIC SCHEDULER AND RESULTS
Figure. 4. Simulation result
The simulation results are shown in the above fig. 3 and fig. 4. These result graphs are Gantt
charts of ten number of tasks being scheduled for three computational cores. Fig. 3 shows the
Gantt chart results of the simulation of static priority scheduling. In this simulation, few
noticeable features are there. Tasks T6, T9 and T10 being assigned with least priorities, are not
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getting scheduled and have missed their deadlines even for the first instance. T3 has migrated
from core3 to core2 to complete its WCET after being preempted by T2. Based on the parameter
attributes and constraints imposed on the tasks, both the static and the dynamic algorithms have
run through the global and partitioned queues one after the other. Fig. 4 shows the Gantt chart
results of the simulation of dynamic priority based minimum slack first scheduling. At every
arrival instant at the global queue, slack for each task is calculated and dynamic priorities are
assigned. For this dynamic priority scheduling, precedence constraints have been imposed on
certain tasks. Tasks with the precedence constraints are mostly collocated at a CPU core. At every
arrival instant at the partitioned queue, the slack of the new task is compared with the total WCET
of previous tasks and the currently running task. Either the tasks are sorted in ascending order of
their slack and scheduled for execution or tasks have been preempted and migrated to other
available core in case there is a probability of missing the deadlines. In the result Gantt chart, T6
has migrated from core2 to core3. All the tasks have satisfied their precedence constraints and all
have met with their deadlines. None of the CPU cores is idle at any point of time. So 100% CPU
utilization is achieved within the simulation duration. To minimize the preemption overhead, the
tasks are allowed to continue their execution unless there is a probability of missing the deadline.
Table 2 given below shows the number of periodic instances of each of the 10 tasks within the
simulation duration for both the static and dynamic scheduling and Table 3 shows the comparison
of performance parameters based on the results out of both static and dynamic scheduling run for
the given task set.
Table 2: Tasks with no of instances
Scheduling Methods T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Static 3 3 2 4 4 0 2 1 0 0
Dynamic 2 2 2 2 2 1 2 1 1 1
Table 3: parameter comparison
10. CONCLUSION
In this paper, a dynamic task scheduling algorithm has been proposed for multicore Engine
control ECU of Automotive electronic system. Engine control ECU being a safety critical, hard
real time system and highly task intensive, the stringent requirement is, all the tasks have to meet
their deadlines. Fixed static priority and partitioned task scheduling for multicore ECUs have
been suggested by AUTOSAR. While adhering to it, there is always a challenge in assigning
priorities to the tasks and high level of difficulty in partitioning the tasks by which certain CPU
cores remain under utilized [3, 8]. In this work, a model taskset with appropriate time attributes
has been tested both with static priority scheduling and the proposed dynamic priority algorithm,
where slack is the utilizing parameter. The performance parameters are compared for the results
of both the algorithms. It is observed that, in static priority scheduling, CPUs are highly utilized
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by higher priority tasks only and the lowest priority tasks are consistently missing their deadlines
while in dynamic priority case, there is a significant improvement in terms of missing deadlines
and there is a fair allocation across all priorities. Average response time, number of pre-emption
and migration have been improved considerably. Since slack is considered to assign dynamic
priorities and to calculate the relative deadlines, unless there is a probability of missing the
deadline, the task does not get preempted or migrated to other core. So the context switching
overhead is also reduced.
REFERENCES
[1] Yu Hua, Lei Rao, Xue Liu, Dan Feng “Co-operative and Efficient Real-Time Scheduling for
Automotive Communications”. IEEE international conference on Distributed Computing Systems
2014; ISBN-978-1-4799-5168-0; DOI- 10.1109/ICDCS.2014.22.
[2] Aurélien Monot, Nicolas Navet, Bernard Bavoux, and Françoise Simonot-Lion, “Multisource
Software on Multicore Automotive ECUs—Combining Runnable Sequencing”, IEEE Transactions
on Industrial Electronics, Vol. 59, No. 10, pp 3934-3942, October 2012
[3] Rajeshwari Hegde, Geetishree Mishra, K S Gurumurthy, “Software and Hardware Challenges in
Automotive Embedded Systems”, International Journal of VLSI design and Communication Systems
(VLSICS) Vol.2, No.3, pp 165-174, Sep 2011 DOI: 10.512/VLSIC.2011.2314.
[4] A. Monot, N. Navet, F. Simomot, and B. Bavoux. “Multicore scheduling in automotive ecus”. In
Proc. of The Embedded Real-Time Software and Systems (ERTS2), May 2010.
[5] N. Navet, A. Monot, B. Bavoux, and F. Simonot-Lion. “Multi-source and multicore automotive ecus:
Os protection mechanisms and scheduling”. In Proc. of IEEE Int’l Symposium on Industrial
Electronics, Jul. 2010.
[6] C. Aussagues, D. Chabrol, V. David, D. Roux, N. Willey, A. Tournadre, and M. Graniou. Pharos, “A
multicore os ready for safety-related automotive systems: results and future prospects”. In Proc. of
The Embedded Real-Time Software and Systems (ERTS2), May 2010.
[7] http://www.bosch motorsport.de/media/msd/ downloads/dokumentation/ steuergeraete_1/ Databook_
Engine_ Control_Units_2014.pdf
[8] AUTOSAR 4.0 specification, available at: www.autosar .org.
[9] Zhang Jie, Yang Fumin, Tu Gang, “A Dynamic Scheduling Model for Real-Time Tasks in Reliable
System” 2009 International Conference on Networks Security, Wireless Communications and Trusted
Computing.
[10] P. Leteinturier (Infineon Technologies). “Multi-core processors: Driving the evolution of automotive
electronics architectures”; http://www.embedded.com/design/multicore/, 2007.
[11] Tao Xie, Andrew Sung, Xiao Qin, “Dynamic Task Scheduling with Security Awareness in Real-Time
Systems” Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium
(IPDPS’05) 1530-2075, 2005.
[12] Anita Mittal, G.Manimaran, C.Siva Ram Murthy, “Integrated Dynamic Scheduling of Hard and QoS
Degradable Real-Time Tasks in Multiprocessor Systems” Journal of Systems Architecture, Vol. 46,
Issue-9, Pages-793-807, July 2000.
[13] G. Manimaran, C. Siva Ram Murthy, and K. Ramamritham. A new approach for Scheduling of
parallelizable tasks in real-time multiprocessor systems, Real-Time Systems, 15:39-60, July 1998.
[14] RL Graham, EL Lawler, JK Lenstra, A.H.G Rinnooy Kan - “Optimization and Approximation in
deterministic sequencing and Scheduling –A Survey” Annalysis of Discrete Mathematics, 5; 1977,
Pages 287-326.
[15] J Blazewicz, J K Lenstra, A.H.G Rinnooy Kan, “Scheduling Subject to resourse constraints:
classification and complexity” , Dicrete Applied Mathematics V-5; Jan 1983, Pages- 11-24.