Arithmetic circuits form an important class of circuits in
With the progress in the very large scale integration
(VLSI) circuit technology, many complex circuits are
made simple and easy.
Algorithms that seemed impossible to implement are
now easy to implement by interfacing of hardware and
software using VLSI.
So as to be familiar with the new technology and to
cope up with the electronic industry, we have chosen
this project as our mini project.
In this project an arithmetic unit based on IEEE
standard for floating point numbers will be
implemented on Spartan3 FPGA Board. The
arithmetic unit will consist of 32-bit processing unit
which allows various arithmetic operations such as,
Addition, Subtraction, Multiplication, Division and
Square Root, on floating point numbers.
From all these operations we have chosen addition
operation as a mini project in the existing year.
Synthesis of the unit for the FPGA board will be done
Floating-point operations are useful for computations
involving large dynamic range, but they require
significantly more resources than integer operations.
FPGAs offer reduced development time and costs
compared to application specific integrated circuits,
and their flexibility enables field upgrade and
adaptation of hardware to run-time conditions.
Our main objective for this standard is that an
implementation of a floating-point system confirming
to this standard “can be realized in software, entirely
in hardware, or in any combination of software and
As per IEEE-754 floating-point standard,
simple representation of floating point
uses binary fraction(F) and
Having the types of single precision(32
bit) & double precision(64 bit).
In single precision out of 32 bits a bit
is used for sign, 8 bits are used for
exponent(E) & 23 are for mantissa.
In double precision out of 64 bits a bit is
used for sign, 11 bits are used for
exponent(E) & 52 are for mantissa.
Representation of 1259.125
Now consider two parts, first is real part
before fraction point & other after
Representing them separately as
Now, we have to normalize it
i.e. (1.0011101011001) * 210
Here, 10 is exponent, biased exponent
is 137(10+127) 1.0011101011001 is
Sign Exponent Mantissa
0 10001001 0011101011001
1. Invalid Operation:-
Some arithmetic operations are invalid, such as a division by zero or
square root of a negative number.
The result of an invalid operation shall be a NaN (Not a number).
This exception should be signaled whenever the result of an arithmetic
operation is not exact due to the restricted exponent and/or precision
Two events cause the underflow to be signaled, tininess and loss of
Tininess is detected after or before rounding when a result lies between
±2Emin. Loss of accuracy is detected when the result is simply inexact or
only when a renormalizations loss occurs.
The overflow is signaled whenever the result exceeds the maximum value
that can be represented due to the restricted exponent range.
It is not signaled when one of the operands is infinity, because infinity
arithmetic is always exact.
1. Compare exponents. If the exponents are not
equal, shift the fraction with the smaller
exponent right and add 1 to its exponent;
repeat until the exponents are equal.
2. Add the fractions(significants).
3. If the result is 0, set the exponent to the
appropriate representation for 0 and exit.
4. If the fraction overflow occurs, shift right and
add 1 to the exponent to correct the overflow.
5. If the fraction is not normalized, shift left and
subtract 1 from the exponent until the fraction
6. Check the exponent overflow indicator, if
7. Round to the appropriate number of bits. If still
it is not normalized go back to step 4.
The main component for hardware
implementation of the project will be the
Spartan 3 FPGA development board.
Interfacing will be done by using JTAG
programmable with parallel or USB
The software used for the simulation of
the code will be Xilinx
Low-cost, high-performance logic solution for high-volume, consumer-oriented applications
Densities up to 74,880 logic cells
Up to 633 I/O pins
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18 single-ended signal standards
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Termination by Digitally Controlled Impedance
Signal swing ranging from 1.14V to 3.465V
Double Data Rate (DDR) support
DDR, DDR2 SDRAM support up to 333 Mb/s
Abundant logic cells with shift register capability
Wide, fast multiplexers
Fast look-ahead carry logic
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JTAG logic compatible with IEEE 1149.1/1532
Select RAM™ hierarchical memory
Up to 1,872 Kbits of total block RAM
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Digital Clock Manager (up to four DCMs)
Clock skew elimination
High resolution phase shifting
Eight global clock lines and abundant routing
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MicroBlaze™ and PicoBlaze™ processor, PCI®, PCI Express® PIPE Endpoint, and other IP cores