Upcoming SlideShare
×

# Final

476 views

Published on

Published in: Technology
1 Like
Statistics
Notes
• Full Name
Comment goes here.

Are you sure you want to Yes No
• Be the first to comment

Views
Total views
476
On SlideShare
0
From Embeds
0
Number of Embeds
1
Actions
Shares
0
4
0
Likes
1
Embeds 0
No embeds

No notes for slide

### Final

1. 1.  Arithmetic circuits form an important class of circuits in digital systems.  With the progress in the very large scale integration (VLSI) circuit technology, many complex circuits are made simple and easy.  Algorithms that seemed impossible to implement are now easy to implement by interfacing of hardware and software using VLSI.  So as to be familiar with the new technology and to cope up with the electronic industry, we have chosen this project as our mini project.
2. 2.  In this project an arithmetic unit based on IEEE standard for floating point numbers will be implemented on Spartan3 FPGA Board. The arithmetic unit will consist of 32-bit processing unit which allows various arithmetic operations such as, Addition, Subtraction, Multiplication, Division and Square Root, on floating point numbers.  From all these operations we have chosen addition operation as a mini project in the existing year.  Synthesis of the unit for the FPGA board will be done using XILINX-ISE.
3. 3.  Floating-point operations are useful for computations involving large dynamic range, but they require significantly more resources than integer operations.  FPGAs offer reduced development time and costs compared to application specific integrated circuits, and their flexibility enables field upgrade and adaptation of hardware to run-time conditions.  Our main objective for this standard is that an implementation of a floating-point system confirming to this standard “can be realized in software, entirely in hardware, or in any combination of software and hardware”.
4. 4.  As per IEEE-754 floating-point standard, simple representation of floating point uses binary fraction(F) and Exponent(E). i.e. N=F*2^E  Having the types of single precision(32 bit) & double precision(64 bit).  In single precision out of 32 bits a bit is used for sign, 8 bits are used for exponent(E) & 23 are for mantissa.
5. 5.  In double precision out of 64 bits a bit is used for sign, 11 bits are used for exponent(E) & 52 are for mantissa.  For example:- Representation of 1259.125 Now consider two parts, first is real part before fraction point & other after point. Representing them separately as (1259)10=(10011101011)2 (0.125)10=(0.001)2
6. 6.  Therefore (1259.125)2=(4EB)16=(10011101011.001)2  Now, we have to normalize it i.e. (1.0011101011001) * 210 Here, 10 is exponent, biased exponent is 137(10+127) 1.0011101011001 is mantissa. Sign Exponent Mantissa 0 10001001 0011101011001
7. 7. 1. Invalid Operation:-  Some arithmetic operations are invalid, such as a division by zero or square root of a negative number.  The result of an invalid operation shall be a NaN (Not a number). 2. Inexact:-  This exception should be signaled whenever the result of an arithmetic operation is not exact due to the restricted exponent and/or precision range. 3. Underflow:-  Two events cause the underflow to be signaled, tininess and loss of accuracy.  Tininess is detected after or before rounding when a result lies between ±2Emin. Loss of accuracy is detected when the result is simply inexact or only when a renormalizations loss occurs. 4. Overflow:-  The overflow is signaled whenever the result exceeds the maximum value that can be represented due to the restricted exponent range.  It is not signaled when one of the operands is infinity, because infinity arithmetic is always exact.
8. 8. 1. Compare exponents. If the exponents are not equal, shift the fraction with the smaller exponent right and add 1 to its exponent; repeat until the exponents are equal. 2. Add the fractions(significants). 3. If the result is 0, set the exponent to the appropriate representation for 0 and exit. 4. If the fraction overflow occurs, shift right and add 1 to the exponent to correct the overflow. 5. If the fraction is not normalized, shift left and subtract 1 from the exponent until the fraction is normalized. 6. Check the exponent overflow indicator, if necessary. 7. Round to the appropriate number of bits. If still it is not normalized go back to step 4.
9. 9.  The main component for hardware implementation of the project will be the Spartan 3 FPGA development board.  Interfacing will be done by using JTAG programmable with parallel or USB cables.  The software used for the simulation of the code will be Xilinx
10. 10.  Low-cost, high-performance logic solution for high-volume, consumer-oriented applications  Densities up to 74,880 logic cells  Up to 633 I/O pins  622+ Mb/s data transfer rate per I/O  18 single-ended signal standards  8 differential I/O standards including LVDS, RSDS  Termination by Digitally Controlled Impedance  Signal swing ranging from 1.14V to 3.465V  Double Data Rate (DDR) support  DDR, DDR2 SDRAM support up to 333 Mb/s  Logic resources  Abundant logic cells with shift register capability  Wide, fast multiplexers  Fast look-ahead carry logic  Dedicated 18 x 18 multipliers  JTAG logic compatible with IEEE 1149.1/1532  Select RAM™ hierarchical memory  Up to 1,872 Kbits of total block RAM  Up to 520 Kbits of total distributed RAM  Digital Clock Manager (up to four DCMs)  Clock skew elimination  Frequency synthesis  High resolution phase shifting  Eight global clock lines and abundant routing  Fully supported by Xilinx ISE® and WebPACK™ software development systems  MicroBlaze™ and PicoBlaze™ processor, PCI®, PCI Express® PIPE Endpoint, and other IP cores
11. 11. THANK YOU