In this paper, we have presented an ALU (Arithmetic and Logic Unit) with a control-signal gating technique for reducing the switching activity on datapath buses.
The main idea behind this logic is the control-signal gating technique that will detect the bus, which is not going to be used and it will turn on only that unit which is functioning and switch-off the module which is not functioning. Control-gating circuit employs a series of AND gate on the input bus line which is controlled by a decoder. We have compared the dynamic power of proposed ALU model with conventional ALU by considering target FPGA device Virtex-6 low power with speed grade -1L.
2. Table I. Function of ALU
Select
operation
Arithmetic
Operation
Select
operation
Logic
Operation
0000 Add 1000 OR
0001 Subtract 1001 AND
0010 Increment 1010 NOT
0011 Decrement 1011 EXOR
0100 Multiply 1100 Shift right
0101 Division 1101 Shift left
0110 Clear 1110 Rotate right
0111 Set 1111 Rotate left
Fig.2. Top level schematic of conventional ALU
Fig.3. Timing waveform of conventional ALU
III. PROPOSED ALU MODEL WITH CONTROL-SIGNAL GATING
A. Architecture and Functional of Proposed ALU
The architecture of proposed ALU is shown in Fig.4,
which consist of ALU with control-signal gating circuit.
Control-gating circuitry consist of a series of AND gate with
decoder, input of each AND gate is fed with output of decoder
to control the input bit line and input of decoder is connected
with Selection line of ALU. Selection line is used to select the
operation of ALU, which is also fed with OUTMUX of ALU.
Here, control-signal gating has been introduced to reduce the
switching activity of datapath, when one operation is running
and other is not. For example, when selection line is “0000”
then it will select the first AND gate of both input bit line and
it will switch on the first bit line of ALU and OUTMUX will
select the first output of ALU. Hence, by introducing this
technique we can reduce the switching activity of other fifteen
input bit line.
Fig.4. Architecture of proposed ALU
IEEE 2nd International Conference on Knowledge Collaboration in Engineering March 27- 28, 2015
3. B. Top level schematic (RTL) of proposed ALU
The top level schematic of proposed model is shown in
Fig.5.
Fig.5. Top level schematic of proposed ALU
C. Timing waveform of proposed ALU
The timing waveform for proposed model is shown in Fig.6.
Fig.6. Timing waveform of proposed model
IV. SIMULATION RESULTS
A. Power comparison
The dynamic and total power for conventional and proposed
model is calculated by Xilinx X’Power Analyzer tool
considering target FPGA Device Virtex-6 low power with
speed grade -1L, given in Table II.
Table II. Power comparison of both model
Parameter Conventional model Proposed model
Total power 1176 mW 1173 mW
Dynamic power 77 mW 74 mW
Quiescent Power 1099 mW 1099 mW
Hence, it can be inferred from the Table II and can be seen from
Fig. 7 that the proposed model consumes less dynamic power
than conventional model.
Fig.7. Dynamic power comparison of conventional and
proposed ALU model
B. Device Utilization Summary
Device Utilization Summary of both the model
(conventional as well as proposed) is shown in Fig.7 and Fig.8.
Fig.7. Device utilization summary of conventional model
Fig.8. Device utilization summary of proposed Model
77
74
72
74
76
78
Dynamic Power (mW)
Dynamic Power Comparison
Conventional Model Proposed Model
IEEE 2nd International Conference on Knowledge Collaboration in Engineering March 27- 28, 2015
4. V. CONCLUSION
Hence, we have designed, simulated and compared the result
of both the model using Xilinx Tool and it has been seen that the
ALU with control-signal gating techniques consumes less power
than conventional model. So, it can be concluded that the
proposed model can be utilized as power optimized technique to
reduce the switching activity on datapath buses. There are other
logic circuitry which can be developed and designed in future to
control the switching activity on datapath buses. Future work
includes the implementation of clock gating technique with
control-signal gating technique to reduce the unnecessary
switching activity of clock and datapath buses, when there is no
need of it.
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IEEE 2nd International Conference on Knowledge Collaboration in Engineering March 27- 28, 2015