1. Disclaimer
The Department of Electrical Engineering of the Eindhoven University of Technology accepts
no reponsibility for the contents of M.Sc. theses or practical training reports
Department of Electrical Engineering
Den Dolech 2, 5612 AZ Eindhoven
P.O. Box 513, 5600 MB Eindhoven
The Netherlands
http://w3.ele.tue.nl/nl/
Series title:
Master graduation paper,
Electrical Engineering
Commissioned by Professor:
Group / Chair:
Date of final presentation:
Report number:
by
Author:
Prof.dr.ir. P.G.M Baltus
Mixed-signal Microelectro
Low noise non-linear interference
suppression
March 20, 2013
Internal supervisors: dr. D. Milosevic, ir. E.J.G Janssen
T.H.M Derks

3. 1
Low noise non-linear interference suppression
T.H.M Derks
Department of Electrical Engineering, Mixed-signal Microelectronics group,
Eindhoven University of Technology, The Netherlands
Email: t.h.m.derks@student.tue.nl, tderks@gmail.com
Abstract—Non-linear interference suppression (NIS) is a tech-
nique to suppress a large known interferer at the frontend of an
RF receiver, to reduce its power consumption. This functionality
is obtained by adaptation of a nonlinear current transfer accord-
ing to the blocker amplitude. A previously developed NIS circuit
requires a low noise amplifier (LNA) before the circuit due to
poor noise performance. This paper introduces a different NIS
topology with the objective of improving the noise performance,
effectively incorporating the LNA into the NIS. This allows the
suppression to take place directly after the antenna, resulting
in maximum power reduction in the rest of the receiver chain.
The control requirements for suppression in the new circuit are
analyzed, as well as the consequences for the desired signal gain.
A harmonic balance simulation is performed that takes into
account memory effects in the circuit. The circuit suppresses
an interferer of -3 to 6dBm by 9 to 18dB while amplifying the
weak desired signal by 15dB. Suppression is limited at the target
frequency of 1.85GHz due to memory effects. The reason for the
limited suppression due to this phenomena is investigated and
various methods are proposed to further increase the suppression
performance. Further work needs to solve the matching challenge
and determine the absolute noise performance of the circuit.
Index Terms—Nonlinear filtering, nonlinear circuits, interfer-
ence suppression, low noise
I. INTRODUCTION
THE number of different wireless standards such as e.g.
WLAN, Bluetooth, GSM, UMTS and GPS supported by
handheld devices has been increasing steadily in recent years.
Therefore, the coexistence of multiple standards becomes an
increasingly important issue [1] [2]. Dealing with an extremely
strong interferer in the analog receiver front-end is typically
encountered in these coexistence situations. A co-located
transmitter is simultaneously active with a receiver at compa-
rable carrier frequencies. This strong interferer imposes large
dynamic range requirement on the receiver, which significantly
increases the power consumption of the receiver chain. The
suppression of the internally generated interferer by frequency
filtering is often inadequate, so time sharing concepts are often
used to circumvent the increase of dynamic range. However,
time sharing leads to a reduction of data throughput and
introduces a challenging synchronization requirement between
the data packets of different standards.
Non-linear interference suppression (NIS) [3] offers an
alternative solution to this problem. A non-linear transfer
function is applied to filter a signal based on amplitude,
independent of frequency. A prototype has been developed
that is able to suppress a -2 to 10 dBm Blocker by -40dB
while amplifying a weak desired signal. The suppression of
the interferer greatly reduces the dynamic range requirements
of the receiver chain. For maximum power conservation the
NIS circuit is located in the first stage of the receiver, directly
after the antenna where normally the low noise amplifier
(LNA) is situated. The noise performance of the NIS prototype
is not adequate to enable the circuit to also function as an
LNA, requiring an LNA between antenna and the NIS circuit.
This paper will introduce a different NIS topology with the
objective of improving the noise performance, integrating the
LNA into the NIS circuit.
The paper is organized in the following way. The remainder
of the introduction will explain the NIS concept and the circuit
implementation requirements to place it directly after the an-
tenna. In Section II, the causes for the bad noise performance
of the originally proposed version of the NIS are identified
and a new circuit topology is selected that aims for better
noise performance. Section III derives the transfer function
and the resulting signal characteristics. Simulations including
memory effects are performed and the noise performance of
the circuit is calculated. Section IV describes the origin of the
memory effects and explains the limited suppression of the
NIS circuit due to these phenomenon. Then, various methods
to improve the suppression performance are proposed. Finally,
the conclusions of the paper are presented in Section V.
A. NIS principle
This section will explain the mathematical background of
the NIS principle and is a summary of the first three pages of
paper in which the NIS concept was originally proposed [3]. A
linear amplifier does not change the spectrum of the input sig-
nal; it only increases the amplitude of the signal. A non-linear
amplifier, on the other hand, introduces higher harmonics and
intermodulation components in addition to the fundamental
component of the input signal. The non-linear transfer function
proposed for NIS produces only higher harmonics at the
output, while suppressing the fundamental component. The in-
and output spectrum for the above mentioned cases are shown
in figures 1a-c. When an input signal, consisting of a strong
and a weak signal, is put into the same transfer, the weak
signal is processed differently than the strong signal. This
functionality enables the removal of a strong undesired signal
in the vicinity of a weak desired signal based on amplitude
discrimination. The generated higher harmonics can be filtered
away, because the frequency difference is large.
This input signal is defined as x(t) and consists of a strong

4. 2
Fig. 1. a) Transfer function of a linear amplifier. b) Non-linear transfer
function that compresses the fundamental and introduces higher harmonics.
c) NIS transfer function that fully compresses the fundamental component for
a specific signal amplitude. d) Small signals accompanying the large signal
are not suppressed but amplified. source: [3].
blocking interferer Int(t) and a weak signal s(t).
Int(t) = ALS(t)sin[ωLSt + φLS(t)]
s(t) = ASS(t)sin[ωSSt + φSS(t)]
x(t) = Int(t) + s(t)
|ASS| << |ALS|
The signal x(t) is fed into the nonlinear circuit, whose
input-output relationship is described by the memoryless
function y = f(x). The effective gain of the fundamental
component of the strong signal GLS is defined by the Fourier
series:
a1 =
1
(ALS · π)
π
−π
f(ALS sin(θ)) sin(θ) dθ (1)
b1 =
1
(ALS · π)
π
−π
f(ALS sin(θ)) cos(θ) dθ (2)
GLS = a2
1 + b2
1
The strong input signal is fully suppressed when GLS is
zero. For a memoryless point-symmetric transfer function, b1
is equal to zero. For a1 to be zero, a transfer shape with three
zero transitions is required. The weak signal accompanying
the strong signal undergoes a different processing. The gain
of this signal GSS is a function of the probability density
function (PDF) of the sinusoidal Int(t), ALS and f(x):
GSS =
ALS
−ALS
∂f(x)
∂x
· PDFsin(x)) dx (3)
When a memoryless nonlinear function is excited with a
large and a small sinusoidal signal, the output around the
fundamental is equal to [4]:
y(t) = GLS · Int(t) +
1
2
[ALS ·
∂GLS
∂ALS
+ GLS] · s(t)
+
1
2
[ALS ·
∂GLS
∂ALS
− GLS] · IM(t) (4)
In addition to the fundamental component of the strong
and weak signal an intermodulation component IM(t) is
introduced which is defined by:
IM(t) = ASS(t)sin[(2ωLS − ωSS)t + 2φLS(t) − φSS(t))]
When GLS is equal to zero, the amplitude of the intermodula-
tion component becomes equal to the amplitude of the desired
signal. This leads to the conclusion that the signal at frequency
ωss is mirrored to (2ωLS − ωSS). Vice versa the same effect
occurs, i.e. the content at (2ωLS − ωSS) is mirrored to ωSS.
This inverse spectrum mirroring leads to the translation of the
input noise at (2ωLS −ωSS) into the signal band. This leads to
noise doubling even of the input noise is not thermal. In case
of a signal being present at (2ωLS − ωSS), crosstalk arises.
B. Circuit requirements
The NIS concept can be applied to suppress an internally
generated interference in a multi-radio system. Suppressing
the large interferer greatly reduces the dynamic range and
linearity requirements of the receiver and thereby its power
consumption. Figure 2 shows the system level diagram of the
implementation in a receiver.
Fig. 2. System diagram showing the application of the NIS principle in
a multi-radio transceiver. The changing amplitude is tracked based on the
combination of a feed-forward and a feedback loop. source: [3].
The NIS circuit needs to adapt its transfer to the interferer
amplitude to satisfy the suppression conditions. Because the
interferer signal is generated locally, its magnitude is known
and is fed into the NIS control block. Since the coupling
between the antennas is susceptible to environmental changes,
a feedback loop to the NIS control is also present. A mixer
multiplies the input and output of the NIS circuit, thereby pro-
viding the cross-correlation between these signals. Since the

5. 3
interferer signal is dominant, minimizing the cross-correlation
equates to maximizing the suppression of the interferer.
The NIS circuit is located directly after the antenna which
requires it to have all the properties of an LNA. The basic
performance parameters of an LNA are gain, noise figure
(NF), impedance matching and linearity requirements like
P1db and IP3. When there is no interferer present the NIS
circuit needs to operate as a normal linear amplifier. In this
mode it is essential for the circuit to provide performance
comparable to a classical LNA because the circuit does not
add the suppression functionality.
The first version of the NIS circuit [5] suppresses a -2 to
10dBm blocker by 40dB, while the weak desired signal is
amplified by 6.5 to 10dB. When the circuit is set to classical
amplifier mode it provides 17dB of voltage gain. The noise
figure in the NIS and amplifier mode are 12.8dB and 8.4dB
respectively. Since LNA’s with similar specs and technology
usually have a NF of 2db [6] this is obviously a strong
disadvantage of this NIS concept. Especially in amplifier
mode the circuit adds significant noise preventing the practical
usability. The most important properties of the NIS circuit are
the suppression and noise figure. Additional gain can always
be supplied in a succeeding circuit. However a significant
amount of gain in the first stage of an Rx chain is generally
required to reach a low overall noise figure.
II. TOPOLOGY
This paper will focus on improving the noise performance
of the originally provided NIS circuit by a different circuit
topology. First, the reason for the poor noise performance
of the first NIS circuit is examined. This is caused by three
factors. The circuit consists of a linear amplifier (common-
gate) and a clipper circuit (common-source) whose output
currents are subtracted to generate the required transfer (Figure
3). Subtracted currents that cancel each other do not provide
any gain while the independent noise sources of the transis-
tors add up. Furthermore, the noise performance cannot be
optimized for amplifier and NIS mode simultaneously due to
different noise optima for the common-source and common-
gate amplifiers applied in the circuit. A compromise between
noise performance for both modes has been made, which limits
noise performance in both cases. Finally, to match the input
impedance to 50Ω the transistors M3 and M4 are connected
as diodes. Therefore the output current of the transconductor
is only half the input current.
To reduce the difference between NIS and amplifier mode
for better noise optimization the transfer will be made with
three clippers consisting solely of common-source amplifiers.
The three transitions of the transfer function are all imple-
mented by clipping differential pairs. The three differential
pairs can be interconnected in various ways as shown in Figure
4
Three differential pairs can be placed in parallel interleaving
the polarity (Figure 4a). A bias voltage between the input
nodes on the outer two pairs shifts the transition point. This
results in the transfer function with three zero transitions
required for NIS operation. The transfer of the NIS can be
Vin-
Vout-Vout+
Vbias, CG Vbias, CG
Vin+
Vdd
Venv
Iclip
M1
M5 M6
M2
M4M3
M7
Iout+ Iout-
Vbias, DP Vbias, DP
C1 C2
Clipper
Linear amplifier Linear amplifier
Fig. 3. Circuit diagram of the previous NIS circuit.
Vin+ Vin-
-1/2Voff +1/2Voff
Voff
0Vc
0 0
VcVc Vc
Vc
Vc
Parallel Series "Gilbert-cell"a) b) c)
d)
Fig. 4. Three possible NIS topologies by interconnecting the differential
pairs in various ways. The topologies are shown in (a-c) composed of the
differential pair model shown in (d).
changed by adjusting the bias voltage on the outer pairs,
shifting the transition point.
By placing the differential pairs in series (Figure 4b), current
reuse is possible which reduces power consumption. Assuming
no overlap in the transitions of the differential pairs, the
series topology will consume three times less power than the
parallel connected topology for the exact same transfer. The
noise of the series connected topology will also be lower,
since only one tail current contributes to the output noise
instead of three in the parallel case. The drawback of putting
transistors in series is the reduced voltage headroom. For
correct operation of the differential pair all transistors should
be kept in saturation. The applied bias voltages reduce the
maximum input voltage sweep of the circuit. The third option
(Figure 4c) is a combination between the parallel and series
topology. This topology is also known as the Gilbert-cell.
However, in this implementation it has modified offsets at
the different differential pairs. It has the same current-reuse

6. 4
properties as the parallel case but the transistors are only
stacked by two instead of three. Table I shows a comparison
of the three topologies. The Gilbert-cell topology is clearly
the preferred choice since it has better noise performance than
the parallel circuit. It also has identical properties as the series
connected topology with more voltage headroom.
TABLE I
COMPARISON OF THE TOPOLOGIES.
Circuit Voltage headroom Current consumption Noise
Parallel ++ - -
Series – + +
Gilbert-cell + + +
Aclip
Vc
Input (V)
Vc
Output(A)
-
a) b)
Fig. 5. Control difference in adjusting the transfer shape of the NIS. a)
Amplitude of the clipper(Aclip) is adjusted. b) Outer transition points are
shifted by the bias voltage (Vc).
The previous NIS circuit controls the transfer shape by
changing the clipper amplitude Aclip (Figure 5a). In com-
bination with the fixed linear amplifier, the transfer shape is
adjusted to reach suppression for various interferer amplitudes.
The new topology controls the shape of the transfer function
differently. The outer transitions of the transfer can be moved
by adjusting the bias voltage (Vc) on the input signal of the
differential pairs (Figure 5b). Since the control mechanism
for adapting the transfer has changed fundamentally, the
requirements to reach suppression will be calculated in the
next section.
A. Simplified Characteristics
In this section the requirements for suppression are calcu-
lated for the new topology. Then the desired-signal gain is
derived in the suppression condition. First the circuit transfer
is simplified by making all three transitions of the differential
pairs very steep. This results in the transfer function described
by f(x) and is shown in Figure 6a.
f(x) =
⎧
⎪⎪⎪⎪⎨
⎪⎪⎪⎪⎩
−A if x < −b
A if -b < x < 0
−A if 0 < x < b
A if x >b
0 otherwise
Because the transfer function is uneven the large signal gain
GLS defined by 1 can be divided into four equal parts which
can be expressed as:
GLS =
4
(ALS · π)
π/2
0
f(ALS sin(θ)) sin(θ) dθ
Filling in the transfer function f with α = arcsin( b
ALS
)
yields:
GLS =
4A
(ALS · π)
(
α
0
sin(θ) dθ −
π/2
α
sin(θ) dθ)
For the large signal gain to be zero, the first and second
integral need to be equal.
α
0
sin(θ) dθ =
π/2
α
sin(θ) dθ
From this equality, α can be determined as:
− cos(θ)|
α
0 = − cos(θ)|
π/2
α
−1 = −2 cos(α) =⇒ α = 2/3π
This α gives the following value for b:
b = ALS · sin(α) = 1/2
√
3 · ALS (5)
Now that the transfer function requirements for suppression
are known the desired signal gain can be calculated in this
situation. The gain for the desired signal previously mentioned
in the introduction is:
GSS =
ALS
−ALS
∂f(x)
∂x
· PDFsin(x)) dx
Filling in the transfer function f(x):
GSS =
ALS
−ALS
2A(δ(x + b) − δ(x) + δ(x − b))
dx
π A2
LS − x2
Solving the integral using (5):
GSS = 2A(
2
πALS
−
1
πALS
+
2
πALS
) =
6A
πALS
For the normalised case where ALS = A this results in a
gain of:
20 · log
6
π
= 5.62dB (6)
The calculated results for suppression and desired signal
gain are verified by doing a quasi-static analysis. The input
signal x(t) defined in the introduction is fed into the transfer
function f(x). The result is shown in Figure 6. The figure
shows the waveforms of the signals as well as the spectrum
for the in- and output of the transfer. It is clear in the figure
that the interferer signal is fully suppressed at the output. The
desired signal power is increased from -40dB to -34.3dB. This
corresponds closely with the calculated small signal gain of
5.62dB in formula 6. The output spectrum shows the spectrum
mirroring by the intermodulation component at (2ωLS −ωSS).
The amplitude of this component is equal to the desired signal
as expected.

7. 5
a) Transfer function
Input voltage
Outputcurrent
−ALS 0 ALS
−Atail
0
Atail
b) Input and output waveforms
Time
Inputvoltage
0 TLS/2 TLS
−ALS
0
ALS
0 TLS/2 TLS
−Atail
0
Atail
Outputcurrent
c) Input spectrum
Frequency
Magnitude(dB)
ωLS 3ωLS 5ωLS 7ωLS
−40
−30
−20
−10
0
d) Output spectrum
Frequency
Magnitude(dB)
ωLS 3ωLS 5ωLS 7ωLS
−40
−30
−20
−10
0
Fig. 6. Input output transfer function of the ideal transfer (a). Input signal
(solid) and resulting output signal (dashed) in time domain (b) and frequency
domain (c,d).
III. NIS CIRCUIT
In this section, the proposed NIS circuit topology will be
analyzed. First, the DC transfer function of the circuit is
derived. Then the large- and small-signal characteristics are
calculated and verified by a quasi-static analysis. A harmonic
balance simulation is performed to analyse the suppression
performance including memory effects. Finally, the noise
performance of the circuit is examined.
A. Circuit transfer
The DC-transfer of the proposed NIS circuit shown in
Figure 7 will be derived. The transistors in the circuit are
modeled using the square-law model:
Ids(Vgs) =
K
2
·
W
L
(Vgs − VT )2
· step(Vgs − Vt) (7)
First the bottom differential pair is analysed.
vGM1
= Vbias + Vin/2
vGM2
= Vbias − Vin/2
vS = Vbias − VT −
L
K W
Itail −
V 2
in
4
Itail =
K
2
W
L
[(vGSM1
− VT )2
+ (vGSM2
− VT )2
]
This results in the following drain currents for the bottom
pair.
IdM1
=
K
2
W
L
L
KW
Itail +
V 2
in
4
+
Vin
2
2
(8)
IdM2
=
K
2
W
L
L
KW
Itail +
V 2
in
4
−
Vin
2
2
(9)
By taking the derivative of these equations and equating to
zero, the value of Vin for which either M1 or M2 are entirely
switched off (Vin,off ) are found, which results in:
Vdd
Vout+ Vout-
Vin+ Vin-
M6M5M4M3
M1 M2
Vc
+
−
+
−Vm1 Vm2
7.75nH 7.75nH1.03pF
4mA
Fig. 7. Circuit diagram of the NIS circuit.
Vin,off = ±
2Itail
K W
L
(10)
So equations 8 and 9 are valid in the region |V in| <
|Vin,off |. Outside this region the tail current flows entirely
through transistor M1 or M2.
An identical analysis applies to the top differential pairs.
Since the control voltage Vc is applied between the differential
input nodes, the transfer function is shifted by this voltage. The
output currents of the bottom amplifier are the tail currents for
the top amplifiers. This results in the following drain currents
for the transistors in the top pair.
IdM3
=
K
2
W
L
L
K W
IdM1
+
(Vin + Vc)2
4
+
(Vin + Vc)
2
2
IdM4
=
K
2
W
L
L
K W
IdM1
+
(Vin + Vc)2
4
−
(Vin + Vc)
2
2
IdM5
=
K
2
W
L
L
K W
IdM2
+
(Vin − Vc)2
4
+
(Vin − Vc)
2
2
IdM6
=
K
2
W
L
L
K W
IdM2
+
(Vin − Vc)2
4
−
(Vin − Vc)
2
2
TABLE II
TRANSISTOR PARAMETERS
Parameter Value:
VT 0.5 V
K’ 200 μA/V 2
W 100 μm
L 180 nm

8. 6
The drain currents for all transistors as a function of V in
are shown in Figure 8. The transistor parameter values are
given in table II. The parameters VT and K are fixed process
parameters of a 180nm process. The choice for the transistor
size parameters will be explained later. Combining the four
output branches gives the differential output current of the
circuit:
Iout = (Id4 + Id6) − (Id3 + Id5)
The higher harmonics are suppressed in the output voltage
by using an LC-tank for the load impedance. This is important
since the voltage drop of the higher harmonics would force the
top transistors out of saturation. The inductor size is chosen
to be the maximum coil size that still acts like an inductor
at the target frequency. The size of the inductor is 7.75nH
and has an estimated Q factor of 10. The resonance frequency
of the LC tank is set equal to the desired signal frequency
of 1.835Ghz. The capacitance value for resonance at this
frequency is determined by Formula 11. The impedance at
resonance frequency is calculated by Formula 12.
C =
1
L · (2πf)2
= 1.03pF (11)
R =
Q
C/L
= 900Ω (12)
−0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8
0
0.5
1
1.5
2
2.5
3
3.5
4
Input Voltage(V)
Current(mA)
Circuit currents
Id1
Id2
Id3
Id4
Id5
Id6
Fig. 8. Transistor drain currents for control voltage (Vc) of 0.57.
The analysis is only valid if all the transistors are kept
in saturation. This imposes a restriction on the maximum
signal amplitude of the input signal. The maximum differential
input voltage where all the transistors are still in saturation is
1.25Vpp.
The circuit transfer adapts to the interferer amplitude to
satisfy the suppression conditions. Figure 9 shows the dif-
ferential output current for various control voltages. For V c
voltages below 0.5V an overlap occurs in the switching of the
differential pairs, compressing the amplitude of the transfer
function. The gain of the small signal would scale inversely
by the amplitude of the signal in the case of no overlap, see
formula II-A. Therefore, moderate amounts of overlap do not
impose a problem for the desired signal gain. When the overlap
is increased further, the transfer function is compressed more
heavily, which greatly diminishes the gain of the circuit.
−1 −0.5 0 0.5 1
−4
−3
−2
−1
0
1
2
3
4
Input voltage (V)
Differentialoutputcurrent(mA)
0.6V
0.5V
0.4V
0.3V
0.2V
0.15V
Fig. 9. Differential output current for various control voltages (Vc).
B. Circuit Characteristics
In section II-A, the suppression conditions have been calcu-
lated for the simplified transfer function. An identical analysis
will be applied to the actual circuit transfer derived in the
previous section. Because the transfer function definition is
more complicated, the analysis cannot be done analytically.
Instead, the suppression conditions and the small signal gain
are computed numerically.
0 0.2 0.4 0.6 0.8 1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Blocker amplitude ALS (V)
ControlvoltageVb(V)
Ideal NIS
NIS circuit
Fig. 10. Vb control voltage as function of Blocker amplitude ALS for ideal
case and in circuit implementation.
A Matlab function is constructed that calculates GLS nu-
merically. The control voltage that minimizes GLS is found

9. 7
by applying a root finding on this function. To show the effect
of the real transfer function on the V bias control voltage, both
the ideal and the circuit case voltage are shown in Figure 10. In
the top range of the blocker amplitude the control voltage has a
small, almost constant deviation. In the lower range the control
voltage starts to deviate more from the ideal reference. This
is due to high overlap in the switching pairs which changes
the shape of the transfer function.
−0.5 0 0.5
−0.05
−0.04
−0.03
−0.02
−0.01
0
0.01
0.02
0.03
0.04
0.05
Input voltage (V)
Smallsignalcurrentgain(mA/V)
Fig. 11. Small-signal gain of the NIS circuit versus the applied large-signal
voltage value. The large signal can be considered a constant variation in bias
point of the circuit. The dashed line indicates the probability of each small-
signal bias point at suppression.
Figure 11 shows the derivative of the transfer function. The
large signal can be considered a continuously changing bias
voltage for the small-signal gain. The desired signal gain is
the weighted average of the derivative at these bias points. In
the plot the probability density function for the bias points is
drawn by the dashed line in the suppression condition.
Figure 12 shows the desired signal gain at suppression
for the simplified and the real circuit transfer. The desired
signal gain of the circuit is smaller than in the ideal case.
Because the transitions are slower not the whole switching
range is utilized in the outer transitions at suppression. For
smaller blocker amplitude the transitions start to overlap. This
compresses the amplitude of the transfer function (Figure 9).
The gain of the desired signal stays constant at first due
the fact that the small signal scales inversely to the signal
amplitude in the ideal case (Formula II-A). When the overlap
increases the transfer function is compressed more heavily.
This dramatically decreases the desired signal gain. Increasing
the transistor width improves the transition speed of the
transfer function, resulting in significant gain for lower input
signal amplitudes. However, the maximum usable transistor
width is limited due to memory effects which will be explained
in Section IV.
The same quasi-static analysis as performed in section II-A
is applied on the DC-transfer of the circuit (Figure 13). The
0 0.2 0.4 0.6 0.8 1
−20
−10
0
10
20
30
40
50
Blocker amplitude ALS (V)
Desiredsignalgain(db)
Ideal NIS
NIS circuit
Fig. 12. Desired signal gain vs blocker amplitude ALS for ideal and circuit
case.
output spectrum shows there is large signal suppression and
amplification of the small desired signal. The desired signal
gain is scaled down by 2dB from the ideal case, because the
outer transitions do not use the whole transfer function range
at suppression.
a) Transfer function
Input voltage (V)
Outputcurrent(mA)
−0.5 0 0.5
−4
−2
0
2
4
b) Input and output waveforms
Time
Inputvoltage(V)
0 TLS/2 TLS
−1
−0.5
0
0.5
1
0 TLS/2 TLS
−4
−2
0
2
4
Outputcurrent(mA)
c) Input spectrum
Frequency
Magnitude(dB)
ωLS 3ωLS 5ωLS 7ωLS
−40
−30
−20
−10
0
d) Output spectrum
Frequency
Magnitude(dB)
ωLS 3ωLS 5ωLS 7ωLS
−40
−30
−20
−10
0
Fig. 13. Input output transfer function of the circuit transfer (a). Input signal
(solid) and resulting output signal (dashed) in time domain (b) and frequency
domain (c,d).
C. Harmonic Balance simulation
Until now the simulations did not include memory ef-
fects, resulting in infinite suppression. Since memory effects
influence the suppression performance significantly at the
frequency of 1.85GHz, a Harmonic Balance (HB) simulation
is applied to improve the accuracy of the simulation. The tran-
sistors are modelled with a level-1 model with the parameters
of the 180nm process defined in Sedra & Smith Appendix B-9
[7]. The harmonic balance simulation order is 21 for both the

10. 8
large and small signal with a maximum mixing order of 4. A
power source is connected to the circuit with an impedance of
50Ω. Since the circuit is not matched and the circuit impedance
is a large mostly imaginary impedance, the full voltage swing
is at the input. Therefore the input power is adjusted by -6dB
assuming a 50 percent voltage drop for a matched circuit to
50Ω.
A HB simulation is performed in ADS for an interferer
amplitude of 6dBm with a 40dB lower desired signal. The
optimal control voltage (V c) is automatically found by using
a gradient optimizer tool that minimizes the large signal gain.
The time signals of the drain currents of transistor M1, M3
and M4 are shown in Figure 14. It is clear there is a delay
between the drain current of M1 and M4 while the switching
of the drain current between M4 and M3 is not delayed. This
memory effect limits the large signal suppression of the circuit
and is stronger for small signals.
Fig. 14. Drain currents of left part of NIS circuit (transistor M1,M3,M4).
Figure 15 shows the large- and small-signal gain as a
function of input power. The small-signal gain stays constant
in the 6dBm to -3dBm range. For lower input powers heavy
overlap occurs which lowers the gain as predicted in the DC-
analysis. The large signal gain is lowest for the highest input
power. The memory effects that reduce the suppression are
larger for smaller input amplitudes. When the input signal
amplitude is smaller the circuit transitions slower, spending
more time in the biasing conditions where the transistor has
a low gm. In linear amplifier mode, the gain of the circuit is
24dB.
The large signal gain of the circuit scales with the desired
signal gain of the circuit. Therefore the suppression of the
system is defined as:
Suppression = GSS/GLS (13)
The control voltage of the circuit needs to be controlled to
have maximum suppression. Figure 16 shows the suppression
of a 6dBm input voltage for the applied control voltage Vc.
There is one optimum suppression point when Vc is equal
to approximately 1/2
√
3 times the interferer amplitude. The
suppression becomes negative for small control voltages of
Vc. For small control voltages the outer transitions clip on the
−15 −10 −5 0 5
−5
0
5
10
15
20
RF input power(dBm)
Gain(dB)
G
LS
G
SS
Fig. 15. Large signal gain (GLS)and small signal gain (Gss) at suppression
versus input power.
high and low parts on the input signal. Because the gain of the
desired signal is made in these parts, this clipping results in
negative suppression. The suppression performance increases
for lower frequencies, because memory effects are reduced.
Table III shows the suppression for a 6dBm interferer for
various operating frequencies. The suppression improves by
20dB for each frequency division of ten.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
−10
−5
0
5
10
15
20
Vc control voltage (V)
Suppression(dB)
Fig. 16. Suppression versus control voltage Vc for RF input power of 6dBm.
TABLE III
SUPPRESSION FOR A 6DBM INTERFERER
Input frequency Suppression
1.85GHz −19.6dB
185MHz −40.2dB
18.5MHz −59.7dB
1.85MHz −80.6dB

11. 9
D. Noise
The circuit topology was selected for the estimated low
noise performance. In this section the noise figure of the circuit
is derived. The input referred noise figure is defined as:
NF =
SNRin
SNRout
=
Nin + Ncircuit
A
Nin
= 1 +
Ncircuit
A · Nin
(14)
Nin is the input noise, A the voltage gain of the desired
signal and Ncircuit the generated noise of the circuit. The input
noise is better known as the noise floor, at room temperature
defined by [6]:
Noisefloor = 174 + 10log(Bandwidth)dBm (15)
This analysis is incorrect since it calculates the squared
output current noise induced from the squared input noise
voltage, instead of the input to output noise power. For a
correct noise calculation a more complex transistor model
than level-1 is needed where current actually flows into the
transistor. Furthermore, the noise matching of the highly non-
linear circuit will pose a challenge as well. The noise figures
values are not quantitatively correct, but the analysis still gives
insight in the noise contributions of the circuit and the relative
nature of the noise figure.
Fig. 17. Small-signal circuit diagram with the thermal noise sources of the
transistors. The contributions of the marked noise sources to the output noise
are shown in Figure 18 .
Figure 17 shows the small-signal diagram of the system
with the thermal noise sources of the transistors. It does not
include the channel and gate-inducted noise as well as the
noise doubling that takes place in the circuit due to the non-
linear transfer. The noise power of each noise source is defined
by the gm of the transistor (formula 16).
|ink|2
= 4kTγgmk (16)
First the output noise current of each branch is determined.
Then, the noise output power of the differential output current
−0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8
0
0.2
0.4
0.6
0.8
1
1.2
x 10
−22
Input voltage
PSD(W/Hz)
Tail current
Bottom pair
Left top pair
Right top pair
Total
Fig. 18. Noise contributions of the circuit. The dashed line indicates the
probability of each small-signal bias point at suppression.
is calculated. The contributions of the output noise from each
differential pair and the tail current are shown in Figure 18.
When the differential pair divides the current equally among
the branches, the noise output of the tail current becomes zero.
The noise added by the differential pair is at a maximum at this
point. The noise component of the differential pair becomes
zero when one of the transistors is off. There is no added noise
at this point because there is only one path for the current
to flow through. The noise figure is calculated by taking the
weighted average of the small-signal bias points induced by
the large signal. The probability density function of the sine,
that is used for the weighting, is displayed with the dashed
line.
−6 −4 −2 0 2 4 6
0
5
10
15
RF input power (dBm)
Noisefigure(dB)
2mW
4mW
8mW
12mW
16mW
20mW
Fig. 19. NF versus RF input power for various power consumption values.
When the ratio Itail/W is kept equal the suppression of
the circuit is not influenced, this is explained in Section IV-A.
A larger tail current gives a greater signal gain, reducing the
noise figure at the cost of power consumption. Figure 19 shows
the noise figure versus the input power for various DC power

12. 10
consumptions for a Itail/W ratio of 40A/m. The noise figure
in amplifier mode is plotted in Figure 20.
2 4 6 8 10 12 14 16 18 20
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
Power consumption (mW)
Noisefigure(dB)
Fig. 20. NF in amplifier mode vs power consumption.
IV. MEMORY EFFECTS
The memory effects of the circuit cause hysteresis in the
transfer function that limits the large-signal suppression per-
formance. This section examines the cause of the hysteresis
and clarifies the mathematical background for the limited
suppression. After understanding the origins of the limited
suppression, methods to increase the suppression performance
of the NIS are proposed.
A. Hysteresis
The hysteresis of the transfer function is shown in Figure 21.
Mainly the middle zero transition is delayed which is clearly
visible in the transfer. The hysteresis is caused by the charge
and discharge of the parasitic capacitors connected to node
VM1 through the transistor M1 (Figure 7). Unloading this
node can be considered an RC circuit. However, since the
circuit is highly nonlinear the current through transistor M1
and the derivative of the voltage swing at the node VM1 are
continuously changing. The top transistors also turn on and
off, changing the total capacitance to the node. Therefore the
hysteresis is very hard to model in an absolute sense.
TABLE IV
PARASITIC CAPACITANCE OF A MOSFET TRANSISTOR
Saturation Off
Cgd W(2/3LCox + LovCox) WLovCox
Cgs WLovCox WLovCox
There are however clear relative observations. When the
ratio between W and Itail is kept constant, the DC transfer
shape is conserved and scales with the magnitude of Itail. This
can be derived from the output current formulas calculated
in Section III-A. Furthermore, the hysteresis of the circuit
does not change when the ratio between W and Itail is
kept constant. The discharging time of node Vm1 remains
Fig. 21. Hysteresis in the transfer function (local phase shift).
unchanged since the discharge current and the parasitic capaci-
tances (Table IV), scale with Itail and W respectively, keeping
the unload time constant. These two observations give a clear
result: when Itail and W are increased by the same factor, the
suppression performance stays identical. This allows power to
be traded for increased signal gain and lowered noise figure.
The suppression performance is a function of the process
parameters, transistor size, interferer power and operating
frequency. The parasitic capacitance should be kept as small
as possible by minimizing the transistor size parameters W
and L. Therefore, L is selected to be the minimum transistor
length of the process. The width of the transistor is a tradeoff
between the DC-transfer shape and parasitic capacitance size.
It should be large enough such that no heavy overlap occurs
since that dramatically decreases the desired-signal gain, as
explained in Section III-B. Enlarging W increases the parasitic
capacitance which decreases the suppression performance for
a constant tail current. A smaller transistor process would
decrease the hysteresis since it has lower capacitances and
therefore a higher intrinsic frequency.
B. Limited suppression
The hysteresis in the circuit causes limited suppression. To
understand the reason for limited suppression by hysteresis,
the Fourier series integrals are calculated for the simplified
transfer function f(x) with a phase shift for the transition at
Vin is zero. Figure 22 and 23 display the integral of the a1 and
b1 component with and without hysteresis for the simplified
transfer function f(x) defined in Section II-A. The green area
is shifted to the red area. The a1 integral can be kept zero
by changing the control voltage. When the control voltage
is increased the marked transitions shift towards each other.
This decreases the value of the integral which compensates
the change due to the hysteresis. The b1 integral can not
be compensated with the control voltage. When the control
voltage is increased the marked transitions shift towards each
other, but the area of the integral does not change. The
suppression performance can be calculated for this simplified
model of the hysteresis effect.
Figure 24 shows the modelled LS suppression and the actual
suppression of the circuit as a function of phase shift at the
zero transition. Due to the instant transitions in the simplified

13. 11
g(θ) = f(ALS sin(θ)) sin(θ)g(Θ)
Fig. 22. Graphical view of the argument (g(θ)) of the Fourier series integral
a1 (1) with and without hysteresis. The green area is shifted to the red area
in the case of hysteresis.
h(θ) = f(ALS sin(θ)) cos(θ)
h(Θ)
Fig. 23. Graphical view of the argument (h(θ)) of the Fourier series integral
b1 (2) with and without hysteresis. The green area is shifted to the red area
in the case of hysteresis.
transfer, the Fourier series components change more than in
the circuit. This shows in the figure, the suppression of the
simplified model is lower for the same phase shift.
There are methods to increase the suppression performance
of the circuit. Two solution categories are distinguished: ex-
ternal and internal phase compensation methods. The external
compensation method adjusts the signals applied to the inputs
of the circuit, while the internal method adds components at
strategic places into the circuit.
C. External phase compensation
The transition at the middle zero crossing is delayed, while
the outer transitions are not. This can be compensated by
shifting the input signal on the top pairs along with the shift
0 5 10 15 20
0
20
40
60
80
100
120
Phase (degrees)
Suppression(dB)
Simplified
Circuit
Fig. 24. Modelled suppression and actual suppression for various phase shifts
of the zero transition.
present in the zero transitions of the output signal. This shifts
the complete output signal resulting in identical suppression
performance as a memoryless circuit. This hypothesis is val-
idated with a voltage-controlled voltage source between the
input signal of the bottom and top pairs. The phase shift
between the input voltage of the bottom and top pair is varied
while keeping the gain unity. In figure 25 the suppression is
plotted versus the phase shift for various input powers. It is
clear that the suppression performance can be improved by
adjusting the phase of the input signal between the top and
bottom pairs.
−18 −16 −14 −12 −10 −8 −6
15
20
25
30
35
40
45
50
55
60
65
Phase (Degrees)
Suppression(dB)
-3dBm
-2dBm
-1dBm
0dBm
1dBm
2dBm
3dBm
4dBm
5dBm
6dBm
Fig. 25. Suppression versus phase shift between the input signal of bottom
and the top pairs for various input powers.
Figure 26 shows the transfer function when the phase is
adjusted for suppression. The hysteresis at the zero transition
is still the same, but hysteresis is also introduced in the outer
transitions. This results in the same output signal as in the
memoryless case, only phase-shifted. This is more clear when
the transfer function is shown as a function of the voltage

14. 12
of the top pairs in Figure 27. This proves that phase shift is
not intrinsically bad for suppression performance. The actual
implementation of the phase shift in the RF receiver chain is a
challenge. The input impedance of the bottom and top pairs are
purely imaginary. This induces an additional phase shift which
is also dependent on the interferer amplitude. Furthermore, the
phase shift needs to be generated without adding too much
noise. This is a difficult task, since the desired signal coming
from the antenna is weak.
Fig. 26. Hysteresis for the transfer function for external phase compensation.
Fig. 27. Hysteresis for the transfer function for external phase compensation
relative to input signal of the top pair.
The desired signal does not need to be present at the bottom
differential pair. The desired signal gain even increases when it
is not present at the bottom pair since it supplies negative gain
(Figure 11). Because the large interferer signal is known, it is a
possibility to generate the phase-shifted version for the bottom
pair. The amplitude of the signal can also be maximized for
smaller signals. Applying the maximum signal amplitude gives
better performance due to faster switching of the bottom pair.
This reduces the overlap of the differential pairs for smaller
signal amplitudes.
D. Internal phase compensation
There are possibilities to compensate for the hysteresis
inside the circuit. The capacitance at node VM1 can be
compensated with a negative capacitance to the gate of M1.
However, the needed negative capacitance that compensates
for the hysteresis is found to be equal to -50fF. Using (17),
this requires an inductor of 148nH at 1.85GHz, which is far
too big to realize on-chip.
jωL =
−1
jωC
⇒ L =
1
ω2C
(17)
Another option to increase the suppression is accomplished
by placing capacitors over the gate-drain nodes of the top
pairs (Figure 28). The top pairs transitions are delayed due
to the extra capacitance, inducing the phase shift required for
higher suppression. The resulting hysteresis plot is shown in
Figure 29. The hysteresis of the circuit depends on the transfer
shape of the circuit. Therefore the capacitor value required
to reach maximum suppression is dependent on the interferer
amplitude. Figure 30 shows the suppression as a function
of capacitor value for various input powers. A minimum
suppression of 20dB over the -3 to 6dBm input power range
is feasible with a fixed capacitor value. To reach higher
suppression values, the capacitor should be adjusted to the
input power.
When there is no voltage swing at the drain nodes due to
the output voltage swing, the current output is the same as
without the added capacitors. However, when the load LC-tank
induces a voltage swing at the output nodes, the addition of
the capacitors compresses the transfer function. This reduces
the desired signal gain of the circuit. The reduced gain is
dependent on the capacitor size and the output voltage swing.
The voltage swing at the drain nodes could be removed by
implementing a folded cascode.
Vdd
Vout+ Vout-
Vin+ Vin
M6M5M4M3
M1 M2
Vc
+
−
+
−
Fig. 28. Capacitances added to the top pairs in the NIS circuit.
As already mentioned, the hysteresis and consequently
the LS suppression depend on the transfer shape. The tail
current can be selected to get the same transfer shape for
a different interferer amplitude. The output currents of the

15. 13
Fig. 29. Hysteresis for the transfer function for internal phase compensation.
40 60 80 100 120 140 160
10
20
30
40
50
60
70
Capacitance (fF)
Suppression(dB)
-3dBm
-2dBm
-1dBm
0dBm
1dBm
2dBm
3dBm
4dBm
5dBm
6dBm
Fig. 30. Suppression versus capacitance capacitance value (C) for a tail
current of 4mA.
bottom differential pair (formula 8 and 9) can be combined as
18.
Idiff,b =
K
2
W
L
· Vin
L
KW
Itail +
V 2
in
4
(18)
Itail = a2
Itail Vin = aV in (19)
Idiff,b =
K
2
W
L
· a · Vin
L
KW
a2 · Itail +
(a · Vin)2
4
(20)
Idiff,b = a2
·
K
2
W
L
· Vin
L
KW
Itail +
V 2
in
4
(21)
When Itail and Vin are scaled by (19) and put into (20), the
transfer shape is identical but scaled by the tail current (21).
Because Vc scales equally to Vin and the drain currents of the
bottom pair scale proportionally to the tail current, an identical
analysis applies to the drain currents of the top pairs. When the
current scales with the square of the input signal amplitude, the
DC transfer shape is identical. However, the charging currents
changed while the capacitor values stayed constant. Yet the
charge and uncharge times are identical because the voltage
changes at the nodes are also different. The overdrive voltage
scales with the root of the tail current. Therefore the voltages
variations at node VM1 and VM2 scale equally with the input
signal. The total energy in a capacitor is defined by formula 22.
The charging current scales equally with the required energy
in the capacitor for the voltage swing. This results in the
same charge and discharge times, keeping the hysteresis and
suppression performance equal.
W =
1
2
CV 2
(22)
To verify this statement Figure 31 shows the suppression
versus Tail current for various input powers. For a change in
input power of -6db, the tail current is approximately divided
by four which corresponds to this theory.
0 1 2 3 4 5
0
10
20
30
40
50
60
70
Itail (mA)
Suppression(dB)
-3dBm
-2dBm
-1dBm
0dBm
1dBm
2dBm
3dBm
4dBm
5dBm
6dBm
Fig. 31. Suppression versus tail current (Itail) for capacitance value (C) of
65fF.
Figure 32 shows the effect of the phase compensation tech-
niques on the desired signal gain. Applying the top capacitors
significantly reduces the gain of the circuit when the LC tank
voltage sweep is present at the output. When the tail current
is adjusted to have maximum suppression for a fixed capacitor
value the gain is suppressed even more. It is not possible
to improve the gain by scaling up the tail current and the
transistor width. When scaling the circuit, the top capacitors
need to be increased, which has a net effect of decreasing the
desired signal gain.
The external phase compensation method only decreases
the gain slightly. The external phase correction method that
applies the generated large signal at the bottom pair, increases
the gain significantly. It also supplies gain for a much greater
input power range, because the overlap of the differential pairs
is reduced.
V. CONCLUSION
The previous NIS circuit was able to suppress an interferer
by 40db, but had poor noise performance, requiring an LNA
preceding the circuit with a large dynamic range. A new
circuit topology with improved noise properties is analysed
to incorporate the LNA into the NIS circuit. This allows
suppression to take place in the first stage of the receiver,
directly after the antenna. By suppressing the interferer in

16. 14
−3 −2 −1 0 1 2 3 4 5 6
0
5
10
15
20
25
RF input power (dBm)
Desiredsignalgain(dB)
Normal
Ext Phase
Int Phase(Cap)
Int Phase(Itail)
Ext Phase(generated)
Fig. 32. Effect of the phase compensation techniques on the desired signal
gain
the first stage of the receiver, the dynamic range requirements
are reduced for all the succeeding parts of the receiver chain,
maximizing the reduction in power consumption. The circuit
suppresses an interferer of -3 to 6dBm by 9 to 18dB while
amplifying the weak desired signal by 15dB. Although the
suppression is lower than in the previous circuit, the sup-
pression is sufficient to reduce the power consumption of the
rest of the receiver chain significantly. When the signal is
suppressed by 10dB the power consumption needed to process
the signal is reduced by 90 percent. For a suppression of 20dB
this power reduction rises to 99 percent. The suppression of
the circuit is limited at the target frequency due to memory
effects. Four methods have been proposed to counter these
memory effects to improve the suppression performance at
high frequencies. The actual implementation of some of these
techniques imposes new design challenges. However, it proves
that phase shift in the circuit is not intrinsically bad for
suppression performance. Furthermore, power can be traded
for increased gain and improved noise figure by equally scaling
the tail current and transistor width without influencing the
suppression performance.
VI. FUTURE WORK
The input impedance of the NIS circuit needs to be matched
to the antenna. Matching the non-linear circuit for different
signal amplitudes for both NIS and amplifier mode operation
is a difficult task which needs to be examined. The noise
performance of the circuit depends on the matching of the
circuit. When the circuit matching is realized, the actual noise
performance of the circuit can be calculated to get an absolute
value for the noise figure. The external phase compensation
that generates the interferer for the bottom pair seems the most
attractive. The method increases the suppression performance,
the desired signal gain and the input power range of the
interferer that can be suppressed. It does however require the
generation of the phase-shifted interferer signal.
REFERENCES
[1] S. Sheng, “Rf coexistence - challenges and opportunities,” in Radio
Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE, June 2011,
pp. 1–1.
[2] J. Zhu, A. Waltho, X. Yang, and X. Guo, “Multi-radio coexistence: Chal-
lenges and opportunities,” in Computer Communications and Networks,
2007. ICCCN 2007. Proceedings of 16th International Conference on,
2007, pp. 358–364.
[3] E. Janssen, H. Habibi, and D. Milosevic, “Interference Suppression in
Multi-Radio Transceivers by Exploiting a Nonlinearity,” Internal docu-
ment of MsM group at TU/e, pp. 1–13, 2012.
[4] N. M. Blachman, “Band-pass nonlinearities,” Information Theory, IEEE
Transactions on, vol. 10, no. 2, pp. 162–164, Apr.
[5] E. J. G. Janssen, D. Milosevic, and P. G. M. Baltus, “A 1.8ghz amplifier
with 39db frequency-independent smart self-interference blocker suppres-
sion,” in Radio Frequency Integrated Circuits Symposium (RFIC), 2012
IEEE, June, pp. 97–100.
[6] B. Razavi, RF Microelectronics, 2nd ed. New York: Prentice Hall, 1998.
[7] A. Sedra and K. C. A. Smith, Microelectronic circuits, 6th ed. New
York: Oxford University Press, 2011.