This document discusses VLSI implementation of Montgomery modular multiplication for cryptographic applications. It proposes a configurable carry-save adder architecture to reduce the number of clock cycles needed for Montgomery multiplication. The architecture can perform either one three-input carry-save addition or two serial two-input carry-save additions. It also discusses the Advanced Encryption Standard (AES) algorithm for encryption and decryption. AES is based on substitution-permutation networks and involves key expansion, initial/final rounds, and intermediate rounds of sub bytes, shift rows, mix columns and add round key transformations.