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8085 Microprocessor Architecture
&
Pin configuration
MCA 1ST YEAR 2ND SEMESTER 2020
Paper: MCA 203
Dr. Utpal Nandi
Dept. of Computer Science
VIDYASAGAR UNIVERSITY
8085 Microprocessor Architecture & Pin configuration
• Pin configuration of 8085
• Limitations of 8085
• Internal Architecture of 8085
• 8085 Single board Microcomputer System
Pin configuration of 8085
8-bit general purpose μp
Capable of addressing 64 k of memory
Has 40 pins
Requires +5 v power supply
Can operate with 3 MHz clock
Pin configuration of 8085
All the signals can be classified into
Six groups –
1. Address Bus
2. Data Bus
3. Control & Status signals
4. Power signal & frequency
signals
5. Externally initiated signals
6. Serial I/O ports
Address & data bus
• 8085 μp consists of 16 signal pins use as address bus.
• Divide into 2 part: A15 – A8 (upper)
AD7 – AD0 (lower).
– A15 – A8 : Unidirectional, known as ‘high order address’.
– AD7 – AD0 : bidirectional and dual purpose (address and data placed
once at a time).
– AD7 – AD0 also known as ‘low order address’.
– To execute an instruction, at early stage AD7 – AD0 uses
as address bus and alternately as data bus for the next
cycle.
– The method to change from address bus to data bus
known as ‘bus multiplexing’.
Control & Status signals
This group of signal includes-
 Two control signals (RD’ & WR’)
 Three status signals (IO/M’ , S1 & S0)
 One special signal (ALE)
• RD’ – Read (active low). To indicate that the I/O or memory
selected is to be read and data are available on the bus.
• WR’ – Write (Active low). This is to indicate that the data available
on the bus are to be written to memory or I/O ports.
• IO/M’ – To differentiate I/O operation or memory operations.
– ‘0’ - indicates a memory operation.
– ‘1’-indicates an I/O operation.
– IO/M’ combined with RD and WR to generate I/O and memory control
signals.
Control and Status Signals.
•S1 and S0: Status signals, similar to IO/M, can identify various
operations as shown on the following table :
Control & Status signals
•ALE (Address Latch Enable) signal :
ALE used to de-multiplex address/data bus
Active high signal - generated to show the start of 8085 operation.
When transition 1-to-0: indicate that lines AD7-AD0
(AD7-AD0 = A7-A0) act as address lines.
Power signal & frequency signals
 Vcc : +5 V power supply
 Vss : Ground reference
 X1 & X2 : A crystal is connected at
these two pins. The frequency is
divided by two.
Therefore, to operate a system at 3
MHz, the crystal should have a
frequency of 6 MHz.
 CLK OUT : This signal is used as the
system clock for other devices.
Externally initiated Signals including Interrupt
Externally initiated Signals including Interrupt
RESET IN’ : When the signal on this pin goes low,
the program counter is set to zero.
the buses are tri-sated.
MPU is reset.
RESET OUT : This signal is used to reset other
devices.
Serial I/O ports
The 8085 has two signals to implement the
serial transmission:
 SID: Serial Input Data
 SOD: Serial Output Data
Limitations of 8085
• The low order address bus is multiplexed with the
data bus. The buses need to be de-multiplexed.
• Appropriate control signals need to be generated
to interface memory and I/O with the 8085.
De-multiplexed Address & Data bus with Control Signals
Internal Architecture of 8085
• It includes-
– ALU
– Timing & Control Unit
– Instruction Register and Decoder
– Register Array
– Interrupt Control
– Serial I/O Control
8085Single board Microcomputer System
Reference Book
“Microprocessor Architecture, Programming
and Applications with 8085”, 5thEdition,
Prentice Hall
by
Ramesh S. Goankar
END

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3. MCA-203 (Architecture pin configuration).pptx

  • 1. 8085 Microprocessor Architecture & Pin configuration MCA 1ST YEAR 2ND SEMESTER 2020 Paper: MCA 203 Dr. Utpal Nandi Dept. of Computer Science VIDYASAGAR UNIVERSITY
  • 2. 8085 Microprocessor Architecture & Pin configuration • Pin configuration of 8085 • Limitations of 8085 • Internal Architecture of 8085 • 8085 Single board Microcomputer System
  • 3. Pin configuration of 8085 8-bit general purpose μp Capable of addressing 64 k of memory Has 40 pins Requires +5 v power supply Can operate with 3 MHz clock
  • 4. Pin configuration of 8085 All the signals can be classified into Six groups – 1. Address Bus 2. Data Bus 3. Control & Status signals 4. Power signal & frequency signals 5. Externally initiated signals 6. Serial I/O ports
  • 5. Address & data bus • 8085 μp consists of 16 signal pins use as address bus. • Divide into 2 part: A15 – A8 (upper) AD7 – AD0 (lower). – A15 – A8 : Unidirectional, known as ‘high order address’. – AD7 – AD0 : bidirectional and dual purpose (address and data placed once at a time). – AD7 – AD0 also known as ‘low order address’. – To execute an instruction, at early stage AD7 – AD0 uses as address bus and alternately as data bus for the next cycle. – The method to change from address bus to data bus known as ‘bus multiplexing’.
  • 6. Control & Status signals This group of signal includes-  Two control signals (RD’ & WR’)  Three status signals (IO/M’ , S1 & S0)  One special signal (ALE) • RD’ – Read (active low). To indicate that the I/O or memory selected is to be read and data are available on the bus. • WR’ – Write (Active low). This is to indicate that the data available on the bus are to be written to memory or I/O ports. • IO/M’ – To differentiate I/O operation or memory operations. – ‘0’ - indicates a memory operation. – ‘1’-indicates an I/O operation. – IO/M’ combined with RD and WR to generate I/O and memory control signals.
  • 7. Control and Status Signals. •S1 and S0: Status signals, similar to IO/M, can identify various operations as shown on the following table :
  • 8. Control & Status signals •ALE (Address Latch Enable) signal : ALE used to de-multiplex address/data bus Active high signal - generated to show the start of 8085 operation. When transition 1-to-0: indicate that lines AD7-AD0 (AD7-AD0 = A7-A0) act as address lines.
  • 9. Power signal & frequency signals  Vcc : +5 V power supply  Vss : Ground reference  X1 & X2 : A crystal is connected at these two pins. The frequency is divided by two. Therefore, to operate a system at 3 MHz, the crystal should have a frequency of 6 MHz.  CLK OUT : This signal is used as the system clock for other devices.
  • 10. Externally initiated Signals including Interrupt
  • 11. Externally initiated Signals including Interrupt RESET IN’ : When the signal on this pin goes low, the program counter is set to zero. the buses are tri-sated. MPU is reset. RESET OUT : This signal is used to reset other devices.
  • 12. Serial I/O ports The 8085 has two signals to implement the serial transmission:  SID: Serial Input Data  SOD: Serial Output Data
  • 13. Limitations of 8085 • The low order address bus is multiplexed with the data bus. The buses need to be de-multiplexed. • Appropriate control signals need to be generated to interface memory and I/O with the 8085.
  • 14. De-multiplexed Address & Data bus with Control Signals
  • 15. Internal Architecture of 8085 • It includes- – ALU – Timing & Control Unit – Instruction Register and Decoder – Register Array – Interrupt Control – Serial I/O Control
  • 17. Reference Book “Microprocessor Architecture, Programming and Applications with 8085”, 5thEdition, Prentice Hall by Ramesh S. Goankar
  • 18. END