The document discusses the 8085 microprocessor architecture and pin configuration. It contains the following key points: 1. The 8085 has 40 pins that are divided into groups for the address bus, data bus, control signals, power/clock, interrupts, and serial I/O. 2. The address bus is multiplexed with the lower data lines, requiring demultiplexing. Control signals like RD, WR are used to indicate read/write operations. 3. The internal architecture of the 8085 includes an ALU, registers, interrupt and serial I/O control, and timing/control units. 4. Examples are given of memory access cycles and communication between the 8085 and external memory

1. 8085 Microprocessor Architecture
&
Pin configuration
MCA 1ST YEAR 2ND SEMESTER
Paper No. MCA-203
Paper name: Microprocessor
Dr. Utpal Nandi
Dept. of Computer Science
VIDYASAGAR UNIVERSITY

2. 8085 Microprocessor Architecture & Pin configuration
• Pin configuration of 8085
• Limitations of 8085
• MPU Communication
• Internal Architecture of 8085
• 8085Single board Microcomputer System

3. Pin configuration of 8085
8-bit general purpose μp
Capable of addressing 64 k of memory
Has 40 pins
Requires +5 v power supply
Can operate with 3 MHz clock

4. Pin configuration of 8085
All the signals can be classified into
Six groups –
1. Address Bus
2. Data Bus
3. Control & Status signals
4. Power signal & frequency
signals
5. Externally initiated signals
6. Serial I/O ports

5. Address & data bus
• 8085 μp consists of 16 signal pins use as address bus.
• Divide into 2 part: A15 – A8 (upper)
AD7 – AD0 (lower).
– A15 – A8 : Unidirectional, known as ‘high order address’.
– AD7 – AD0 : bidirectional and dual purpose (address and data placed
once at a time).
– AD7 – AD0 also known as ‘low order address’.
– To execute an instruction, at early stage AD7 – AD0 uses
as address bus and alternately as data bus for the next
cycle.
– The method to change from address bus to data bus
known as ‘bus multiplexing’.

6. Control & Status signals
This group of signal includes-
 Two control signals (RD’ & WR’)
 Three status signals (IO/M’ , S1 & S0)
 One special signal (ALE)
• RD’ – Read (active low). To indicate that the I/O or memory
selected is to be read and data are available on the bus.
• WR’ – Write (Active low). This is to indicate that the data available
on the bus are to be written to memory or I/O ports.
• IO/M’ – To differentiate I/O operation or memory operations.
– ‘0’ - indicates a memory operation.
– ‘1’-indicates an I/O operation.
– IO/M’ combined with RD and WR to generate I/O and memory control
signals.

7. Control and Status Signals.
•S1 and S0: Status signals, similar to IO/M, can identify various
operations as shown on the following table :

8. Control & Status signals
•ALE (Address Latch Enable) signal :
ALE used to de-multiplex address/data bus
Active high signal - generated to show the start of 8085 operation.
When transition 1-to-0: indicate that lines AD7-AD0
(AD7-AD0 = A7-A0) act as address lines.

9. Power signal & frequency signals
 Vcc : +5 V power supply
 Vss : Ground reference
 X1 & X2 : A crystal is connected at
these two pins. The frequency is
divided by two.
Therefore, to operate a system at 3
MHz, the crystal should have a
frequency of 6 MHz.
 CLK OUT : This signal is used as the
system clock for other devices.

10. Externally initiated Signals including Interrupt

11. Externally initiated Signals including Interrupt
• An interrupt is a hardware-initiated subroutine CALL.
• When interrupt pin is activated, an ISR will be called,
interrupting the program that is currently executing.
Pin Subroutine Location
TRAP 0024
RST 5.5 002C
RST 6.5 0034
RST 7.5 003C
INTR *
Note: * the address of the ISR is determined by the external hardware.

12. Externally initiated Signals including Interrupt
• INTR input is enabled when EI instruction is
executed.
• The status of the RST 7.5, RST 6.5 and RST 5.5
pins are determined by both EI instruction and
the condition of the mask bits in the interrupt
mask register.

13. Externally initiated Signals including Interrupt
RESET IN’ : When the signal on this pin goes low,
the program counter is set to zero.
the buses are tri-sated.
MPU is reset.
RESET OUT : This signal is used to reset other
devices.

14. Serial I/O ports
The 8085 has two signals to implement the
serial transmission:
 SID: Serial Input Data
 SOD: Serial Output Data

15. Limitations of 8085
• The low order address bus is multiplexed with the
data bus. The buses need to be de-multiplexed.
• Appropriate control signals need to be generated
to interface memory and I/O with the 8085.

16. Generating Control Signals

17. De-multiplexing Address/Data Lines
Mr. Utpal Nandi, Dept. of Computer Science, Vidyasagar University

18. De-multiplexed Address & Data bus with Control Signals

19. MPU Communication
Figure : Moving data form memory to MPU using instruction MOV C, A
(code machine 4FH = 0100 1111)

20. MPU Communication
1. The μp placed a 16 bit memory address from PC
(program counter) to address bus.
– The high order address, 20H, is placed at A15 – A8.
– the low order address, 05H, is placed at AD7 - AD0 and ALE is
active high.
– Synchronously the IO/M is in active low condition to show it is a
memory operation.
2. Then, active low control signal, RD, is activated so
as to activate read operation; it is to indicate that
the MPU is in fetch mode operation.

21. MPU Communication
3. The active low RD signal enabled the byte
instruction, 4FH, to be placed on AD7 – AD0 and
transferred to the MPU. While RD high, the data
bus will be in high impedance mode.
4. The machine code, 4FH, will then be decoded in
instruction decoder. The content of accumulator
(A) will then copied into C register.

22. Internal Architecture of 8085

23. Internal Architecture of 8085
• It includes-
– ALU
– Timing & Control Unit
– Instruction Register and Decoder
– Register Array
– Interrupt Control
– Serial I/O Control

24. 8085Single board Microcomputer System

25. END