This paper presents a genetic based approach to the partitioning and mapping of multicore SoC cores over a NoC system that uses mesh topology. The proposed algorithm performs the partitioning and mapping by reducing communication cost and minimizing power consumption by placing those intercommunicated cores as close as possible together. A program developed in C++ in which the provided specification of the multicore MPSoC system captures all data dependencies before any start of the design process. Experimental results of several multimedia benchmarks demonstrates that the genetic-based approach able to find different satisfied implementations to the problem of partitioning and mapping of MPSoC cores over mesh-based NoC system that satisfies design goals.
A FLEXIBLE SOFTWARE/HARDWARE ADAPTIVE NETWORK FOR EMBEDDED DISTRIBUTED ARCHIT...csijjournal
Embedded platforms are projected to integrate hundreds of cores in the near future, and expanding the
interconnection network remains a key challenge. We propose SNet, a new Scalable NETwork paradigm
that extends the NoCs area to include a software/hardware dynamic routing mechanism. To design routing
pathways among communicating processes, it uses a distributed, adaptive, non-supervised routing method
based on the ACO algorithm (Ant Colony Optimization). A small footprint hardware unit called DMC
speeds up data transfer (Direct Management of Communications). SNet has the benefit of being extremely
versatile, allowing for the creation of a broad range of routing topologies to meet the needs of various
applications. We provide the DMC module in this work and assess SNet performance by executing a large
number of test cases.
TEST-COST-SENSITIVE CONVOLUTIONAL NEURAL NETWORKS WITH EXPERT BRANCHESsipij
It has been proven that deeper convolutional neural networks (CNN) can result in better accuracy in many
problems, but this accuracy comes with a high computational cost. Also, input instances have not the same
difficulty. As a solution for accuracy vs. computational cost dilemma, we introduce a new test-cost-sensitive
method for convolutional neural networks. This method trains a CNN with a set of auxiliary outputs and
expert branches in some middle layers of the network. The expert branches decide to use a shallower part
of the network or going deeper to the end, based on the difficulty of input instance. The expert branches
learn to determine: is the current network prediction is wrong and if the given instance passed to deeper
layers of the network it will generate right output; If not, then the expert branches stop the computation
process. The experimental results on standard dataset CIFAR-10 show that the proposed method can train
models with lower test-cost and competitive accuracy in comparison with basic models.
An overview on application of machine learning techniques in optical networksKhaleda Ali
This document provides an overview of machine learning techniques applied to optical networks. It discusses how optical networks have become more complex with the introduction of technologies like coherent transmission and elastic optical networks. This increased complexity motivates the use of machine learning to analyze network data and make decisions. The document surveys existing work on machine learning applications in optical communications and networking. It aims to introduce researchers to this field and propose new research directions to further the application of machine learning to optical networks.
Noise Tolerant and Faster On Chip Communication Using Binoc ModelIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Network clustering is an important technique used in many large-scale distributed systems. Given good design and implementation, network clustering can significantly enhance the system\'s scalability and efficiency. However, it is very challenging to design a good clustering protocol for networks that scale fast and change continuously. In this paper, we propose a distributed network clustering protocol SDC targeting large-scale decentralized systems. In SDC, clusters are dynamically formed and adjusted based on SCM, a practical clustering accuracy measure. Based on SCM, each node can join or leave a cluster such that the clustering accuracy of the whole network can be improved. A big advantage of SDC is it can recover accurate clusters from node dynamics with very small message overhead. Through extensive simulations, we conclude that SDC is able to discover good quality clusters very efficiently.
In network aggregation techniques for wireless sensor networks - a surveyGungi Achi
This document provides a comprehensive survey of in-network aggregation techniques for wireless sensor networks. It begins by defining in-network aggregation and classifying approaches into those with and without data size reduction. It identifies the key components of in-network aggregation as routing protocols, aggregation functions, and data representation. It reviews theoretical limits of aggregation and discusses open issues. The document aims to provide an updated view of in-network aggregation and motivate future research in this area.
Estimation of Optimized Energy and Latency Constraint for Task Allocation in ...ijcsit
In Network on Chip (NoC) rooted system, energy consumption is affected by task scheduling and allocation
schemes which affect the performance of the system. In this paper we test the pre-existing proposed
algorithms and introduced a new energy skilled algorithm for 3D NoC architecture. An efficient dynamic
and cluster approaches are proposed along with the optimization using bio-inspired algorithm. The
proposed algorithm has been implemented and evaluated on randomly generated benchmark and real life
application such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark
and has been compared with the existing mapping algorithm spiral and crinkle and has shown better
reduction in the communication energy consumption and shows improvement in the performance of the
system. On performing experimental analysis of proposed algorithm results shows that average reduction
in energy consumption is 49%, reduction in communication cost is 48% and average latency is 34%.
Cluster based approach is mapped onto NoC using Dynamic Diagonal Mapping (DDMap), Crinkle and
Spiral algorithms and found DDmap provides improved result. On analysis and comparison of mapping of
cluster using DDmap approach the average energy reduction is 14% and 9% with crinkle and spiral.
This document summarizes research on 3D network-on-chip architectures. It begins by introducing the benefits of 3D integrated circuits for reducing wire lengths and improving performance. It then surveys several existing 3D NoC architectures:
1) Symmetric NoC which treats intra-layer and inter-layer hops identically, incurring high overhead.
2) NoC-Bus Hybrid which uses a bus for single-hop vertical links to reduce hops.
3) Ciliated 3D Mesh which restricts switches to layers and adds cores per switch, lowering bandwidth.
4) True 3D NoC Router which embeds vertical links directly in crossbars for seamless routing.
The
A FLEXIBLE SOFTWARE/HARDWARE ADAPTIVE NETWORK FOR EMBEDDED DISTRIBUTED ARCHIT...csijjournal
Embedded platforms are projected to integrate hundreds of cores in the near future, and expanding the
interconnection network remains a key challenge. We propose SNet, a new Scalable NETwork paradigm
that extends the NoCs area to include a software/hardware dynamic routing mechanism. To design routing
pathways among communicating processes, it uses a distributed, adaptive, non-supervised routing method
based on the ACO algorithm (Ant Colony Optimization). A small footprint hardware unit called DMC
speeds up data transfer (Direct Management of Communications). SNet has the benefit of being extremely
versatile, allowing for the creation of a broad range of routing topologies to meet the needs of various
applications. We provide the DMC module in this work and assess SNet performance by executing a large
number of test cases.
TEST-COST-SENSITIVE CONVOLUTIONAL NEURAL NETWORKS WITH EXPERT BRANCHESsipij
It has been proven that deeper convolutional neural networks (CNN) can result in better accuracy in many
problems, but this accuracy comes with a high computational cost. Also, input instances have not the same
difficulty. As a solution for accuracy vs. computational cost dilemma, we introduce a new test-cost-sensitive
method for convolutional neural networks. This method trains a CNN with a set of auxiliary outputs and
expert branches in some middle layers of the network. The expert branches decide to use a shallower part
of the network or going deeper to the end, based on the difficulty of input instance. The expert branches
learn to determine: is the current network prediction is wrong and if the given instance passed to deeper
layers of the network it will generate right output; If not, then the expert branches stop the computation
process. The experimental results on standard dataset CIFAR-10 show that the proposed method can train
models with lower test-cost and competitive accuracy in comparison with basic models.
An overview on application of machine learning techniques in optical networksKhaleda Ali
This document provides an overview of machine learning techniques applied to optical networks. It discusses how optical networks have become more complex with the introduction of technologies like coherent transmission and elastic optical networks. This increased complexity motivates the use of machine learning to analyze network data and make decisions. The document surveys existing work on machine learning applications in optical communications and networking. It aims to introduce researchers to this field and propose new research directions to further the application of machine learning to optical networks.
Noise Tolerant and Faster On Chip Communication Using Binoc ModelIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Network clustering is an important technique used in many large-scale distributed systems. Given good design and implementation, network clustering can significantly enhance the system\'s scalability and efficiency. However, it is very challenging to design a good clustering protocol for networks that scale fast and change continuously. In this paper, we propose a distributed network clustering protocol SDC targeting large-scale decentralized systems. In SDC, clusters are dynamically formed and adjusted based on SCM, a practical clustering accuracy measure. Based on SCM, each node can join or leave a cluster such that the clustering accuracy of the whole network can be improved. A big advantage of SDC is it can recover accurate clusters from node dynamics with very small message overhead. Through extensive simulations, we conclude that SDC is able to discover good quality clusters very efficiently.
In network aggregation techniques for wireless sensor networks - a surveyGungi Achi
This document provides a comprehensive survey of in-network aggregation techniques for wireless sensor networks. It begins by defining in-network aggregation and classifying approaches into those with and without data size reduction. It identifies the key components of in-network aggregation as routing protocols, aggregation functions, and data representation. It reviews theoretical limits of aggregation and discusses open issues. The document aims to provide an updated view of in-network aggregation and motivate future research in this area.
Estimation of Optimized Energy and Latency Constraint for Task Allocation in ...ijcsit
In Network on Chip (NoC) rooted system, energy consumption is affected by task scheduling and allocation
schemes which affect the performance of the system. In this paper we test the pre-existing proposed
algorithms and introduced a new energy skilled algorithm for 3D NoC architecture. An efficient dynamic
and cluster approaches are proposed along with the optimization using bio-inspired algorithm. The
proposed algorithm has been implemented and evaluated on randomly generated benchmark and real life
application such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark
and has been compared with the existing mapping algorithm spiral and crinkle and has shown better
reduction in the communication energy consumption and shows improvement in the performance of the
system. On performing experimental analysis of proposed algorithm results shows that average reduction
in energy consumption is 49%, reduction in communication cost is 48% and average latency is 34%.
Cluster based approach is mapped onto NoC using Dynamic Diagonal Mapping (DDMap), Crinkle and
Spiral algorithms and found DDmap provides improved result. On analysis and comparison of mapping of
cluster using DDmap approach the average energy reduction is 14% and 9% with crinkle and spiral.
This document summarizes research on 3D network-on-chip architectures. It begins by introducing the benefits of 3D integrated circuits for reducing wire lengths and improving performance. It then surveys several existing 3D NoC architectures:
1) Symmetric NoC which treats intra-layer and inter-layer hops identically, incurring high overhead.
2) NoC-Bus Hybrid which uses a bus for single-hop vertical links to reduce hops.
3) Ciliated 3D Mesh which restricts switches to layers and adds cores per switch, lowering bandwidth.
4) True 3D NoC Router which embeds vertical links directly in crossbars for seamless routing.
The
Energy efficiency is one of the most critical issue in design of System on Chip. In Network On
Chip (NoC) based system, energy consumption is influenced dramatically by mapping of
Intellectual Property (IP) which affect the performance of the system. In this paper we test the
antecedently extant proposed algorithms and introduced a new energy proficient algorithm
stand for 3D NoC architecture. In addition a hybrid method has also been implemented using
bioinspired optimization (particle swarm optimization) technique. The proposed algorithm has
been implemented and evaluated on randomly generated benchmark and real life application
such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark
and has been compared with the existing algorithm (spiral and crinkle) and has shown better
reduction in the communication energy consumption and shows improvement in the
performance of the system. Comparing our work with spiral and crinkle, experimental result
shows that the average reduction in communication energy consumption is 19% with spiral and
17% with crinkle mapping algorithms, while reduction in communication cost is 24% and 21%
whereas reduction in latency is of 24% and 22% with spiral and crinkle. Optimizing our work
and the existing methods using bio-inspired technique and having the comparison among them
an average energy reduction is found to be of 18% and 24%.
Applying convolutional neural networks for limited-memory applicationTELKOMNIKA JOURNAL
Currently, convolutional neural networks (CNN) are considered as the most effective tool in image diagnosis and processing techniques. In this paper, we studied and applied the modified SSDLite_MobileNetV2 and proposed a solution to always maintain the boundary of the total memory capacity in the following robust bound and applied on the bridge navigational watch & alarm system (BNWAS). The hardware was designed based on raspberry Pi-3, an embedded single board computer with CPU smartphone level, limited RAM without CUDA GPU. Experimental results showed that the deep learning model on an embedded single board computer brings us high effectiveness in application.
This document discusses analyzing the throughput of IEEE 802.11 DCF in the presence of hidden nodes. It motivates the need to quantify the effect of hidden nodes on wireless network throughput with and without RTS/CTS. The deliverables will be an analytical model extending Bianchi's DCF model to incorporate hidden nodes, analytical throughput results using this model under different traffic loads, simulation results validating the model, and a comparison of the analytical and simulation results.
Technical analysis of content placement algorithms for content delivery netwo...IJECEIAES
Content placement algorithm is an integral part of the cloud-based content de-livery network. They are responsible for selecting a precise content to be re-posited over the surrogate servers distributed over a geographical region. Although various works are being already carried out in this sector, there are loopholes connected to most of the work, which doesn't have much disclosure. It is already known that quality of service, quality of experience, and the cost is always an essential objective targeting to be improved in existing work. Still, there are various other aspects and underlying reasons which are equally important from the design aspect. Therefore, this paper contributes towards reviewing the existing approaches of content placement algorithm over cloud-based content delivery network targeting to explore open-end re-search issues.
Security and imperceptibility improving of image steganography using pixel al...IJECEIAES
Information security is one of the main aspects of processes and methodologies in the technical age of information and communication. The security of information should be a key priority in the secret exchange of information between two parties. In order to ensure the security of information, there are some strategies that are used, and they include steganography and cryptography. An effective digital image-steganographic method based on odd/even pixel allocation and random function to increase the security and imperceptibility has been improved. This lately developed outline has been verified for increasing the security and imperceptibility to determine the existent problems. Huffman coding has been used to modify secret data prior embedding stage; this modified equivalent secret data that prevent the secret data from attackers to increase the secret data capacities. The main objective of our scheme is to boost the peak-signal-to-noise-ratio (PSNR) of the stego cover and stop against any attack. The size of the secret data also increases. The results confirm good PSNR values in addition of these findings confirmed the proposed method eligibility.
IEEE Emerging topic in computing Title and Abstract 2016 tsysglobalsolutions
This document contains 3 summaries of research papers from the IEEE Transactions on Emerging Topics in Computing from May and June 2016.
The first paper proposes a software toolchain that introduces variability awareness from high-level modeling down to runtime management on heterogeneous multicore platforms. It demonstrates the toolchain on 2 platforms.
The second paper proposes a method to jointly tune on-chip lasers and microring resonators in nanophotonic interconnects to improve energy efficiency under thermal variations. It shows up to 53% energy reduction is possible.
The third paper introduces a new multiple-access single-charge associative memory architecture called MASC TCAM that can search contents multiple times with a single precharge, achieving
This document summarizes a study that compares the performance of the MAC layer in flat and hierarchical mobile ad hoc networks (MANETs). The study uses simulation to analyze throughput and packet drops. It finds that throughput is the same for both network structures, but that hierarchical networks have fewer packet drops at the MAC layer. Specifically, packet drops only occurred at 3 nodes in the hierarchical network, whereas 14 nodes experienced drops in the flat network structure. Therefore, the hierarchical approach improves MAC layer performance by reducing packet drops.
IGeekS Technologies is a company located in Bangalore, India. We have being recognized as a quality provider of hardware and software solutions for the student’s in order carry out their academic Projects. We offer academic projects at various academic levels ranging from graduates to masters (Diploma, BCA, BE, M. Tech, MCA, M. Sc (CS/IT)). As a part of the development training, we offer Projects in Embedded Systems & Software to the Engineering College students in all major disciplines.
Abstract: Energy consumption is one of the constraints in Wireless Sensor Networks (WSNs). The routing protocols are the hot areas to address quality-of-service (QoS) related issues viz. Energy consumption, network lifetime, network scalability and packet overhead. In existing system a hybrid optimization based PEGASIS-DSR optimized routing protocol (PDORP) is presented which used cache and directional transmission concept of both proactive and reactive routing protocols. The performance of PDORP has been evaluated and the results indicated that it performs better in most significant parameters. The performance of the existing method is checked when it is evaluated and validated with the nodes which are highly dynamic in nature based on the application requirement. The current system finds the trusted nodes in the case of only static environment. To overcome the issue the proposed system is applied for dynamic WSN’s with the location frequently being changed. The PDORP-LC is applied with local caching (LC) to acquire the location information so that the path learning can be dynamic without depending on the fixed location. The proposed work is performing in dynamic environment with the dynamic derivation of trusted nodes.
Keywords: local caching (LC), Wireless Sensor Networks (WSNs), PEGASIS-DSR optimized routing protocol (PDORP).
Title: Energy Efficient Optimal Paths Using PDORP-LC
Author: ADARSH KUMAR B, BIBIN CHRISTOPHER, ISSAC SAJAN, AJ DEEPA
ISSN 2350-1022
International Journal of Recent Research in Mathematics Computer Science and Information Technology
Paper Publications
This document proposes a new networking paradigm called Knowledge-Defined Networking (KDN) that combines Software-Defined Networking (SDN), Network Analytics, and Machine Learning techniques. The key aspects of KDN are:
1) It uses SDN to provide centralized network control and network analytics to provide a rich view of the network.
2) A Knowledge Plane applies machine learning to the network analytics data to build models of network behavior and make automated decisions.
3) The decisions are expressed through an intent-based language and translated by the SDN controller into specific configuration actions for network devices.
This document provides a detailed proposal for a research project on LANdroids, which are small autonomous robots that could establish and maintain wireless mesh networks to maximize connectivity and network longevity. The proposal outlines four main technical goals: 1) Identifying exploitable features of indoor radio environments through experiments and data collection. 2) Developing self-forming, self-healing network protocols that are energy aware. 3) Learning combined optimization techniques that operate in real and signal space. 4) Understanding the system architecture that maximizes performance at low cost. The proposal describes the benefits of exploiting radio structures to improve connectivity, challenges in modeling indoor radio environments, and approaches involving radio analysis, gradient-based control, feature learning, and system-level
A RAPID DEPLOYMENT BIG DATA COMPUTING PLATFORM FOR CLOUD ROBOTICSIJCNCJournal
The primary contribution of this research is the production of a general cloud robotics architecture that leverages the established and evolving big data technologies. Prior research in this area has not released all details of their deployed architectures, which prevents experimental results from being replicated and verified. By providing a general-purpose architecture, it is hoped that this framework will allow future research to build upon and begin to create a standardised platform, where research can be easily repeated, validated and compared.The secondary contribution is the critical evaluation of the design of cloud robotic architectures. Whilst prior research has demonstrated that cloud-based robotic processing is achievable via big data technologies, such research has not discussed the choice in design. With the ecosystem of big data technologies expanding in recent years, a review of the most relevant technologies for cloud robotics is appropriate to demonstrate and validate the proposed architectural design.
A COMBINATION OF THE INTRUSION DETECTION SYSTEM AND THE OPEN-SOURCE FIREWALL ...IJCNCJournal
There are many security models for computer networks using a combination of Intrusion Detection System and Firewall proposed and deployed in practice. In this paper, we propose and implement a new model of the association between Intrusion Detection System and Firewall operations, which allows Intrusion Detection System to automatically update the firewall filtering rule table whenever it detects a weirdo intrusion. This helps protect the network from attacks from the Internet.
Studies towards heterogeneous Mobile Adhoc Network (MANET) as well as inter-domain routing is still in much infancy stage. After reviewing the existing literaturs, it was found that problems associated with scalability, interoperability, and security is not defined up to the mark as it should be part of pervasive computing in future networks. Moreover, it was found that existing studies do not consider the complexities associated with heterogeneous MANET to a large extent leading to narrowed research scope. Hence, this paper introduces a novel scheme called as Secure, Scalable and Interoperable (SSI )routing, where a joint algorithm is designed, developed, and implemented. The outcome exhibits the correctness of this scheme by simulation assisted by analysis for inter-domain routing.
This document discusses connector models and their accuracy. It begins by describing the evolution of connector models from simple lumped element models to complex multiport microwave models as data rates and simulation capabilities increased. The document then examines extracting connector models from both simulation and measurement, noting sources of variation. Simulation factors like mesh density, material properties, and port setup that impact model accuracy are evaluated. Measurement challenges like fixture removal calibration assumptions and footprint differences that can introduce errors are also discussed. The impacts of real world mechanical variations like insertion depth and solder variations that are often ignored are highlighted. Overall, the document aims to analyze the accuracy of connector models and highlight sources of potential inaccuracies.
Network Function Modeling and Performance EstimationIJECEIAES
This work introduces a methodology for the modelization of network functions focused on the identification of recurring execution patterns as basic building blocks and aimed at providing a platform independent representation. By mapping each modeling building block on specific hardware, the performance of the network function can be estimated in terms of maximum throughput that the network function can achieve on the specific execution platform. The approach is such that once the basic modeling building blocks have been mapped, the estimate can be computed automatically for any modeled network function. Experimental results on several sample network functions show that although our approach cannot be very accurate without taking in consideration traffic characteristics, it is very valuable for those application where even loose estimates are key. One such example is orchestration in network functions virtualization (NFV) platforms, as well as in general virtualization platforms where virtual machine placement is based also on the performance of network services offered to them. Being able to automatically estimate the performance of a virtualized network function (VNF) on different execution hardware, enables optimal placement of VNFs themselves as well as the virtual hosts they serve, while efficiently utilizing available resources.
A Flexible Software/Hardware Adaptive Network for Embedded Distributed Archit...csijjournal
Embedded platforms are projected to integrate hundreds of cores in the near future, and expanding the interconnection network remains a key challenge. We propose SNet, a new Scalable NETwork paradigm that extends the NoCs area to include a software/hardware dynamic routing mechanism. To design routing pathways among communicating processes, it uses a distributed, adaptive, non-supervised routing method based on the ACO algorithm (Ant Colony Optimization). A small footprint hardware unit called DMC speeds up data transfer (Direct Management of Communications). SNet has the benefit of being extremely versatile, allowing for the creation of a broad range of routing topologies to meet the needs of various applications. We provide the DMC module in this work and assess SNet performance by executing a large number of test cases.
An octa core processor with shared memory and message-passingeSAT Journals
Abstract This being the era of fast, high performance computing, there is the need of having efficient optimizations in the processor architecture and at the same time in memory hierarchy too. Each and every day, the advancement of applications in communication and multimedia systems are compelling to increase number of cores in the main processor viz., dual-core, quad-core, octa-core and so on. But, for enhancing the overall performance of multi processor chip, there are stringent requirements to improve inter-core synchronization. Thus, a MPSoC with 8-cores supporting both message-passing and shared-memory inter-core communication mechanisms is implemented on Virtex 5 LX110T FPGA. Each core is based on MIPS III (Microprocessor without interlocked pipelined stages) ISA, handling only integer type instructions and having six-stage pipeline with data hazard detection unit and forwarding logic. The eight processing cores and one central shared memory core are inter connected using 3x3 2-D mesh topology based Network-on-chip (NoC) with virtual channel router. The router is four stage pipelined supporting DOR X-Y routing algorithm and with round robin arbitration technique. For verification and functionality test of above fully synthesized multi core processor, matrix multiplication operation is mapped onto the above said. Partitioning and scheduling of multiple multiplications and addition for each element of resultant matrix has been done accordingly among eight cores to get maximum throughput. All the codes for processor design are written in Verilog HDL. Keywords: MPSoC, message-passing, shared memory, MIPS, ISA, wormhole router, network-on-chip, SIMD, data level parallelism, 2-D Mesh, virtual channel
This document summarizes a research paper that analyzes different network-on-chip (NoC) topologies using computer simulations. The paper compares a standard 2D mesh topology to a proposed new topology in terms of the number of links, number of hops in the longest path, end-to-end delay, and throughput. Simulation results using the ns-2 network simulator show that the proposed topology reduces the number of links by 20% and the longest path by one hop, resulting in lower end-to-end delay and higher throughput compared to the standard 2D mesh topology. The paper concludes that optimizing NoC topology can reduce power consumption while maintaining performance.
The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.
Energy efficiency is one of the most critical issue in design of System on Chip. In Network On
Chip (NoC) based system, energy consumption is influenced dramatically by mapping of
Intellectual Property (IP) which affect the performance of the system. In this paper we test the
antecedently extant proposed algorithms and introduced a new energy proficient algorithm
stand for 3D NoC architecture. In addition a hybrid method has also been implemented using
bioinspired optimization (particle swarm optimization) technique. The proposed algorithm has
been implemented and evaluated on randomly generated benchmark and real life application
such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark
and has been compared with the existing algorithm (spiral and crinkle) and has shown better
reduction in the communication energy consumption and shows improvement in the
performance of the system. Comparing our work with spiral and crinkle, experimental result
shows that the average reduction in communication energy consumption is 19% with spiral and
17% with crinkle mapping algorithms, while reduction in communication cost is 24% and 21%
whereas reduction in latency is of 24% and 22% with spiral and crinkle. Optimizing our work
and the existing methods using bio-inspired technique and having the comparison among them
an average energy reduction is found to be of 18% and 24%.
Applying convolutional neural networks for limited-memory applicationTELKOMNIKA JOURNAL
Currently, convolutional neural networks (CNN) are considered as the most effective tool in image diagnosis and processing techniques. In this paper, we studied and applied the modified SSDLite_MobileNetV2 and proposed a solution to always maintain the boundary of the total memory capacity in the following robust bound and applied on the bridge navigational watch & alarm system (BNWAS). The hardware was designed based on raspberry Pi-3, an embedded single board computer with CPU smartphone level, limited RAM without CUDA GPU. Experimental results showed that the deep learning model on an embedded single board computer brings us high effectiveness in application.
This document discusses analyzing the throughput of IEEE 802.11 DCF in the presence of hidden nodes. It motivates the need to quantify the effect of hidden nodes on wireless network throughput with and without RTS/CTS. The deliverables will be an analytical model extending Bianchi's DCF model to incorporate hidden nodes, analytical throughput results using this model under different traffic loads, simulation results validating the model, and a comparison of the analytical and simulation results.
Technical analysis of content placement algorithms for content delivery netwo...IJECEIAES
Content placement algorithm is an integral part of the cloud-based content de-livery network. They are responsible for selecting a precise content to be re-posited over the surrogate servers distributed over a geographical region. Although various works are being already carried out in this sector, there are loopholes connected to most of the work, which doesn't have much disclosure. It is already known that quality of service, quality of experience, and the cost is always an essential objective targeting to be improved in existing work. Still, there are various other aspects and underlying reasons which are equally important from the design aspect. Therefore, this paper contributes towards reviewing the existing approaches of content placement algorithm over cloud-based content delivery network targeting to explore open-end re-search issues.
Security and imperceptibility improving of image steganography using pixel al...IJECEIAES
Information security is one of the main aspects of processes and methodologies in the technical age of information and communication. The security of information should be a key priority in the secret exchange of information between two parties. In order to ensure the security of information, there are some strategies that are used, and they include steganography and cryptography. An effective digital image-steganographic method based on odd/even pixel allocation and random function to increase the security and imperceptibility has been improved. This lately developed outline has been verified for increasing the security and imperceptibility to determine the existent problems. Huffman coding has been used to modify secret data prior embedding stage; this modified equivalent secret data that prevent the secret data from attackers to increase the secret data capacities. The main objective of our scheme is to boost the peak-signal-to-noise-ratio (PSNR) of the stego cover and stop against any attack. The size of the secret data also increases. The results confirm good PSNR values in addition of these findings confirmed the proposed method eligibility.
IEEE Emerging topic in computing Title and Abstract 2016 tsysglobalsolutions
This document contains 3 summaries of research papers from the IEEE Transactions on Emerging Topics in Computing from May and June 2016.
The first paper proposes a software toolchain that introduces variability awareness from high-level modeling down to runtime management on heterogeneous multicore platforms. It demonstrates the toolchain on 2 platforms.
The second paper proposes a method to jointly tune on-chip lasers and microring resonators in nanophotonic interconnects to improve energy efficiency under thermal variations. It shows up to 53% energy reduction is possible.
The third paper introduces a new multiple-access single-charge associative memory architecture called MASC TCAM that can search contents multiple times with a single precharge, achieving
This document summarizes a study that compares the performance of the MAC layer in flat and hierarchical mobile ad hoc networks (MANETs). The study uses simulation to analyze throughput and packet drops. It finds that throughput is the same for both network structures, but that hierarchical networks have fewer packet drops at the MAC layer. Specifically, packet drops only occurred at 3 nodes in the hierarchical network, whereas 14 nodes experienced drops in the flat network structure. Therefore, the hierarchical approach improves MAC layer performance by reducing packet drops.
IGeekS Technologies is a company located in Bangalore, India. We have being recognized as a quality provider of hardware and software solutions for the student’s in order carry out their academic Projects. We offer academic projects at various academic levels ranging from graduates to masters (Diploma, BCA, BE, M. Tech, MCA, M. Sc (CS/IT)). As a part of the development training, we offer Projects in Embedded Systems & Software to the Engineering College students in all major disciplines.
Abstract: Energy consumption is one of the constraints in Wireless Sensor Networks (WSNs). The routing protocols are the hot areas to address quality-of-service (QoS) related issues viz. Energy consumption, network lifetime, network scalability and packet overhead. In existing system a hybrid optimization based PEGASIS-DSR optimized routing protocol (PDORP) is presented which used cache and directional transmission concept of both proactive and reactive routing protocols. The performance of PDORP has been evaluated and the results indicated that it performs better in most significant parameters. The performance of the existing method is checked when it is evaluated and validated with the nodes which are highly dynamic in nature based on the application requirement. The current system finds the trusted nodes in the case of only static environment. To overcome the issue the proposed system is applied for dynamic WSN’s with the location frequently being changed. The PDORP-LC is applied with local caching (LC) to acquire the location information so that the path learning can be dynamic without depending on the fixed location. The proposed work is performing in dynamic environment with the dynamic derivation of trusted nodes.
Keywords: local caching (LC), Wireless Sensor Networks (WSNs), PEGASIS-DSR optimized routing protocol (PDORP).
Title: Energy Efficient Optimal Paths Using PDORP-LC
Author: ADARSH KUMAR B, BIBIN CHRISTOPHER, ISSAC SAJAN, AJ DEEPA
ISSN 2350-1022
International Journal of Recent Research in Mathematics Computer Science and Information Technology
Paper Publications
This document proposes a new networking paradigm called Knowledge-Defined Networking (KDN) that combines Software-Defined Networking (SDN), Network Analytics, and Machine Learning techniques. The key aspects of KDN are:
1) It uses SDN to provide centralized network control and network analytics to provide a rich view of the network.
2) A Knowledge Plane applies machine learning to the network analytics data to build models of network behavior and make automated decisions.
3) The decisions are expressed through an intent-based language and translated by the SDN controller into specific configuration actions for network devices.
This document provides a detailed proposal for a research project on LANdroids, which are small autonomous robots that could establish and maintain wireless mesh networks to maximize connectivity and network longevity. The proposal outlines four main technical goals: 1) Identifying exploitable features of indoor radio environments through experiments and data collection. 2) Developing self-forming, self-healing network protocols that are energy aware. 3) Learning combined optimization techniques that operate in real and signal space. 4) Understanding the system architecture that maximizes performance at low cost. The proposal describes the benefits of exploiting radio structures to improve connectivity, challenges in modeling indoor radio environments, and approaches involving radio analysis, gradient-based control, feature learning, and system-level
A RAPID DEPLOYMENT BIG DATA COMPUTING PLATFORM FOR CLOUD ROBOTICSIJCNCJournal
The primary contribution of this research is the production of a general cloud robotics architecture that leverages the established and evolving big data technologies. Prior research in this area has not released all details of their deployed architectures, which prevents experimental results from being replicated and verified. By providing a general-purpose architecture, it is hoped that this framework will allow future research to build upon and begin to create a standardised platform, where research can be easily repeated, validated and compared.The secondary contribution is the critical evaluation of the design of cloud robotic architectures. Whilst prior research has demonstrated that cloud-based robotic processing is achievable via big data technologies, such research has not discussed the choice in design. With the ecosystem of big data technologies expanding in recent years, a review of the most relevant technologies for cloud robotics is appropriate to demonstrate and validate the proposed architectural design.
A COMBINATION OF THE INTRUSION DETECTION SYSTEM AND THE OPEN-SOURCE FIREWALL ...IJCNCJournal
There are many security models for computer networks using a combination of Intrusion Detection System and Firewall proposed and deployed in practice. In this paper, we propose and implement a new model of the association between Intrusion Detection System and Firewall operations, which allows Intrusion Detection System to automatically update the firewall filtering rule table whenever it detects a weirdo intrusion. This helps protect the network from attacks from the Internet.
Studies towards heterogeneous Mobile Adhoc Network (MANET) as well as inter-domain routing is still in much infancy stage. After reviewing the existing literaturs, it was found that problems associated with scalability, interoperability, and security is not defined up to the mark as it should be part of pervasive computing in future networks. Moreover, it was found that existing studies do not consider the complexities associated with heterogeneous MANET to a large extent leading to narrowed research scope. Hence, this paper introduces a novel scheme called as Secure, Scalable and Interoperable (SSI )routing, where a joint algorithm is designed, developed, and implemented. The outcome exhibits the correctness of this scheme by simulation assisted by analysis for inter-domain routing.
This document discusses connector models and their accuracy. It begins by describing the evolution of connector models from simple lumped element models to complex multiport microwave models as data rates and simulation capabilities increased. The document then examines extracting connector models from both simulation and measurement, noting sources of variation. Simulation factors like mesh density, material properties, and port setup that impact model accuracy are evaluated. Measurement challenges like fixture removal calibration assumptions and footprint differences that can introduce errors are also discussed. The impacts of real world mechanical variations like insertion depth and solder variations that are often ignored are highlighted. Overall, the document aims to analyze the accuracy of connector models and highlight sources of potential inaccuracies.
Network Function Modeling and Performance EstimationIJECEIAES
This work introduces a methodology for the modelization of network functions focused on the identification of recurring execution patterns as basic building blocks and aimed at providing a platform independent representation. By mapping each modeling building block on specific hardware, the performance of the network function can be estimated in terms of maximum throughput that the network function can achieve on the specific execution platform. The approach is such that once the basic modeling building blocks have been mapped, the estimate can be computed automatically for any modeled network function. Experimental results on several sample network functions show that although our approach cannot be very accurate without taking in consideration traffic characteristics, it is very valuable for those application where even loose estimates are key. One such example is orchestration in network functions virtualization (NFV) platforms, as well as in general virtualization platforms where virtual machine placement is based also on the performance of network services offered to them. Being able to automatically estimate the performance of a virtualized network function (VNF) on different execution hardware, enables optimal placement of VNFs themselves as well as the virtual hosts they serve, while efficiently utilizing available resources.
A Flexible Software/Hardware Adaptive Network for Embedded Distributed Archit...csijjournal
Embedded platforms are projected to integrate hundreds of cores in the near future, and expanding the interconnection network remains a key challenge. We propose SNet, a new Scalable NETwork paradigm that extends the NoCs area to include a software/hardware dynamic routing mechanism. To design routing pathways among communicating processes, it uses a distributed, adaptive, non-supervised routing method based on the ACO algorithm (Ant Colony Optimization). A small footprint hardware unit called DMC speeds up data transfer (Direct Management of Communications). SNet has the benefit of being extremely versatile, allowing for the creation of a broad range of routing topologies to meet the needs of various applications. We provide the DMC module in this work and assess SNet performance by executing a large number of test cases.
An octa core processor with shared memory and message-passingeSAT Journals
Abstract This being the era of fast, high performance computing, there is the need of having efficient optimizations in the processor architecture and at the same time in memory hierarchy too. Each and every day, the advancement of applications in communication and multimedia systems are compelling to increase number of cores in the main processor viz., dual-core, quad-core, octa-core and so on. But, for enhancing the overall performance of multi processor chip, there are stringent requirements to improve inter-core synchronization. Thus, a MPSoC with 8-cores supporting both message-passing and shared-memory inter-core communication mechanisms is implemented on Virtex 5 LX110T FPGA. Each core is based on MIPS III (Microprocessor without interlocked pipelined stages) ISA, handling only integer type instructions and having six-stage pipeline with data hazard detection unit and forwarding logic. The eight processing cores and one central shared memory core are inter connected using 3x3 2-D mesh topology based Network-on-chip (NoC) with virtual channel router. The router is four stage pipelined supporting DOR X-Y routing algorithm and with round robin arbitration technique. For verification and functionality test of above fully synthesized multi core processor, matrix multiplication operation is mapped onto the above said. Partitioning and scheduling of multiple multiplications and addition for each element of resultant matrix has been done accordingly among eight cores to get maximum throughput. All the codes for processor design are written in Verilog HDL. Keywords: MPSoC, message-passing, shared memory, MIPS, ISA, wormhole router, network-on-chip, SIMD, data level parallelism, 2-D Mesh, virtual channel
This document summarizes a research paper that analyzes different network-on-chip (NoC) topologies using computer simulations. The paper compares a standard 2D mesh topology to a proposed new topology in terms of the number of links, number of hops in the longest path, end-to-end delay, and throughput. Simulation results using the ns-2 network simulator show that the proposed topology reduces the number of links by 20% and the longest path by one hop, resulting in lower end-to-end delay and higher throughput compared to the standard 2D mesh topology. The paper concludes that optimizing NoC topology can reduce power consumption while maintaining performance.
The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.
Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on field programmable gate array (FPGA).
Low power network on chip architectures: A surveyCSITiaesprime
Mostly communication now days is done through system on chip (SoC) models so, network on chip (NoC) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.
Design of Tele command SOC-IP by AES Cryptographic Method Using VHDLdbpublications
The goal of this project is to implement the (AES) encryption system using Verilog. To do this, several separate sections of the algorithm will be coded to work together towards the end goal of performing the correct encryption routines. A telecommand is a command sent to control a remote system or systems i.e not directly connected (e.g. via wires) to the place from which the telecommand is sent. The telecommand word is derived from tele = remote (Greek), and command = to entrust/order (Latin). Systems that need remote measurement and reporting of information of interest to the system designer or operator, require the counterpart of telecommand, telemetry. For a telecommand (TC) to be effective, it must be compiled into a pre-arranged format (which may follow a standard structure), modulated onto a carrier wave which is then transmitted with adequate power to the remote system. The remote system will then demodulates the digital signal from the carrier, decode the telecommand, and execute it.
HOMOGENEOUS MULTISTAGE ARCHITECTURE FOR REAL-TIME IMAGE PROCESSINGcscpconf
The document describes a homogeneous multistage architecture for real-time image processing. It proposes a parallel architecture using multiple identical processing elements connected by different communication links. As an example application, it discusses a multi-hypothesis approach for road recognition, which uses multiple hypotheses to detect and track road edges in video in real-time. Experimental results using a FPGA demonstrate the architecture can detect roadsides in images within 60 milliseconds.
A Review - Synchronization Approaches to Digital systemsIJERA Editor
Synchronization is a prime requirement in the process of Digital systems. Wherein new devices are upcoming
towards providing higher service level, advanced distributed systems are been integrated onto a single platform
for higher service provision. However with the integration of large processing units, the distributed processing
needs a high level synchronization with minimum processing overhead. The issue of synchronization was
processed by various approaches. This paper outlines a brief review on the developments made in the field of
synchronization approach to digital system, under distributed mode operation.
Design of an Efficient Communication Protocol for 3d Interconnection NetworkIJMTST Journal
Three-dimensional integrated circuits (3D ICs) provide better device integration, reduced signal delay and reduced interconnect power. They additionally give better layout flexibility by permitting heterogeneous integration, by taking the advantage of intrinsic capability of reducing the wire length in 3D ICs, 3D NOC Bus Hybrid mesh layout was suggested. This layout provides an apparently significant stage to implement economical multicast routings for 3D networks-on-chip. A unique multicast partitioning and routing strategy for the 3D NOC-Bus Hybrid mesh architectures to improve the system performance and to decrease the power consumption is being proposed. The planned design exploits the useful attribute of a single-hop (bus-based) interlayer communication of the 3D stacked mesh design to supply superior hardware multicast support. Finally customized partitioning approach and an effective routing method is given to decrease the average hop count and network latency. Compared to the recently designed 3D NOC architectures being capable of supporting hardware multicasting, huge simulations with traffic profiles reveals design exploitation, which is the planned multicast routing strategy will facilitate significant performance enhancements.
Network on Chip Architecture and Routing Techniques: A surveyIJRES Journal
This document summarizes research on Network on Chip (NOC) architecture and routing techniques. It discusses NOC topology options including mesh, torus, ring and irregular networks. It also reviews router architecture, switching techniques, virtual channels, buffering, error correction, quality of service implementations, and routing algorithms. Specific NOC implementations discussed include QNOC, Ethereal NOC, and SPIN NOC. The document provides an overview of research on improving performance and efficiency in NOC design.
Area-Efficient Design of Scheduler for Routing Node of Network-On-ChipVLSICS Design
This document describes an area-efficient design for a scheduler used in routing nodes of a Network-on-Chip (NoC). The scheduler arbitrates between requests from input ports to access the switching fabric. The original scheduler design uses round-robin arbitration and has separate grant and accept arbiters. The proposed design folds the scheduler onto itself, reducing its area by 50% while maintaining the same scheduling functionality. Synthesis results show the modified scheduler has a 30% smaller area but requires two extra clock cycles per scheduling decision compared to the original design.
AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIPVLSICS Design
Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbased architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.
Design and Implementation of JPEG CODEC using NoCIRJET Journal
This document describes the design and implementation of a JPEG codec using a Network-on-Chip (NoC) structure. It aims to speed up the image transfer process and provide shorter processing times. The key steps are:
1. The JPEG encoding process includes color space conversion, downsampling, block division, discrete cosine transform, quantization, and entropy coding to compress the image.
2. A NoC is used to transmit the compressed image data packets across the chip to reduce latency during transfer.
3. The JPEG decoding process reverses the encoding steps through entropy decoding, dequantization, inverse discrete cosine transform, and image reconstruction to decompress the image for viewing.
Analysis and assessment software for multi-user collaborative cognitive radi...IJECEIAES
Computer simulations are without a doubt a useful methodology that allows to explore research queries and develop prototypes at lower costs and timeframes than those required in hardware processes. The simulation tools used in cognitive radio networks (CRN) are undergoing an active process. Currently, there is no stable simulator that enables to characterize every element of the cognitive cycle and the available tools are a framework for discrete-event software. This work presents the spectral mobility simulator in CRN called “App MultiColl-DCRN”, developed with MATLAB’s app designer. In contrast with other frameworks, the simulator uses real spectral occupancy data and simultaneously analyzes features regarding spectral mobility, decision-making, multi-user access, collaborative scenarios and decentralized architectures. Performance metrics include bandwidth, throughput level, number of failed handoffs, number of total handoffs, number of handoffs with interference, number of anticipated handoffs and number of perfect handoffs. The assessment of the simulator involves three scenarios: the first and second scenarios present a collaborative structure using the multi-criteria optimization and compromise solution (VIKOR) decision-making model and the naïve Bayes prediction technique respectively. The third scenario presents a multi-user structure and uses simple additive weighting (SAW) as a decision-making technique. The present development represents a contribution in the cognitive radio network field since there is currently no software with the same features.
ENERGY AND LATENCY AWARE APPLICATION MAPPING ALGORITHM & OPTIMIZATION FOR HOM...cscpconf
Energy efficiency is one of the most critical issue in design of System on Chip. In Network On
Chip (NoC) based system, energy consumption is influenced dramatically by mapping of
Intellectual Property (IP) which affect the performance of the system. In this paper we test the
antecedently extant proposed algorithms and introduced a new energy proficient algorithm
stand for 3D NoC architecture. In addition a hybrid method has also been implemented using
bioinspired optimization (particle swarm optimization) technique. The proposed algorithm has
been implemented and evaluated on randomly generated benchmark and real life application
such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark
and has been compared with the existing algorithm (spiral and crinkle) and has shown better
reduction in the communication energy consumption and shows improvement in the
performance of the system. Comparing our work with spiral and crinkle, experimental result
shows that the average reduction in communication energy consumption is 19% with spiral and
17% with crinkle mapping algorithms, while reduction in communication cost is 24% and 21%
whereas reduction in latency is of 24% and 22% with spiral and crinkle. Optimizing our work
and the existing methods using bio-inspired technique and having the comparison among them
an average energy reduction is found to be of 18% and 24%.
1) The planning of Physical Cell Identities (PCI) has a strong impact on the performance of LTE networks. PCI planning determines the frequency locations of cell-specific reference signals, which can collide between neighboring cells and degrade signal quality estimates.
2) Most research on PCI planning has focused on avoiding collisions and confusion between PCI assignments. However, no study has quantified the impact of PCI planning on downlink throughput performance.
3) This paper develops an analytical model to quantify the influence of PCI planning on reference signal collisions. It then uses a system-level simulator to test different PCI planning schemes and analyze their impact on call blocking, dropping, and user throughput under various traffic conditions.
This document outlines a research proposal on developing a congestion-aware adaptive routing protocol for an on-chip network. The objectives are to minimize congestion and enhance network performance by dynamically adjusting routing paths based on real-time network conditions. The proposal will involve implementing a congestion-aware adaptive routing algorithm using Verilog, gathering performance data from conventional and proposed algorithms, and analyzing results to optimize the routing protocol and network structure. The desired outcome is to improve latency and throughput in the on-chip network at low cost by exploiting adaptive routing.
Automatic Layer-Based Generation Of System-On-Chip Bus Communication ModelsKaren Gomez
This document summarizes an approach for automatically generating system-on-chip (SoC) bus communication models through layered refinement from an abstract specification. It presents a two-stage design flow for communication synthesis: 1) network design to generate a customized heterogeneous bus network model, and 2) link design to refine the network model into a linked implementation. The approach targets architectures consisting of processing elements connected by a network of shared buses, with buses connected by communication elements. It generates models at different abstraction levels to enable early design space exploration while balancing simulation speed and accuracy.
SENSOR SIGNAL PROCESSING USING HIGH-LEVEL SYNTHESIS AND INTERNET OF THINGS WI...pijans
Sensor routers play a crucial role in the sector of Internet of Things applications, in which the capacity for transmission of the network signal is limited from cloud systems to sensors and its reversal process. It describes a robust recognized framework with various architected layers to process data at high level synthesis. It is designed to sense the nodes instinctually with the help of Internet of Things where the applications arise in cloud systems. In this paper embedded PEs with four layer new design framework architecture is proposed to sense the devises of IOT applications with the support of high-level synthesis DBMF (database management function) tool.
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#Abstract:
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#Prerequisites:
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APPLYING GENETIC ALGORITHM TO SOLVE PARTITIONING AND MAPPING PROBLEM FOR MESH NETWORK-ON-CHIP SYSTEMS
1. International Journal of Computer Science & Information Technology (IJCSIT) Vol 13, No 1, February 2021
10.5121/ijcsit.2021.13103 33
APPLYING GENETIC ALGORITHM TO SOLVE
PARTITIONING AND MAPPING PROBLEM FOR
MESH NETWORK-ON-CHIP SYSTEMS
WalidMoktharSalh1
and Azeddien M. Sllame2
1
Faculty of Science University of Tripoli Tripoli, Libya
2
Faculty of Information Technology University of Tripoli Tripoli, Libya
ABSTRACT
This paper presents a genetic based approach to the partitioning and mapping of multicore SoC cores over
a NoC system that uses mesh topology. The proposed algorithm performs the partitioning and mapping by
reducing communication cost and minimizing power consumption by placing those intercommunicated
cores as close as possible together. A program developed in C++ in which the provided specification of
the multicore MPSoC system captures all data dependencies before any start of the design process.
Experimental results of several multimedia benchmarks demonstrates that the genetic-based approach able
to find different satisfied implementations to the problem of partitioning and mapping of MPSoC cores
over mesh-based NoC system that satisfies design goals.
KEYWORDS
Network-on-Chip, Multicore, Partitioning, Mesh topology, Genetic algorithm
1. INTRODUCTION
System-on-Chip (SoC) is an electronic circuit which usually realizes the maximum tasks needed
practically to perform an intended system’s behavior. Current state-of-the-art SoCs contain
memory modules/banks, instruction-set processors (central processing units, CPUs), (Intellectual
Property) IP processing cores, specialized logic, busses and interconnection networks,
multimedia cores, digital signal processing (DSP) units, and wireless transmitters/receivers. In
addition, current SoC implementations may include also micro-electric-mechanical systems
(MEMS) and microsystems cores including a set of hierarchical cores [1] [2]. The most essential
issue with current SoC systems is the communication subsystem. However, current practices are
using scalable interconnection networks as an alternative to old design style which uses different
buses or wires along the chip to interconnect the cores of SoC system. Thus, as a result with
technology advances, the SoC design approach is moved to multiprocessing system-on-chip
(MPSoC) systems which may contain multi-thousands cores with hierarchical cores memories,
sending and receiving devices and microsystems; which is now named as “Network-On-Chip”
(NoC) design paradigm [2] [3] [4].However, Figure (1) illustrates the big picture of NoC system
design with different interconnection networks which currently used in developing efficient
MPSoC designs that are very useful and efficiently working with intensive multiprocessing
applications.
2. International Journal of Computer Science & Information Technology (IJCSIT) Vol 13, No 1, February 2021
34
Figure (1): SoC generic architecture with different NoC interconnection topologies
NoC is anon-chip communication subsystem built to facilitate communication between cores
composing of SoC systems. NoC design approach applies diverse networking algorithms,
processes, theories, and methods to on-chip communications which bringsoutstanding
improvements over typical bus or hierarchical buses and point-to-point links. NoC uses packet
switching technique as found in TCP/IP networking model; instead of old fashioned bus
techniques that communicate by wires routed around the chip [5]. More precisely, in NoC model,
when one IP processing core is idle, other IP blocks (cores, components) continue to make use of
the network resources. Consequently, NoC design approach has the benefits of being modular,
scalable, well-structured, power efficient, employ reusable switches (routers), and flexible with
higher bandwidth usability. However, Butterfly fat tree (BFT) and mesh topologies are
considered essential representative prototypes of standard interconnection networks [1] [5], see
Figure (1). However, the use of interconnection networks as a means of on-chip communication
leads to use the principle of separation between computation and communication that has been
used in supercomputing in the past.
This paper aims to implement a genetic algorithm which systematically changing its internal
mechanisms to find a solution to the partitioning and mapping problem in NoC designs after
reading the specification and use Hamilton distance to map the intercommunicated processing
cores as near as feasible to reduce routing and power consumption overhead.
The paper is organized as follows: the Section 2 report the related work, Section 3 summarizes
outlines multiprocessing SoC with core-based design approach. Section 4 explains the properties
of mesh topology, while Section 5 describes the proposed design methodology with the genetic
algorithm’s structure. Finally results are reported in Section 6.
2. RELATED WORK
There are many research explorations about NoC design and multicore mapping techniques with
diverse approaches carried out in a lot of universities and research centers internationally. The
following are representative set from that research.
Lei and Kumar in [6] described a genetic algorithm optimization technique to map different
applications into a NoC system based on 2D mesh structure, which represented in graph
representation. The applied genetic algorithm maps cores onto graph vertices with the aim
3. International Journal of Computer Science & Information Technology (IJCSIT) Vol 13, No 1, February 2021
35
of reducing time consumed by application execution with efficient a delay model
developed for NoC communication over mesh topology.
Teich et al in [7] presented a technique that concentrates on the partitioning of system level
specification using evolutionary algorithms. The methodology explores the effect of the
partitioning process with different design implementations only at the system level.
Following this, scheduling of each specification partition is made by a list-based scheduler.
Henkel et al in [8] presented a high-level assessment methodology to discover the design
space with respect to different design constraints in order to guide HW/SW partitioning at
system level. The methodology considers only high-level decisions and does not consider
any implementation details of the HW.
Amit Kumar et al. in [9] outlined a state-of-the-art comprehensive analysis review and
cataloguing of mapping techniques which focused on evolving developments for multicore
design systems. An evaluation study is delivered comparing the analyzed techniques
according to target optimization objectives.
G. Ascia et al. in [10] addressed the problem of topological mapping of IP cores on the tiles
of a mesh-based NoC architecture. The target was to get a mapping which enhances the
design performance while reducing the consumed power over a mesh topology.
Glenn Leary et al. in [11] described automation design tool for NoC designs based on
genetic algorithm. The designed tool provides also applies communication synthesis
method over interconnection networks.
The work in this paper is different than the one mentioned above works in such a way that; the
system specification is read by the algorithm to determine the data dependencies among the
statements and define their execution order.
After that, the core methods of the proposed genetic algorithm are systematically evaluated,
modified and biased in the direction of gaining their power of finding proficient solution to the
partitioning and allocation problem in NoC designs by reducing the communication between
associated SoC cores by placing them as close as possible in order to minimize power
consumption of the designed system.
3. MULTIPROCESSING SYSTEM-ON-CHIP
SoC systems are supported by a wide variety collection of microprocessors, processor
architectures, IP cores, CPUs, application specific integrated circuits (ASIC), application specific
instruction set processor (ASIP), digital signal processing cores (DSP), etc. At present, more than
a hundred different microprocessors are available from more than 40 semiconductor vendors.
SoC systems have been migrated into MPSoC design paradigm due to two reasons; first one is
the introduction of interconnection networks as an on-chip communication means; the second one
is the latest developments and advancements in deep submicron technologies which allowed
producing billions of transistors into a single chip. Thus, allowed implementing multiple-
instruction multiple-data streams (MIMD) processing systems into a single chip. On another
hand, SoC designs have maturated to apply reusability by employing the cores-based design
approach which facilitated designing powerful SoC systems with hundreds of heterogeneous
cores that need to communicate efficiently into a single chip. However, core-based approach
enabled designers to concentrate on single core/hierarchical or microsystem designs which lead
to produce reusable, tested, well-documented cores with proper interfacing. Consequently, this
made making NoC possible which resulted into realizing power efficient, modular, flexible, and
scalable MPSoC systems for current intensive multiprocessing devices which overcomes the
design problems encountered with SoC traditional design techniques such as: variety of dedicated
4. International Journal of Computer Science & Information Technology (IJCSIT) Vol 13, No 1, February 2021
36
interfaces, design and verification complexity, unpredictable performance, and many
underutilized wires while using buses and wires inside the chip [1] [4] [5].
However the heterogeneity on core types leads to the following characteristics in MPSoC:
a) MPSoC system with heterogeneous cores is modeled and described by interconnected
executable processes which can be implemented as hardware, software, and
communication components (routers and switches) that are employed to facilitate
communication between system cores and external environment.
b) Heterogeneous MPSoC architecture encourages the separation between computation and
communication.
c) The MPSoC heterogeneous architecture provides highly concurrent computation and
flexible programmability.
d) The heterogeneous MPSoC are composed of different kinds of PEs which need different
interfacing unis.
e) Homogeneous MPSoC are made of the same type of element which is instantiated several
times.
f) Heterogeneous MPSoCs can include similar cores, hierarchal cores and divergent cores
analog and digital which allows MPSoCs architecture to include large number of
processing elements integrated into a single chip.
g) Next generation of heterogeneous MPSoC will be designed from few heterogeneous
subsystems (hierarchy feature of multicore design methods), where each subsystem
includes a massive number of identical processors (cores) to run a specific SW, or HW
task.
4. MESH INTERCONNECTION TOPOLOGYAS AN ON-CHIP COMMUNICATION
SYSTEM
With NoC implementation an aggregate bandwidth grows while the BW of the bus is shared and
the speed goes down as the cores added to the bus implementation. In addition, NoC system
designs are based on the interconnection networks which exhibit pipelining concurrency in their
design as they have been developed to work with parallel computing and supercomputers. Bus
implementations did not have any concurrency, whereas pipelining is difficult to implement with
buses. Furthermore, the NoC designs demonstrate the separation of abstraction layers as well as
separation of computation and communications which enhances the scalability issue of the NoC
systems, in contrary bus designs suffer from such separation feature. However, unlike NoC
designs, the bus designs are fairly simple to build with low cost, while NoC designs need new
design techniques and methodologies, such as network interfacing and buffering and router
(switch) designs. However, 2D mesh is a popular interconnection structure is currently the
preferred choice for large-scale MPSoC implementations. With mesh structure, the links is only
interconnecting directly neighboring nodes which highlights a regular layout of the mesh
topology as a key advantage over other networking structures such as fat trees. On another hand,
the key disadvantage of the mesh structure is the large number of hops (routers) traversed through
the topology to reach their final destination. However, each router imposes a minimum latency
and it is thus; a potential point of contention. A large number of hops have a direct impact on the
energy consumed in interconnecting the communication path for buffering, transmission, and
flow control. As a result, mesh topology will have performance degradation on performance, and
scalability problems as the size of the mesh interconnection matrix grows quickly by increasing
the number of nodes [12] [13] [14] [15].
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4.1. Mesh Structure Concepts
The 1-D meshes are organized from linear array of processing cores, while the most practical
mesh’s topologies are, of type, 2D, and 3D meshes. In a mesh topology structure, the nodes are
organized in am dimensional lattice of width w, producing a result of wm nodes; commonly m=1
(linear array) or m=2 (2D array). Therefore, the communications in mesh topology are allowed
only between neighboring processing nodes. All interior nodes are connected to 2m other nodes
and all the communication links are short and balanced. However, in 2D mesh architecture the
routers or switches are found in each intersection between columns and rows; where switches
(routers) are low radix with up to C+4 input and output ports. Consequently, this considered as a
disadvantage because a large number of hops is needed for the packets to reach their final
destination, which is considered a proportional to “N”; for N routers. For the routing purposes
with mesh designs, the well-known XY routing is considered which uses a typical minimal turn
deterministic algorithm. The XY routing algorithm decides the routing path to all current packets
in every routing step, by firstly routing packets in X (horizontal direction) to the desired column,
then finally performing the routing in Y (vertical direction) to reach the targeted destination.
However, XY routing is performing efficiently on mesh topology and routers’ addresses are their
XY-coordinates, as seen in Figure (2) [14] [15].
.
Figure (2): Routing inside mesh networks
4.2. Features of the Mesh Topology [12] [13] [14] [15] [16]:
• Topology: Mesh network has a fixed regular topology and belongs to direct type
interconnection networks, in which switches with point-to-point interconnections are set up
between the network nodes to establish the mesh structure. Though, as the dimension of
mesh increases the number of switches (routers) increases, which increases the cost
overheads, such as in the 2D mesh topology there are as many switches as processing
cores. Mesh networks commonly use the same design for the switches included in the
topology, each of them has connections between four neighboring cores. Yet, because of
the structure regularity; the mesh topology has the feature of straightforward distance
calculation between the sending and receiving nodes by summing up the offsets along
mesh topology dimensions.
• Network traffic balance: In mesh interconnection networks deterministic routing in 2D
mesh has in-order packet transfer which produces simple designs and efficiently working
under uniform traffic only.
• Deadlock, livelock, starvation: Mesh uses XY deterministic routing that is thought-out as
deadlock and livelock free.
• Routing: Mesh uses XY deterministic routing; in which all packets take the same path
between any source-destination pairs. Hence, it is typically selects the shortest path
associated with in-order flow control. In addition, the traffic with the traditional XY
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38
routing; does not spread regularly over the entire network because the algorithm causes the
biggest load flows in the middle of the network. In addition, under non congestion state, the
mesh network which applies deterministic routing can achieve reasonable reliability with
low latency overhead.
• Fault tolerance: as a result of its static interconnections among nodes which look as a
matrix structure, the mesh topology possesses low fault tolerance characteristics.
• Congestion control: Since, mesh network has fixed regular structure so it is impossible for
it to respond dynamically to network congestion. That will affect the efficiency and
network’s throughput negatively.
• Latency and throughput: In mesh networks, as the size of the network increases the
latency and throughput will increase.
• Network utilization: XY deterministic routing in mesh networks causes the network
resources to be underutilized. However, XY deterministic routing has a tendency to transfer
packets in the direction of the mesh center which increase the network contention because
the early network capacity saturation. Consequently, the performance will be reduced. On
another hand, XY routing works well with uniform distributed traffic.
• Scalability: With scalability the performance increases with the addition of new processing
cores consistently, which lead to more utilization of the network’ bandwidth (BW).
However, the BW in mesh networks is not scalable where it is static by the number of
employed cores.
• Energy dissipation: The energy dissipation increases linearly as the number of channels
increase in the operational switches in the mesh network.
Physical realization: The main practical feature of the mesh network is its simple mapping into
the physical space of the chip using uniform short wiring between processing cores. However,
more simplicity is expected as the size of the mesh found to be similar to the packaging
technology’s dimensions.
5. THE PROPOSED DESIGN METHODOLOGY
Current state-of-the-art research in MPSoC design domain is concentrating on defining specific
features of infrastructure such as partitioning the MPSoC system specification amongst its
available components (cores) and scheduling their execution in the selected components,
selecting the suitable on-chip communication network subsystems, and defining interfacing. In
this paper we will consider the partitioning and mapping of the specification (cores) of the
MPSoC system into NoC mesh structure. The proposed methodology is described in Figure (3).
Thus, the main work will be as follows:
(1) To model the MPSoC system in a text-like C++ specification, this captures the data
dependencies among cores, which usually represented as data flow graph (DFG).
(2) To develop a genetic algorithm based solution to partition and map the cores of the MPSoC
system into mesh type NoC system.
(3) To produce a software program for the developed genetic algorithm in C++ programming
language to model the partitioning solution over the mesh NoC system.
However, the developed genetic algorithm is to make sure that all cores during the partitioning
process are mapped efficiently as close as possible to their interconnected cores and all cores
whose have an intensive communication and data transfer between them is placed closer than
others in order to reduce the routing timing and communication overheads between them.
Therefore, the employed genetic program is made in such a way that it easily finds one or more
“optimized” implementation(s) for a given MPSoC system over mesh NoC architecture by
7. International Journal of Computer Science & Information Technology (IJCSIT) Vol 13, No 1, February 2021
39
respecting the data flow dependencies and precedence constraints found in the supplied
specification between the SoC’ cores.
Design input
Check design
specification
Accept
design
specification
Apply genetic
algorithm
Check design
partitioning and
mapping results
Accept
design
paritioning?
Input :
Writing design
specification
Main phase :
Producing
suitable
partitioning
Report results:
Do design space
exploration
YES
YES
NO
Change genetic algorithm parameters
Report results:
Select efficient design
NO
Modify design specification
Output:
Selecting
different
implementations
Figure (3): The proposed partitioning and mapping methodology
5.1. Formal Definitions
The following definitions are provided that may help formally understand the partitioning and
mapping problem.
Definition 5.1.1:
MT is a set of operation types. Note that MT = { *, -, +, <>, /} in this paper examples.
Definition 5.1.2:
Core (component) graph (DFG) is a directed acyclic graph G (V, E1, )
Where:
V: is a set of vertices, each labeled with an operation using a mapping MT
V
:
.
E1: is a relation of the operations.
Note that a DFG does not have to be a single connected graph and a number of disconnected
graphs by design imply multiple, parallel data flows.
Definition 5.1.3:
A precedence relation between two operations viV and vjV is denoted by vi vj, where vi is
the immediate predecessor of vj and vj uses the result of operation vi. This data dependence will
8. International Journal of Computer Science & Information Technology (IJCSIT) Vol 13, No 1, February 2021
40
be defined as a precedence constraint during the mapping and scheduling process between the
two operations of the core which must be satisfied.
Definition 5.1.4:
: MT N+
is a resource constraint mapping, which assigns the number of functional units to
every operation type.
Definition 5.1.6:
A core library CL is a set of K cores,
Where
.
..
1
,
:
, j
i
j
i
j
i a
a
then
d
d
and
t
t
if
holds
j
i
and
K
j
i
j
i
Definition 5.1.7:
A system-on-chip is modeled as a directed acyclic graph SoC (VM, E2, CL)
Where
VM is a set of cores vi, vi CL.
E2 represents connections of the cores.
CL is a component library used for implementation.
Definition 5.1.8:
An implementation of a DFG G (V, E1, ) is a system-on-chip SoC (VM, E2 , CL) if mappings
exist:
VM
V
:
2
1
: E
E
Such that the DFG and SoC produce the same result for any input data.
5.2. Genetic Algorithm Design
Genetic algorithms are well-known global probabilistic search methods initially begins by
building an initial population of generated potential solutions to a problem, and progressively
advances towards better candidate solutions by applying genetic operators of crossover, mutation,
and potential elections of competent solutions reiteratively. Furthermore, the genetic algorithms
approach of have been employed to find optimized solutions on different design problems in
many engineering fields such as chip designs and networking [17][18][19][20]. However, genetic
algorithms technique doesn’t work with a single solution at a team, but it works concurrently
with a large group of candidate solutions which enable finding efficient solutions by discovering
the design space globally. Crossover is a reproduction technique that takes parent chromosomes
and mates them to new child chromosomes. Mutation is employed to search for different designs
in the design space in order to keep the range and the variations of the design population adequate
to find satisfactory solutions. In addition, fitness function is used to control and measure the
quality of the population progression toward better solutions, since the fitness of any obtained
solution during the design process that is a gained score marks how-much suitable the produced
solution while satisfying design goals. However, it is also known from these references that the
9. International Journal of Computer Science & Information Technology (IJCSIT) Vol 13, No 1, February 2021
41
evolutionary algorithm does not guarantee an optimal solution being reached in every run, but, if
the problem domain is ingeniously captured in the genetic algorithm, then it can outperforms
traditional solutions [20]. However, during the design process of the SoC using the genetic
program the designers seek to find one or more “optimized” implementation(s) for a given
system such that all cores are distributed and mapped efficiently so that the performance is
maximized and power dissipation is minimized by mapping all cores as close as possible to their
parents and interrelated cores which will reduce the routing process overhead of the targeted NoC
architecture.
Toward explaining the idea of the proposed genetic algorithm an example of video object plane
decoder is selected; as shown in Figure (4); as one of the standard benchmarks in the field to
demonstrate the results obtained by the applied technique. Figure (5) describes the data
dependencies relations between the nodes of the video object plane decoder.
Figure (4): Block diagram of video object plane decoder
Figure (5): Precedence relations of the cores of the SoC example
The designed algorithm starts by reading the following inputs, as illustrated in Figure (3): (1) the
specification of the MPSoC; (2) the size of the targeted NoC architecture (mesh size). Whereas
the expected output is to produce an optimized SoC design in such a way that the communication
10. International Journal of Computer Science & Information Technology (IJCSIT) Vol 13, No 1, February 2021
42
overheads are between cores are minimized; by placing interrelated cores as close as possible to
required design performance; if one exists, otherwise either the mesh size is changed or the
specification is revised or the genetic algorithm parameters is updated and applied again. What
can be said here, that designers able to change design parameters, employ their experience,
perform discussions within design teams in order to improve the reported design results. Since
genetic algorithm can report many suitable implementations; but one of them might be optimal.
(A) Creation of the first population
The developed genetic program begins with the creation of the parents from an initial population,
which are made up by two-dimensional two-array matrices (4 X 4) so that each matrix is a
generation of 16 chromosomes, and each matrix is represented by a number representing each
number of components (cores) of the SoC system. However, the chromosome looks as follows:
n1=1 , n2=2, n3=3, n4=4, n5=5, n6=6, n7=7, n8=8, n9=9, n10=10, n11=11, n12=12, n13=13,
n14=14, n15=15, n16=16.
Here, the distribution of chromosomes is random in both matrices, which named as parent1 and
parent2, which are the two base processes by which the new generations will be produced. The
generation of first population is stored into two random arrays par1, par2 as seen in tables below.
(B) Fitness calculation
The fitness function calculates the fitness of each generation, which is a two-dimensional matrix
based on measuring the distance between each core (HW component, processing node) and the
cores it needs to communicate with them in order to reduce the routing process overhead between
them using the Hamilton distance using the formula (H i, j = ǀ Xi – Xjǀ + ǀ Yi - Yjǀ).
For example in parent1 data, the Hamilton distance between core 12 and core 10 is equal to = 2,
whereas the distance between core 12 and core 11 = 3, the distance between core 12 and core 14
= 1, the distance between core 3 and core 13 = 2, the distance between core 3 and core 1 = 2, the
distance between core 3 and core 12 = 3, the distance between core 9 and core 13 = 3, the
distance between core 9 and core 7 = 5, the distance between core 9 and core 8 = 3, and the
distance between core 6 and core 5 = 1 and the distance between core 6 and core 4 = 5 and the
distance between core 6 and core 14 = 4 to be the total fitness output is the sum of the distances
between each core and the core that is needed here in this chromosome (matrix) = 33.
Parent2 has a distance between core 12 and element 10 = 2, the distance between element 12 and
element 11 = 5, the distance between element 12 and element 14 = 5, the distance between
element 3 and element 13 = 5, the distance between core3 and core1 = 3 and the distance between
core3 and core2 = 1, the distance between core9 and core13 = 2, the distance between core9 and
core7 = 3, the distance between core9 and core8 = 1, the distance between core6 and core5 = 2,
the distance between core6 and core4 = 3, and the distance Between core6 and core14 = 4.
Therefore the total fitness result is the sum of the distances between each core and its related
cores, which for this chromosome = 36.
Parent1
03
02
14
01
16
08
04
11
15
09
05
13
12
06
10
07
Parent2
06
07
11
10
05
01
02
14
16
15
13
12
08
03
04
09
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43
The best generation is elected by comparing Parent1with Parent2, which shown in below. In this
example the second father whose fitness is equal to 46 is selected because it is less than the first
father’ fitness value which equals to 63, then it is stored as the solution of the best father to enter
the new cycle of generations to elect who is better than him if it is found in future generations, as
shown below.
(C) Rotary processing
Here the rotary is entered and we have said that it represents the number of generated generations
in this algorithm and the first thing inside this rotary is to convert the two binary matrices into
two monolithic matrices so that the program performs the crossover and mutation and other
operations within a rotary that we initially defines as to be 10, 20, 100, 1000, or 10000. It
represents the number of generated generations that will be created and the comparison between
them and who will be selected represents the best optimization solution.
Parent 1
8
3
4
9
16
15
13
12
5
1
2
14
6
7
11
10
Parent2
12
6
10
7
15
9
5
13
16
8
4
11
3
2
14
1
(D) Crossover
The proposed genetic algorithm performs the crossover process by selecting one common point
between the two matrices of the parents which need to make an exchange of their two matrices
parts between them at the specified crossover point in order to form two new children namely
child1 and child2. In this step there are some iterations in some values i.e. there are repeated
values in each matrix, and these are resolved by the program directly, where the developed
algorithm excludes any repeated values in the matrix and put a value that does not exist to
prevent the process of repetition in one generation and this repair is done in the same part of the
crossover process. The output from the program execution of the crossover is shown below.
One- point crossover
Parent1
8
3
4
9
16
15
13
12
5
1
2
14
6
7
11
10
Parent2
12
6
10
7
15
9
5
13
16
8
4
11
3
2
14
1
After crossover and repair
Parent1
03
02
14
01
16
08
04
11
15
09
05
13
12
06
10
07
Parent2
06
07
11
10
05
01
02
14
16
15
13
12
08
03
04
09
12. International Journal of Computer Science & Information Technology (IJCSIT) Vol 13, No 1, February 2021
44
child1
8
11
10
9
16
13
15
12
5
6
4
7
3
2
14
1
child2
12
4
1
3
15
9
5
13
16
8
2
14
6
7
11
10
(E) Mutation
In this step, the mutation of the generation process is done, which is made by choosing two
random children in the same generation and is switched between them to create a genetic
mutation, and this process is usually applied after a number of cycles and here we have chosen to
be perform the mutation process after every five cycles during the program execution period. The
following tables show the steps of the mutation with mutation results.
Before mutation
Child 1
8
11
10
9
16
13
15
12
5
6
4
7
3
2
14
1
Child 2
12
4
1
3
15
9
5
13
16
8
2
14
6
7
11
10
After mutation
Child 1
8
11
10
3
16
13
15
12
5
6
4
7
9
2
14
1
Child 2
12
4
1
6
15
9
5
13
16
8
2
14
3
7
11
10
(F) Election of the best generation
Now, in this step, the two single matrices must be returned to two pairs to complete the selection
or distinction process, which is the election of the best generation that is made by calculation and
record-keeping of fitness’s value of each generation.
(G) Fitness recalculation
The fitness of each generation is calculated by a function of measuring the Hamilton distance
between each node or core with all other components or cores that it needs to communicate with
them, i.e. route packets between them, by the formula: H i, j = ǀ Xi –Xj ǀ + ǀ Yi - Yj ǀ. However,
the process of electing the best generation between the two generations of new child1 and child2
is done by comparing the best generation of parent1or parent2, and electing the best one of them.
13. International Journal of Computer Science & Information Technology (IJCSIT) Vol 13, No 1, February 2021
45
(H) Obtaining the optimized solution
The rotary returns if the number of revolutions (the generations) has not ended and the same
previous operations are performed again so that the best matrix is registered and it is the best
generation in terms of fitness. Thus, an optimized solution is found; which could be an optimal
solution. Mapping results to 4X4 mesh NoC topology.
Mapping
Final
9n
1n
13n
14n
10n
3n
11n
15n
8n
7n
2n
12n
16n
4n
5n
6n
(I) Designer intervention
Note: The designer still can have the ability to change and move nodes mappings to achieve and
realize his/her point of to the design.
6. PRACTICAL RESULTS
Figure (6) describes the dependency graph of standard multimedia benchmark of CCG VOPD
multimedia algorithm, and Figure (7) illustrates the MPEG4 multimedia algorithm, while Figure
(8) shows the audio video multimedia algorithm, see [22][23][24].
Figure (6): The mapping results of CCG multimedia algorithm
Figure (7): The mapping results of MPEG4 multimedia algorithm
mapping
Final
CCG
x
x
1
0
x
3
4
2
11
10
5
x
9
8
6
7
mapping
Final
MPEG4
x
x
6
12
2
4
11
7
9
5
3
x
x
1
10
8
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Figure (8): The mapping results of audio video(AV) benchmark with 18 cores
7. CONCLUSION
We applied the presented approach on various multimedia benchmark applications with
experimental results showing that it is possible to find efficient (not necessary optimal) MPSoC
mapped designs using the genetic algorithm. Thus, from the results of implemented benchmark
examples we can say that the realized genetic program of mapping-cores approach is producing
practically efficient results which can aid to explore the MPSoC design space carefully.
Consequently, it is clear that the results of mapping MPSoC cores using mesh as a NoC topology
satisfies design specified goals in terms of reducing communication cost and power consumption.
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