The document describes various digital logic integrated circuits (ICs) including their pin configurations, logic levels, truth tables and functions. It provides details for common ICs like NAND, NOR, AND, OR gates, flip-flops, decoders, multiplexers, comparators and counters. The document serves as a reference for the pin connections, symbols and operating modes of different digital logic family ICs.

1. Digital IC Pin Details and Functional Tables
1) 7400 QUAD 2 INPUT NAND GATE:
𝒀 = 𝑨𝑩
̅̅̅̅
H=High Logic Level
L=Low Logic Level
2) 7402 QUAD 2 INPUT NOR GATE:
𝒀 = 𝑨 + 𝑩
̅̅̅̅̅̅̅̅
H=High Logic Level
L=Low Logic Level
3) 7404 HEX INVERTER/NOT GATE:
𝒀 = 𝑨
̅
H=High Logic Level
L=Low Logic Level
Inputs Output
A B Y
L L H
L H H
H L H
H H L
Inputs Output
A B Y
L L H
L H L
H L L
H H L
Input Output
A Y
L H
H L

2. 4) 7408 QUAD 2 INPUT AND GATE:
𝒀 = 𝑨𝑩
H=High Logic Level
L=Low Logic Level
5) 7410 TRIPLE 3 INPUT NAND GATE:
𝒀 = 𝑨𝑩𝑪
̅̅̅̅̅̅
H=High Logic Level
L=Low Logic Level
X=Either Low or High Logic Level
6) 7411 TRIPLE 3 INPUT AND GATE:
𝒀 = 𝑨𝑩𝑪
H=High Logic Level
L=Low Logic Level
X=Either Low or High Logic Level
Inputs Output
A B Y
L L L
L H L
H L L
H H H
Inputs Output
A B C Y
X X L H
X L X H
L X X H
H H H L
Inputs Output
A B C Y
X X L L
X L X L
L X X L
H H H H

3. 7) 7420 DUAL 4 INPUT NAND GATE:
𝒀 = 𝑨𝑩𝑪𝑫
̅̅̅̅̅̅̅̅̅
H=High Logic Level
L=Low Logic Level
X=Either Low or High Logic Level
8) 7421 DUAL 4 INPUT AND GATE:
𝒀 = 𝑨𝑩𝑪𝑫
H=High Logic Level
L=Low Logic Level
X=Either Low or High Logic Level
9) 7427 TRIPLE 3 INPUT NOR GATE:
𝒀 = 𝑨 + 𝑩 + 𝑪
̅̅̅̅̅̅̅̅̅̅̅̅̅
H=High Logic Level
L=Low Logic Level
X=Either Low or High Logic Level
Inputs Output
A B C D Y
X X X L H
X X L X H
X L X X H
L X X X H
H H H H L
Inputs Output
A B C D Y
X X X L L
X X L X L
X L X X L
L X X X L
H H H H H
Inputs Output
A B C Y
X X H L
X H X L
H X X L
L L L H

4. 10) 74LS30 - 8 INPUT NAND GATE:
𝒀 = 𝑨𝑩𝑪𝑫𝑬𝑭𝑮𝑯
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
H=High Logic Level
L=Low Logic Level
11) 7432 QUAD 2 INPUT OR GATE:
𝑌 = 𝐴 + 𝐵
H=High Logic Level
L=Low Logic Level
12) 7446/7447 BCD TO SEVEN SEGMENT DECODER:
Inputs Output
A through H Y
All inputs H L
One or more inputs L H
Inputs Output
A B Y
L L L
L H H
H L H
H H H
Symbol Description
A, B, C, D BCD inputs
RBI
̅̅̅̅̅ Ripple-Blanking Input
LT Lamp-Test Input
BIRBO
̅̅̅̅̅̅̅̅̅̅ Blanking Input or
Ripple-Blanking Output
𝑎
̅to 𝑔̅ Outputs

6. 13) 7448 BCD TO SEVEN SEGMENT DECODER:
H=High Logic Level
L=Low Logic Level
X=Either Low or High Logic Level
Symbol Description
A, B, C, D BCD inputs
RBI
̅̅̅̅̅ Ripple-Blanking Input
𝐿𝑇
̅
̅̅
̅ Lamp-Test Input
BIRBO
̅̅̅̅̅̅̅̅̅̅ Blanking Input or
Ripple-Blanking Output
𝑎 to 𝑔 Outputs

7. 14) 7473 DUAL J-K FLIP-FLOP:
Symbol Description
Q True output
Q
̅ Complement Output
Clock Clock input
J Data input1
K Data input2
RESET
Asynchronous reset
(Low activated)
GND Ground
VCC Supply Voltage

8. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition;
X = don’t care;
= HIGH-to-LOW clock transition.
15) 7474 DUAL D FLIP-FLOP:
Symbol Description
Q True output
Q
̅ Complement Output
CLK Clock input
D Data input
CLR
Asynchronous reset
(active low)
PR
Asynchronous set
(active low)
GND Ground
VCC Supply Voltage
Inputs Outputs
Operating mode
RESET Clock J K Q Q
̅
L X X X L H Asynchronous reset (Low activated)
H h h 𝑞
̅ q Toggle
H l h L H Load 0 (reset)
H h l H L Load 1 (set)
H l l q 𝑞
̅ Hold (no change)
Inputs Outputs
Operating mode
PR CLR CLK D Q Q
̅
L H X X H L Asynchronous set (Low activated)
H L X X L H Asynchronous reset (Low activated)
L L X X H H Note1
H H h H L Load 1 (set)
H H l L H Load 0 (reset)
H H L X q 𝑞
̅ Hold (no change)

9. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Note1: This configuration is nonstable; That is, it will not persist when either the preset andor clear inputs return to
their inactive (HIGH) level.
16) 7478 DUAL J-K FLIP-FLOP WITH PRESET, COMMON CLOCK, AND
COMMON CLEAR:
Symbol Description
Q True output
Q
̅ Complement Output
CLK Clock input
J Data input1
K Data input2
CLR
Asynchronous reset
(Low activated)
PR
Asynchronous set
(Low activated)
GND Ground
VCC Supply Voltage
Inputs Outputs
Operating mode
PR CLR Clock J K Q Q
̅
L H X X X H L Asynchronous set (Low activated)
H L X X X L H Asynchronous reset (Low activated)
L L X X X H H Note 1
H H h h 𝑞
̅ q Toggle
H H l h L H Load 0 (reset)
H H h l H L Load 1 (set)
H H l l q 𝑞
̅ Hold (no change)
H H H X X q 𝑞
̅ Hold (no change)

10. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition;
X = don’t care;
= HIGH-to-LOW clock transition.
Note1: This configuration is nonstable; That is, it will not persist when either the preset andor clear inputs return to
their inactive (HIGH) level.
17) 7485 – 4 BIT MAGNITUDE COMPARATOR:
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care
Symbol Description
A0-A3, B0-B3 Parallel inputs
IA=B A=B Expander inputs
IA<B, IA>B
A<B, A>B,
Expander inputs
OA>B A greater than B output
OA<B B greater than A output
OA=B A equal to B output

11. 18) 7486 – QUAD 2 INPUT EXCLUSIVE OR GATE:
𝑌 = 𝐴⨁𝐵 = 𝐴̅𝐵 + 𝐴𝐵
̅
H = HIGH voltage level;
L = LOW voltage level;
19) 7490 ASYNCHRONOUS DECADE COUNTER:
H = HIGH voltage level;
L = LOW voltage level;
X=Either Low or High Logic Level
Inputs Output
A B Y
L L L
L H H
H L H
H H L
Symbol Description
𝐶𝑃0
̅̅̅̅̅ Clock (Active LOW going edge) Input to divide by
2 Section
𝐶𝑃1
̅̅̅̅̅ Clock (Active LOW going edge) Input to divide by
5 Section
MR1, MR2 Master Reset (Clear) Inputs
MS1, MS2 Master Set (Preset-9) Inputs
Q0 Output from divide by 2 Section
Q1, Q2, Q3 Outputs from divide by 5 Section

12. 20) 7493 ASYNCHRONOUS BINARY COUNTER:
H = HIGH voltage level;
L = LOW voltage level;
X=Either Low or High Logic Level
21) 74112 JK FLIP FLOP WITH PRESET AND CLEAR:
Symbol Description
𝐶𝑃0
̅̅̅̅̅ Clock (Active LOW going edge) Input to divide by
2 Section
𝐶𝑃1
̅̅̅̅̅ Clock (Active LOW going edge) Input to divide by
5 Section
MR1, MR2 Master Reset (Clear) Inputs
Q0 Output from divide by 2 Section
Q1, Q2, Q3 Outputs from divide by 5 Section
Symbol Description
Q True output
Q
̅ Complement Output
CLK Clock input
J Data input1
K Data input2
CLR
Asynchronous reset
(Low activated)
PR
Asynchronous set
(Low activated)
GND Ground
VCC Supply Voltage

13. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition;
X = don’t care;
= HIGH-to-LOW clock transition.
Note1: This configuration is nonstable; That is, it will not persist when either the preset andor clear inputs return to
their inactive (HIGH) level.
22) 74138 -3:8 DECODER:
Inputs Outputs
Operating mode
PR CLR Clock J K Q Q
̅
L H X X X H L Asynchronous set (Low activated)
H L X X X L H Asynchronous reset (Low activated)
L L X X X H H Note 1
H H h h 𝑞
̅ q Toggle
H H l h L H Load 0 (reset)
H H h l H L Load 1 (set)
H H l l q 𝑞
̅ Hold (no change)
H H H X X q 𝑞
̅ Hold (no change)
Symbol Description
A0-A2 Address inputs
𝐸1
̅̅̅̅, 𝐸2
̅̅̅̅ Enable (Active low) inputs
E3 Enable (Active high) input
𝑂
̅0 − 𝑂
̅7 Active low outputs

14. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care
23) 74139 -2:4 DECODER:
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care
Inputs Outputs
E1 E2 E3 A0 A1 A2 𝑂
̅0 𝑂
̅1 𝑂
̅2 𝑂
̅3 𝑂
̅4 𝑂
̅5 𝑂
̅6 𝑂
̅7
H X X X X X H H H H H H H H
X H X X X X H H H H H H H H
X X L X X X H H H H H H H H
L L H L L L L H H H H H H H
L L H H L L H L H H H H H H
L L H L H L H H L H H H H H
L L H H H L H H H L H H H H
L L H L L H H H H H L H H H
L L H H L H H H H H H L H H
L L H L H H H H H H H H L H
L L H H H H H H H H H H H L
Symbol Description
A0-A2 Address inputs
E
Enable (Active low)
inputs
𝑂
̅0 − 𝑂
̅3 Active low outputs
Inputs Outputs
E A0 A1 𝑂
̅0 𝑂
̅1 𝑂
̅2 𝑂
̅3
H X X H H H H
L L L L H H H
L H L H L H H
L L H H H L H
L H H H H H L

15. 24) 74147 -10 LINE TO 4 LINE PRIORITY ENCODER:
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care

16. 25) 74148 -8 LINE TO 3 LINE PRIORITY ENCODER:
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care
Note: 74148 provides cascading circuitry (Enable input EI and enable output EO) octal expansion without the need
for external circuitry. GS is the glitch free output.

17. 26) 74151 -8:1 MULTIPLEXER:
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care
Symbol Description
S0-S2 Select inputs
E
Enable (Active low)
input
I0-I7 Multiplexer inputs
Z Multiplexer output
𝑍̅ Complementary
multiplexer output

18. 27) 74153 -4:1 MULTIPLEXER:
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care
Symbol Description
S0-S1 Select inputs
𝐸
̅ Enable (Active low)
input
I0-I3 Multiplexer inputs
Z Multiplexer output

19. 28) 74154 – 4:16 DECODER / DEMULTIPLXER:
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care
Symbol Description
A-D Address inputs
𝐺1
̅̅̅̅-𝐺2
̅̅̅̅ Strobe (Active low)
inputs
0-15 Active low outputs
Inputs Outputs
𝐺1
̅̅̅ 𝐺2
̅̅̅ D C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
L L L L L L L H H H H H H H H H H H H H H H
L L L L L H H L H H H H H H H H H H H H H H
L L L L H L H H L H H H H H H H H H H H H H
L L L L H H H H H L H H H H H H H H H H H H
L L L H L L H H H H L H H H H H H H H H H H
L L L H L H H H H H H L H H H H H H H H H H
L L L H H L H H H H H H L H H H H H H H H H
L L L H H H H H H H H H H L H H H H H H H H
L L H L L L H H H H H H H H L H H H H H H H
L L H L L H H H H H H H H H H L H H H H H H
L L H L H L H H H H H H H H H H L H H H H H
L L H L H H H H H H H H H H H H H L H H H H
L L H H L L H H H H H H H H H H H H L H H H
L L H H L H H H H H H H H H H H H H H L H H
L L H H H L H H H H H H H H H H H H H H L H
L L H H H H H H H H H H H H H H H H H H H L
L H X X X X H H H H H H H H H H H H H H H H
H L X X X X H H H H H H H H H H H H H H H H
H H X X X X H H H H H H H H H H H H H H H H

20. 29) 74155 – 2:4 DECODER / DEMULTIPLXER:
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care
30) 74160 – BCD DECADE COUNTERS:
Symbol Description
A0-A1 Address inputs
𝐸
̅ Enable (Active low)
inputs
𝑂
̅0-𝑂
̅3 Active low outputs
Symbol Description
𝑃𝐸
̅̅̅̅ Parallel Enable (Active low)
inputs
𝑃0 − 𝑃3 Parallel inputs
CEP Count Enable parallel input
CET Count Enable Trickle input
CP
Clock (Active high going
edge) input
MR
Master reset (Active low)
input
𝑄0 − 𝑄3 Parallel outputs
TC Terminal count output

21. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care
31) 74168 – BCD DECADE BI-DIRECTIONAL COUNTERS:
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care
Symbol Description
𝑃𝐸
̅̅̅̅ Parallel Enable (Active low)
inputs
𝑃0 − 𝑃3 Parallel Data inputs
CEP
Count Enable parallel input
(Active low)
𝐶𝐸𝑇
̅̅̅̅̅̅ Count Enable Trickle input
(Active low)
CP
Clock (Active positive going
edge) input
𝑈/𝐷
̅ Up-Down Count Control
Input
𝑄0 − 𝑄3 Parallel outputs
𝑇𝐶
̅̅̅̅ Terminal count output

22. 32) 74170 – 4 X 4 REGISTER FILE:
Write Function
Read Function
 H = HIGH voltage level; L = LOW voltage level; X = don’t care;
 (Q = D) = The four selected internal flip-flop outputs will assume the states applied to the four external data
inputs.
 Q0 = the level of Q before the indicated input conditions were established.
 W0B1 = The first bit of word 0, etc.
Symbol Description
𝐷1 − 𝐷4 Data inputs
𝑊𝐴, 𝑊𝐵 Write Address Inputs
𝐸
̅𝑊
Write Enable
(Active LOW) Input
𝑅𝐴, 𝑅𝐵 Read Address Inputs
𝐸
̅𝑅
Read Enable
(Active LOW) Input
𝑄1 − 𝑄4 Outputs

23. 33) 74181 – 4 BIT ARITHMETIC LOGIC UNIT:
Symbol Description
𝐴̅0 − 𝐴̅3 Operand (Active LOW) Inputs
𝐵
̅0 − 𝐵
̅3 Operand (Active LOW) Inputs
𝑆0 − 𝑆3 Function – select inputs
M Mode Control Input
𝐶𝑛 Carry Input
𝐹
̅0 − 𝐹
̅3 Function (Active LOW) Outputs
A=B Comparator Output
𝐺̅ Carry Generator (Active LOW) Output
𝑃
̅ Carry Propagate (Active LOW) Output
𝐶𝑛+1 Carry Output

24.  L = LOW Voltage Level
 H = HIGH Voltage Level
 *Each bit is shifted to the next more significant position
 **Arithmetic operations expressed in 2s complement notation
34) 74190 – PRESETTABLE BCD/DECADE UP/DOWN COUNTERS:

25. Mode select table
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care
35) 74194 – 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER COUNTERS:
Symbol Description
𝐶𝐸
̅̅̅̅ Count Enable (Active LOW) Input
CP Clock Pulse (Active HIGH going edge) Input
𝑈
̅/D Up/Down Count Control Input
𝑃𝐿
̅̅̅̅ Parallel Load Control (Active LOW) Input
Pn Parallel Data Inputs
Qn Flip-Flop Outputs
𝑅𝐶
̅̅̅̅ Ripple Clock Output
TC Terminal Count Output

26.  H = HIGH voltage level;
 L = LOW voltage level;
 X = don’t care
 I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition
 h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition
 pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time
prior to the LOW to HIGH clock transition.
Symbol Description
𝑆0, 𝑆1 Mode Control Inputs
𝑃0 − 𝑃3 Parallel Data Inputs
𝐷𝑆𝑅 Serial (Shift Right) Data Input
𝐷𝑆𝐿 Serial (Shift Left) Data Input
𝐶𝑃 Clock (Active HIGH Going Edge) Input
𝑀𝑅
̅̅̅̅̅ Master Reset (Active LOW) Input
𝑄0 − 𝑄3 Parallel Outputs

27. 36) 74280 – 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS:
Function Table:
37) 74283 – 4-BIT BINARY FULL ADDER WITH FAST CARRY:

28. Example:
Function Truth Table:
C1-C3 are generated internally
C0 is an external input
C4 is an output generated internally
Symbol Description
𝐴1 − 𝐴4 Operand A Inputs
𝐵1 − 𝐵4 Operand B Inputs
𝐶0 Carry Input
∑1 − ∑4 Sum Outputs
𝐶4 Carry Output

29. 38) LT-542 SEVEN SEGMENT DISPLAY (COMMON ANODE):
39) LT-540 SEVEN SEGMENT DISPLAY (COMMON CATHODE):
dp
d
g
a
f b
e c
a
VCC
g f b
c
VCC
e d dp
LT542