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MODULE TITLE : PROGRAMMABLE LOGIC
CONTROLLERS
TOPIC TITLES : PROGRAMMABLE FACILITIES AND
ADDITIONAL FACILITIES
TUTOR MARKED ASSIGNMENT 3
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TELEPHONE......................................................
PLC - 3 - TMA (v1)
© Teesside University 2011
THIS BOX MUST BE COMPLETED
Student Code No.
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Student's Signature
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Date Submitted
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Contact e-mail
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Published by Teesside University Open Learning (Engineering)
School of Science & Engineering
Teesside University
Tees Valley, UK
TS1 3BA
+44 (0)1642 342740
All rights reserved. No part of this publication may be
reproduced, stored in a
retrieval system, or transmitted, in any form or by any means,
electronic, mechanical,
photocopying, recording or otherwise without the prior
permission
of the Copyright owner.
This book is sold subject to the condition that it shall not, by
way of trade or
otherwise, be lent, re-sold, hired out or otherwise circulated
without the publisher's
prior consent in any form of binding or cover other than that in
which it is
published and without a similar condition including this
condition being imposed on the subsequent purchaser.
IMPORTANT
Before you start please read the following instructions
carefully.
1. This assignment forms part of the formal assessment for this
module. If
you fail to reach the required standard for the assignment then
you will be
allowed to resubmit but a resubmission will only be eligible for
a Pass
grade, not a Merit or Distinction.
You should therefore not submit the assignment until you are
reasonably
sure that you have completed it successfully. Seek your tutor's
advice if
unsure.
2. Ensure that you indicate the number of the question you are
answering.
3. Make a copy of your answers before submitting the
assignment.
4. Complete all details on the front page of this TMA and return
it with
the completed assignment including supporting calculations
where
appropriate. The preferred submission is via your TUOL(E)
Blackboard
account:
https://eat.tees.ac.uk
5. Your tutor’s comments on the assignment will be posted on
Blackboard.
1
Teesside University Open Learning
(Engineering)
© Teesside University 2011
1. Design and draw a ladder diagram circuit suitable for a PLC
which will
fulfil the following control requirement:
A momentary push switch is to be recognised, remembered and
used to
switch on an output for a period of 30 seconds. After 30
seconds this
output is to be switched off and must be off for 0.5 seconds
before a
second output switches on.
The second output remains on until a second push switch is
operated to
turn it off. If the second push is operated at any time then the
current
output must turn off and the system await the press of the first
push. The
rungs of the ladder diagram must contain interlock contacts
which prevent
both outputs being on at the same time.
2. Redesign and improve the pelican crossing ladder diagram
given of
FIGURE 1 of lesson PLC - 6 - 2 by adding timer rungs and
counter rungs
between rungs 12 and 14 (or any similar workable scheme)
together with
the necessary contacts inserted in the amber and green man
lights of rungs
7 and 10, etc. The chart below shows the required sequence of
events.
Note that a section of the chart is repeated a total of 16 times.
The time
intervals are given below.
Time periods 1 2 3 4 5 6 7 ....... 35 36 37
Green road light ON ON OFF OFF OFF OFF .......... OFF OFF
ON
Red road light OFF OFF OFF ON OFF OFF .......... OFF OFF
OFF
Amber road light OFF OFF ON OFF ON OFF .......... ON OFF
OFF
Wait sign OFF ON ON OFF OFF OFF .......... OFF OFF OFF
Green man OFF OFF OFF ON ON OFF .......... ON OFF OFF
Red man ON ON ON OFF OFF OFF .......... OFF OFF ON
first sixteenth
occurrence time
� �� ��� �� ��
2
Teesside University Open Learning
(Engineering)
© Teesside University 2011
Time period 1 is the 'normal' conditions.
Time period 2 is after the pedestrian presses the push button.
The change from period 2 to period 3 can only be made after at
least one
five second check of the road sensors.
The time interval between 3 and 4 is 4 seconds.
The time interval between 4 and 5 is 10 seconds.
The time interval between 5 and 6 is 0.5 seconds.
The time interval between 6 and 7 is 0.5 seconds.
It is not necessary to show the whole of the traffic light ladder
diagram of
lesson PLC - 6 - 2, only rungs which have been modified.
There must,
however, be a comprehensive explanation of the operation of
the
modified rungs accompanying the modified ladder diagram.
3
Teesside University Open Learning
(Engineering)
© Teesside University 2011
3. The chart below shows a required set of step sequences with
the same
time interval between steps.
Provide a ladder diagram and a comprehensive explanation as a
solution
for this chart by using two eight-bit shift registers (SFT0
controls relays
50 to 57, SFT1 controls relays 60 to 66). The sequence is to
have an
initial start signal and thereafter can be free running. A reset
control and
timer to clock the shift registers must be provided.
STEP No. OUT0 OUT1 OUT2 OUT3 OUT4 OUT5
RESET all outputs off RESET
1 ON 1
2 ON ON 2
3 ON ON ON 3
4 ON ON ON 4
5 ON ON ON 5
6 ON ON ON 6
7 ON ON 7
8 ON 8
9 ON ON 9
10 ON ON ON 10
11 ON ON ON 11
12 ON ON ON 12
13 ON ON ON 13
14 ON ON 14
15 ON STEP 1 and 15
Return to step 2
4
Teesside University Open Learning
(Engineering)
© Teesside University 2011
4. (a) An A/D conversion circuit with 10 bit resolution has an
input range
of 0 – 5 V. A second has a 12 bit resolution and an input range
of
0 – 10 V. Calculate the digital output value that will represent
a 2 V
input for both of the A/D converters. Convert the digital levels
in
both cases to hexadecimal and then to binary values.
(b) Explain briefly from what you notice about the digital
output values
in (a) why a digital output value of an A/D converter is rarely
the
exact same digital value as the analogue input value.
(c) State briefly why a PLC A/D module haveing 4 analogue
input
channels would probably not incorporate 4 internal A/D
circuits.
(d) State briefly which of the two digital output values in (a) is
the more
accurate and why.
5. Explain briefly the technique of multiplexed switching of
analogue
signals.
6. The diagram of FIGURE 1 shows a 3 input R/2R digital to
analogue
converter circuit. By working back from the output (or
otherwise) to find
the equivalent input resistance in order to determine the input
voltage,
show that the output voltage values for the following digital
input
combinations are as shown below.
(i)
(ii)
(iii)
(iv)
A B C (volts)
0 0 0
1 0 0
0 0 1
4
12
or
1
3
out
in
in
V
V
V
0
1
12
VV
V V
in
in in1 1
3
12
or
1
4
0
5
Teesside University Open Learning
(Engineering)
© Teesside University 2011
FIG. 1
7. State briefly:
(i) what is meant by a LAN
(ii) types of LAN
(iii) an application of LANs
(iv) the types of cable likely to be used in a LAN
(v) the meaning of RTU
(vi) what the current title of EIA–422 is and to what it relates
(vii) to what the protocal IEEE-488 relates.
A B C
2R 2R 2R
R R
2R 2R
0 volts
Analogue output
V
out
F E
D
6
Teesside University Open Learning
(Engineering)
© Teesside University 2011
Teesside University Open Learning
(Engineering)
© Teesside University 2011
Question
No.
Teesside University Open Learning
(Engineering)
© Teesside University 2011
Question
No.
Teesside University Open Learning
(Engineering)
© Teesside University 2011
Question
No.
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2d0064006f006b0075006d0065006e00740020006d00650064002
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006f006b0075006d0065006e00740065006e0020006b0061006e0
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630072006f0062006100740020006f00630068002000520065006
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06100200069006e0073007400e4006c006c006e0069006e006700
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