MICRO ELECTRO MECHANICAL SYSTEMS

1. Lecture #08
MOSFET Fabrication
Department of Instrumentation & Control Engineering, MIT, Manipal
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2. Department of Instrumentation & Control Engineering, MIT, Manipal
Contents
1. CMOS inverter cross-section
2. Fabrication procedure
3. Inverter cross-section with well and substrate taps
4. Flow diagram
5. Fabrication procedure – Basic steps
6. Mask set
7. Fabrication steps
8. Testing
9. Die cut and assembly
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3. Inverter Cross-section
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• Typically use p-type substrate for nMOS transistors
• Requires n-well for body of pMOS transistors
GND VDD
n+
n+ p+
p substrate
p+
n well
A
Y
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor

4. Fabrication Procedure
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• Well
– Requires to build both pMOS and nMOS on single wafer.
– To accommodate both pMOS and nMOS devices, special
regions must be created in which the semiconductor type
is opposite of the substrate type.
– Also Known as Tubs.
– Twin-tubs
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

5. Inverter Cross-section with Well and Substrate taps
ON
OFF
5
• Typically use p-type substrate for nMOS transistors
• Requires n-well for body of pMOS transistors
• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor
connection
• Use heavily doped well and substrate contacts / taps
GND VDD
n+ p+
p+ n+
n+
p substrate
p+
n well
A
Y
substrate tap well tap
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
VDD
A=0 Y=1
GND

6. Flow Diagram
Create n-Well regions and
Channel Stops region
Grow Field Oxide and
Gate Oxide
Deposit and pattern
Polysilicon Layer
Implant sources, drain regions
and substrate contacts
Create contact Windows,
deposit and pattern metal layer
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal 6

7. Fabrication Procedure – Basic Steps
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• Masks: Each Processing steps in the fabrication procedure requires
to define certain area on the chip. This is known as Masks.
• Chips are specified with set of masks
• Minimum dimensions of masks determine transistor size (and hence
speed, cost, and power)
• Feature size f = distance between source and drain
– Set by minimum width of polysilicon
• Feature size improves 30% every 3 years or so
• Normalize for feature size when describing design rules
• The ICs are viewed as a set of pattern layers of doped Silicon,
Polysilicon, Metal and Insulating Silicon Dioxide.
• A layer must be Patterned before the next layer of material is
applied on the chip.
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

8. Inverter Mask Set
8
• Transistors and wires are defined by masks
• Cross-section taken along dashed line
A
Y
GND VDD
nMOS transistor pMOS transistor
substrate tap well tap
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

9. Detailed Mask Views
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• Six masks
– n-well
– Polysilicon
– n+ diffusion
– p+ diffusion
– Contact
– Metal
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
n well
Polysilicon
n+ Diffusion
p+ Diffusion
Contact
Metal

10. Fabrication Steps
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• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2
p substrate
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

11. Oxidation
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• Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace
p substrate
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
SiO2

12. Photoresist
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• Used for lithography.
• Lithography is a process used to transfer a pattern to layer on
the chip. Similar to printing process.
• Spin on photoresist (about 1 mm thickness)
– Photoresist is a light-sensitive organic polymer
– Positive Photoresist: Softens where exposed to light
– Negative Photoresist: Harden where exposed to light, Not
used in practice generally.
p substrate
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
Photoresist
SiO2

13. Lithography
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• Expose photoresist through n-well mask
• Strip off exposed photoresist
p substrate
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
Photoresist
SiO2

14. Etch
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• Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been exposed
p substrate
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
Photoresist
SiO2

15. Strip Photoresist
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• Strip off remaining photoresist
– Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step
p substrate
SiO2
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

16. n Well
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• n-well is formed with diffusion or ion implantation
• Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
• Ion Implantation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
n well
SiO2
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

17. Strip Oxide
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• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps
p substrate
n well
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

18. Polysilicon
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• Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Polysilicon
Thin gate oxide
p substrate
n well
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

19. Polysilicon Patterning
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• Use same lithography process to pattern polysilicon
Polysilicon
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
Polysilicon
p substrate
Thin gate oxide
n well

20. n Diffusion
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• Use oxide and masking to expose where n+ dopants should be
diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well contact
p substrate
n well
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

21. n Diffusion
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• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates because it
doesn’t melt during later processing
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
n+ Diffusion
p substrate
n well

22. n Diffusion
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• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion
n+ n+ n+
n well
p substrate
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

23. n Diffusion
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• Strip off oxide to complete patterning step
n+ n+ n+
n well
p substrate
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

24. p Diffusion
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• Similar set of steps form p+ diffusion regions for pMOS
source and drain and substrate contact
p+ n+ n+ p+ p+ n+
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
p+ Diffusion
p substrate
n well

25. Contacts
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• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed
p+ n+ n+ p+ p+ n+
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
Contact
p substrate
Thick field oxide
n well

26. Metalization
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• Sputter on aluminium over whole wafer
• Pattern to remove excess metal, leaving wires
p+ n+ n+ p+ p+ n+
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
Metal
p substrate
Metal
Thick field oxide
n well

27. Testing
Defective IC
Individual integrated circuits are
tested to distinguish good die
from bad ones.
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal 27

28. Die cut and assembly
Good chips are attached
to a lead frame package.
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal 28

29. Die Attach and Wire Bonding
lead frame gold wire
bonding pad
connecting pin
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal 29

30. Final Test
Chips are electrically
tested under varying
environmental conditions.
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal 30