1. Mani Srivastava
UCLA - EE Department
mbs@ee.ucla.edu
CMOS Technology
EE116B (Winter 2001): Lecture #3
2. Copyright 2001 Mani Srivastava
2
Reading for this Lecture
http://vlsi.wpi.edu/webcourse/ch02/ch02.html
3. Copyright 2001 Mani Srivastava
3
Silicon Semiconductor
Technology
Pure silicon is a semiconductor
bulk electrical resistance in between that of a
conductor and insulator
Conductivity of silicon can be varied several
orders of magnitude by introducing impurity atoms
called dopants
acceptors: accept electrons to leave holes in silicon
– lead to p-type silicon (e.g. Boron)
donors: provide electrons to silicon
– lead to n-type silicon (e.g. Arsenic, Phosphorous)
4. Copyright 2001 Mani Srivastava
4
CMOS Process
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
Semiconductor devices formed by bringing
together n & p type silicon to form junctions in
certain physical structures
5. Copyright 2001 Mani Srivastava
5
How is CMOS built?
Start with a disk of silicon called wafer
75 mm to 230 mm in diameter, < 1 mm thick
cut from ingots of single-crystal silicon
– pulled from a crucible of pure molten polycrystalline
silicon using a seed crystal
Layers of diffusion, polysilicon, and Aluminum
separated by insulating material
6. Copyright 2001 Mani Srivastava
6
Simplified View of CMOS
Fabrication Process
7. Copyright 2001 Mani Srivastava
7
Oxidation
Silicon Dioxide (SiO2) important to silicon ICs
therefore, its reliable manufacturing important
Oxidation of silicon achieved by heating silicon
wafers in an oxidizing atmosphere (O2 or H2O)
grows equally in both vertical directions
8. Copyright 2001 Mani Srivastava
8
Making Silicon with Donor or
Acceptor Impurities
Epitaxy
growing a single-crystal film on the silicon surface
– silicon wafer subjected to elevated temperatures and
a source of dopant material
Deposition
evaporating dopant material into the silicon surface
followed by thermal cycle to drive impurities from
silicon surface into the bulk
Ion Implantation
silicon surface subjected to highly energized donor
or acceptor atoms
– atoms impinge silicon surface, and drive below it to
form regions of varying concentrations
9. Copyright 2001 Mani Srivastava
9
Construction of Transistors
Depends on ability to control
what type dopant source
how many energy, time, temperature etc.
where using special material as “masks”
of impurities are introduced into silicon wafer
10. Copyright 2001 Mani Srivastava
10
Masks
Masks act as barrier against doping impurities
ion implantation does not occur in places covered
by mask, or dopant does not contact silicon
surface for diffusion to take place
Commonly used mask materials
photoresist
polysilicon
silicon dioxide (SiO2)
silicon nitride (SiN)
11. Copyright 2001 Mani Srivastava
11
Example: Oxide Mask
Key idea:
SiO2 surface is covered with a photoresist which is
acid resistant
photoresist is selectively polymerized by UV light, and
removed in those places by a solvent
exposed SiO2 is now etched
The above is called positive resist
negative photoresist: unexposed photoresist is
dissolved
Diffraction of UV around edges of mask pattern,
and alignment tolerances, limit line widths
electron beam lithography has emerged
– direct: no intermediate hardware masks
12. Copyright 2001 Mani Srivastava
12
Patterning of SiO2
a. bare silicon wafer
b. wafer with SiO2 & resist
c. exposing resist to UV light
d. final etched SiO2
13. Copyright 2001 Mani Srivastava
13
Silicon Gate Process
Silicon also comes in a polycrystalline form
called polysilicon, or just poly
high resistance
– normally doped at the same time as source/drain regions
Used as
an interconnect in silicon ICs
gate electrode in MOS transistors
most important: acts as a mask to allow precise
definition of source and drain extension under gate
– minimum gate to source/drain overlap improves circuit
performance (why?)
– called self-aligned process
14. Copyright 2001 Mani Srivastava
14
Fabrication Steps for a Silicon
Gate NMOS Transistor
a. patterning SiO2 layer
b. gate oxidation
c. patterning polysilicon
15. Copyright 2001 Mani Srivastava
15
Fabrication Steps for a Silicon
Gate NMOS Transistor (contd.)
d. implant or diffusion
e. contact cuts
f. patterning of Aluminum layer
16. Copyright 2001 Mani Srivastava
16
A Basic N-well CMOS Process
a. Define the N well
b. Active mask to
define where thin
oxide is needed to
define transistor gates
c. Channel stop
implant uses p-well
mask to dope p-
substrate p+ in areas
with no n transistors
17. Copyright 2001 Mani Srivastava
17
A Basic N-well CMOS Process
(contd.)
d. Photoresist is
stripped, leaving
SiO2/SiN sandwich
defining active
regions. Thick field
oxide is grown where
SiN is absent
e. Poly gate definition
by covering surface
with poly, and then
etching
18. Copyright 2001 Mani Srivastava
18
A Basic N-well CMOS Process
(contd.)
f. A n+ mask is used to
indicate thin-oxide and
poly areas that are to
be implanted n+. Also
called select mask.
g. More complicated
source/drain structures
are sometimes used
19. Copyright 2001 Mani Srivastava
19
A Basic N-well CMOS Process
(contd.)
h. Complement of n+
mask is used to define
p+ diffusion areas
i. Contact cuts are
defined by etching SiO2
down to surface to be
contacted
j. Metallization is
applied, and selectively
etched
20. Copyright 2001 Mani Srivastava
20
A Basic N-well CMOS Process
(contd.)
Final step: the wafer is passivated, and
openings to bonding pads are etched to allow for
wire bonding
passivation protects the silicon surface against
contaminants
21. Copyright 2001 Mani Srivastava
21
CMOS Inverter in N-well Process
22. Copyright 2001 Mani Srivastava
22
Substrate & Well Contacts
In N-well process
p-type substrate is
connected to VSS
p+ regions
well is connected to
VDD
n+ regions
Called:
well contacts
substrate contacts
23. Copyright 2001 Mani Srivastava
23
P-well Process
P-well processes were common in early days
N-well is more popular now
P-well preferred where NMOS and PMOS
characteristics need to be more balanced
transistor that resides in well tends to have inferior
characteristics as compared to transistor in native
substrate
– P-well has better PMOS than a N-well process
24. Copyright 2001 Mani Srivastava
24
Twin-Well Processes
Allow separate optimization of NMOS and PMOS
independent optimization of threshold voltage, body
effect, gain, etc.
25. Copyright 2001 Mani Srivastava
25
Silicon on Insulator
Insulating substrate (e.g. sapphire) to improve
process characteristics
Advantages
no latch-up problems
speed due to lower parasitic substrate capacitance
closer packing of NMOS and PMOS transistors
26. Copyright 2001 Mani Srivastava
26
CMOS Process Enhancements
for Better Interconnect
Process enhancements to
ease routing, especially automated routing
improve power and clock distribution
Enhancements include:
additional layers of metal (2,3, or more)
additional layers of poly (2, 3, or more)
improving existing layer of poly
– reduce sheet resistance of poly (20-40 ) by combining it
with a refractory metal (e.g. silicon & tantalum)
improving existing layer of metal
– copper instead of aluminum
27. Copyright 2001 Mani Srivastava
27
Two-level Metal Process
Normally Aluminum is used for metal layers
As vertical topology becomes more varied, the
width and spacing of conductors has to increase
to avoid conductors becoming too thin, and hence
break, at vertical topology jumps
28. Copyright 2001 Mani Srivastava
28
Two-level metal Via/Contact
Geometries
Via to connect M1 & M2
Separation between via
& contact to diff or poly
M1 must be involved in
contact to diff or poly
M1 & M2 borders
required around via
Restrictions on
placement of via
29. Copyright 2001 Mani Srivastava
29
Polysilicon/Refractory Metal
Interconnect
Goal is to allow the gate material to be used as
a moderate long-distance interconnect
