This document describes the design and simulation of a 4-bit arithmetic logic unit (ALU) circuit. It includes block diagrams and schematics of the logic gates, full adder, 4-to-1 multiplexer, 1-bit ALU, and 4-bit ALU. Simulation results demonstrate the circuit's functionality when performing operations on different input patterns, and propagation delays are reported for each component.

1. 4-Bit ALU

2. Highlights
•Introduction- How does the circuit workApproach for the designIndiv

4. Block Diagram for 4-Bit ALU

5. Design Flow

6. AND2 schematic

7. AND2 Layout & LVS Report

8. OR2 Schematic

9. OR2 Layout & LVS Report

10. XOR2 Schematic

11. XOR2 Layout & LVS

12. Full Adder Schematic

13. Full Adder Layout

14. Full Adder LVS Report

15. 4-to-1 MUX schematic

16. 4-to-1 MUX schematic (cont.)

17. 4-to-1 MUX Layout

18. 4-to-1 MUX LVS Report

19. 1-bit ALU schematic

20. 1-bit ALU Layout

21. 1-bit ALU LVS Report

22. 4-bit ALU Schematic

23. 4-bit ALU Layout

24. 4-bit ALU LVS Report

25. Test Vectors
•Walking ones for inputs on all operations (1-8)Testing for Cout and Cin (9, 10)

26. Simulation Results

27. Simulation Results

28. Simulation Results

29. Simulation Results

30. Simulation Results

31. Simulation Results

32. Simulation Results

33. Simulation Results

34. Simulation Results (Cout)

35. Simulation Results (Cin)

36. Propagation Delay for AND gate

37. Propagation Delay for OR gate

38. Propagation Delay for XOR gate

39. Propagation Delay for Full Adder

40. Propagation Delay for 4-to-1 MUX

41. elay For 4-bit ALU (when S1=S0=0 A

42. elay For 4-bit ALU ( when S1=0, S0=1

43. elay for 4-bit ALU(when S1=1, S0=0 X

44. Delay for 4-bit ALU (when S1=S0=1 A

45. Delay for 4-bit ALU (when S1=S0=1 A

46. Delay for 4-bit ALU (when S1=S0=1 A

47. ation for 4-bit ALU (when S1=S0=0 AN

48. ion For 4-bit ALU ( when S1=0, S0=1

49. ion for 4-bit ALU(when S1=1, S0=0 X

50. ation for 4-bit ALU (when S1=S0=1 Ad