low power design

1. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Topics
 Low power design.
 Pipelining.

2. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Rules for reducing power
consumption.
 Turn it off.
– Eliminates leakage current.
 Slow it down, reduce voltage.
– Performance is linear with clock frequency.
– Power is V2.
 Don’t change its inputs.
– Activity-dependent.

3. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Energy and power
 Energy = power * time.
 Energy consumption is critical for battery-
powered systems.
 Power consumption is critical for heat
dissipation limited systems.

4. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Energy and performance
 In many cases, high performance = low
energy.
– Efficiency pays off in both arenas.
 In some cases, energy can be saved by
reducing performance.
– P = 1/2 CV2
– Power goes down faster than performance.

5. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Levels of abstraction
 Physical:
– Minimize capacitance.
 Gate:
– Use low leakage gates.
 Combinational:
– Avoid twitches.
 Register-transfer:
– Avoid using units.
 Architecture:
– Slow things down, turn them off.

6. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Sources of energy consumption
 Static:
– Leakage.
 Dynamic:
– Switching activity.

7. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Physical optimizations
 Assuming equal signal probabilities, total
wire capacitance is proportional to dynamic
power consumption.
 Shorter wires -> less power consumption.
 More active nets should be shortened first.

8. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
How to reduce wire length
 Use hard macros where possible.
 Add placement constraints.
 Use design hierarchy to guide placement
search.
 Use nets with small drivers where possible.
– Don’t drive a net faster than it needs to go.

9. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Logic/circuit optimizations
 Turn off gate where possible.
– Not an option in most FPGAs, but it should be.
 Operate gate at low voltage.
– Speed decreases linearly, power decreases as
V2.

10. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Combinational optimizations
 Design network to avoid unnecessary
glitching where possible.
– Balance delays across paths.
 Can duplicate logic to reduce wire lengths.
– Does the duplicate logic use less power than the
wire?

11. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Register-transfer optimizations
 Hold inputs when a unit’s output will not be
used.
– Put register at inputs.
 Turn off units when they won’t be used for
several cycles.
– Can’t selectively turn off LEs in most FPGAs.

12. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Architectures for low power
 Two important methods:
– architecture-driven voltage scaling
– power-down modes

13. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Architecture-driven voltage
scaling
 Add extra logic to increase parallelism so
that system can run at lower rate.
 Power improvement for n parallel units over
Vref:
– Pn(n) = [1 + Ci(n)/nCref + Cx(n)/Cref](V/Vref)
Clock = 50 MHz
Clock = 25 MHz
Clock = 25 MHz

14. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Power-down modes
 CMOS doesn’t consume power when not
transitioning. Many systems can incorporate
power-down modes:
– condition the clock on power-down mode;
– add state to control for power-down mode;
– modify the control logic to ensure that power-
down/power-up don’t corrupt control state.

15. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Pipelines
 Provide higher utilization of logic:
Combinational logic
P1
P2

16. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Pipeline metrics
 Throughput: rate at which new values enter
the system.
– Initiation interval: time between successive
inputs.
 Latency: delay from input to output.

17. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Simple pipelines
 Pure pipelines have no control.
 Choose latency, throughput.
 Choose register locations with retiming.
 Overhead:
– Setup, hold times.
– Power.

18. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Complex pipelines
 Actions in pipeline depend on data or
external events.
 Actions on pipe:
– Stall values.
– Abort operation.
– Bypass values.

19. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Pipeline metrics
 Ignore register delay:
– Combinational logic delay D.
– Latency L.
– Throughput T.
 Delay through unpipelined system.
– L = D.
– T = 1/D.

20. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Adding pipeline stages
 Add a pipeline stage:
– Latency remains L = D.
– Throughput increases: T = 2/D.
 n-stage pipeline:
– Throughput increases: T = n/D.
 Clock period:
– P = D/n.

21. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Performance vs. pipeline stages
# stages
throughput
clock period

22. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Adding pipeline stages
 Must add a pipeline stage that cuts the logic.
– Cutset for PI-PO graph.
 Can use retiming to position the registers in
the logic.

23. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Cutsets

24. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Bad pipeline

25. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Pipeline utilization
 Need to fill up the pipeline.
– Later stages are unused as the pipeline fills up.
 Assume D stages of valid data, n total
stages.
– Utilization U= D / D+n.
 In steady state, utilization approaches 1.

26. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Pipelines with control
 Pipeline may do different things at different
times.
– CPU control flow.
 Must make sure that the pipeline operates
properly in all cases.

27. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Sending a control signal forward

28. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Sending a control signal backward
 Make sure control arrives at right cycle:

29. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Combining signals from multiple
cycles
 Different stages
can’t use ALU on
same cycle.

30. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Distributed pipeline control

31. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Pipeline control logic
 Ideal pipeline
needs no
significant
control:
s1
-/ALU = op

32. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Simple decisions
 Simple decision
doesn’t add
states:
s1
0 /ALU = +
1 /ALU = -

33. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Controlling a pipeline flush

34. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Product machine for pipeline flush

35. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Hardware sharing control

36. FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR
Pipeline verification
 Extensive simulation is required to exercise
the pipeline.
– State of pipeline stages interact.
 Symbolic simulation: simulate names, not
particular values.