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Vikas marka.pptx
1. DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
8-Bit ALU Design Using m-GDI Technique
Presented By:
K.Naveen(19C31A0426)
M.Vikas Kumar(19C31A0435)
M.Arun Teja(19C31A0441)
R.Laxmi Prasanna(19C31A0449)
Guided by:
Mr.P.Kiran Kumar
Associate Professor
3. ABSTRACT
In this project, the design of an 8-bit Arithmeticogic Unit (ALU) using Gate Diffusion Input (GDI)
technique is proposed. Implementing the GDI technique in designing the ALU results in low
power consumption and the number of transistors it requires is much less. Which result in
reduced chip-area and power consumption โ two of the most important parameters in digital
VLSI design. In this design, 3T XOR is used in the full adder. Moreover, a novel 1-to-8
demultiplexer circuit has been used in the design as well. A considerable number of research
papers are studied and compared various logic families and then finally designed an 8-bit ALU
which can perform 8 different operations. The design is validated using the schematic
editorDHCH 3.5 and the simulation have been carried out using Xilinx ISE 14.7
4. INTRODUCTION
To reduce the power consumption different logic design
techniques like CMOS complementaryFontSlidesArrange
QuickStyleslogic, Pseudo n MOS, Dynamic CMOS, Clocked CMOS
logic (C2 MOS), CMOS Domino logic, Cascade voltage switch logic
(CVSL), Modified Domino logic, PassTransistor Logic(PTL) have
been proposed.Although Static CMOS Logic has been the most
popular design approach for the past threedecades, many
attempts have been made to propose a better alternative to
achieve lower powerdissipation, smaller area and better
performance reported.
5. EXISTING SYSTEM
->AnALU (Arithmetic and Logical Unit) is a vital part of almost
every computing device be it microprocessors, computers,
embedded designs etc.
->The 8-bit ALU was formed by combining three 4-bit ALU's with 5
multiplexers.The design of the 8-bit ALU is based on the use of a
carry select line.The four lowest bits of the input are fed into one of
the 4 bit ALU's.
->The carry out line from this ALU is used to select the outputs
from one of the two remainingALUS. If carry out is asserted then
the ALU with carry in tied true is selected.
6. -> If carry out is not asserted then the ALU with carry in tied false is selected.The outputs of the
selectable ALUS are multiplexed together forming the upper and lower 4 bits, and carry out for the 8
Bit ALU.
7. PROPOSED SYSTEM
Modified Gate Diffusion Input is a new method for designing circuits which
reduces the power requirements considerably. Also, M- GDI results in a
reduced number of transistors, which in turn makes for a decrease in chip-
area giving an edge to the designs over conventional methods.
The basic GDI primitive cell is similar to the CMOS implementation of the
inverter circuit. But, it is capable of doing much more than that. Depending
on the inputs given to G, N and P the functionality of the circuit varies. G is
the common gate of the NMOS and PMOS. N is the source terminal of the
NMOS and P is the source terminal of the PMOS.All these acts as input
terminals.The output is collected from the common drain D.
8. -> GDI technique is area efficient technique which consumes less power with
reducing the number of transistor.
11. CONCLUSION
-> In this work a novel strategy to convert 3-valued temary input into two-valued binary output is
proposed. Proposed 3-stepTemary-to-Binary Converter (TBC) circuit involves "Trit-to-Unary
Decoder(TUD)" in Stage-I. "Complete-Unary-Decoder (CUD)" in Stage-II and "Unary-to-Binary
Converter (UBC)" in the third and final stage (Stage-III).
-> A 2:4TBC circuit has been designed and optimized based on Double Pass-transistor Logic (DPL)
and time-equalized through Coarse tuning at circuit level and fine tuning at device level to achieve
optimum delay balance at the output. Each "Trit-to-Unary Decoder (TUD)" in Stage-I consists of
two NTI. one PTI and one Binary OR-Gate. Stage-II consists of 2-input binary AND-plane whereas
stage-III is constructed with binary OR-plane.
12. REFERENCES
1] W. Alexander. "The temary computer." IET Electronics and Power, vol. 10, no. 2. pp. 36-39,
February 1964.
[2] M. Yoeli and G. Rosenfeld. "Logical design of temary switching circuits." IEEE Transactions on
Electronic Computers, vol. EC-14, no. 1. pp. 19-29. February 1965.
[3] P. C. Balla and A. Antoniou, "Low power dissipation MOS temary logic family,โ IEEE Journal of
Solid-State Circuits, vol. SC-19, no. 5, pp. 739-749, October 1984.
[4] X. W. Wu. "CMOS temary logic circuits." IEE Proceedings, vol. 137, Pt. G. no. I, pp. 21-27,
February 1990.
[5] I. Halpem and M. Yoeli, "Ternary arithmetic unit," IEE Proceedings, vol. 115, no. 10, pp. 1385-
1388, October 1968.
[6] H.S. Crafts, "Trinary to binary level conversion circuit," US Patent, US5045728A, 1991.
