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Lucent Technologies - Proprietary
Use pursuant to Company instructions
SONET Testing:
2.5G TTRN / TRCV ATE Test
Development On
Hybrid LTX FUSION HF
Laird Snowden, Jr
NETCOM High Speed Physical Layer
Test Development
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 2
BACKGROUND
• Worked on RF Wafer Probe for 1.7 GB/s GaAs Codes,
optimized Package Yield using data analysis to re-set wafer
limits and develop new tests as required.
• Developed at-speed wafer probe for Sonet 2.488 GaAs CDR
and Limiting Amp.
• Wrote RnS Wafer Test Executive for above codes.
• Developed at-speed internal RF Die Probing for FMA.
• Worked with Cascade on some preliminary Membrane Card
features during its development such as contact sense.
• Developed wafer PCM to device performance models for GaAs
wafers using Neural Networks.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 3
Considerations
• At-Speed Wafer Test.
• Known Good Die Solder Bump At-Speed Test.
• Short test time required.
• High Functional Pin Count.
• Variety of Pin Types.
• Analog, Digital and RF tests required.
• 2.488 GB/s Bit Rate.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 4
Device Test Requirements
• High pin count.
• RF VSWR test 2.488 GB/s
• Multiple Logic Levels and pin types.
– CMOS, Open Drain, CML (Current Mode Logic), LVPECL,
Analog.
• High Speed Timing tests in pico seconds.
• High speed BERT Testing 2.488 GB/s
• Low speed 32 pin digital 155 MB/s.
• Jitter testing (less than 1 pS capability)
• FEC rate 15/14 (* Bit Rate).
• Analog leakage tests.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 5
TRCV012G5 Pin Out
• Demux
• 34 155 GB/s LVPECL Outputs.
• 2 155 GHz LVPECL Outputs.
• 2 155 GHz LVPECL Inputs.
• 2 2.488 GB/s CML Outputs.
• 2 2.488 GHz CML Outputs.
• 2 2.488 GB/s Analog Inputs.
• 10 CMOS Inputs.
• 9 Analog Inputs.
• 2 Analog Outputs.
• 2 Open Drain Outputs.
• 2 2.488 GB/s CML Inputs.
• 16 VCCD Power Pins.
• 3 VCCLA Power Pins.
• 4 VCCA Power Pins.
• 24 GND Pins.
• CML= Current Mode Logic.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 6
TTRN012G5 Mux Pin Out
• MUX
• 4 CML 2.488 GB/s Output
Pins.
• 2 CML 2.488 GHz Output
Pins.
• 2 CML Input Pins.
• 4 Analog Input Pins.
• 2 Analog Output Pins.
• 9 CMOS Input Pins.
• 2 CMOS Output Pins.
• 36 LVPECL Input Pins.
• 4 LVPECL Output Pins.
• 5 VCCA Power Pins.
• 21 VCCD Power Pins.
• 24 Gnd Pins.
• CML= Current Mode Logic.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 7
DIE TEMPERATURE CONTROL
• One additional constraint is the need to test this part
at 125 degrees Celsius die temperature. This is
verified by measuring an ESD diode Voltage drop with
100 uA current applied.
• Coefficients for temperature conversion developed by
profiling the diode without power applied except for
forward bias. Self heating is minimized by reading the
Voltage drop immediately after applying bias.
• Air temperature over package is set for correct die
temperature.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 8
Optimum Test Platform
• Neither type of platform in current configurations met
device test requirements.
• REQUIREMENTS:
– Analog Test
– Digital Test
– RF Test
– Support for high throughput:
– Short Test Time.
– Dockable to Handler or Prober.
– Distributed knowledge of hardware.
– Distributed knowledge of software.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 9
Rack and Stack Considerations
And Constraints
• + High Speed RF path can be managed.
• + Custom test routines easily programmed.
• + Flexible, can integrate any GPIB bus equipment.
• + Hardware changes can be implemented quickly.
• - No Test Head for docking to Prober or Handler
available.
• - Large digital pin count difficult to manage.
• - Verification must be developed for each code.
• - Specialized knowledge required for troubleshooting.
• - Test Time not optimal.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 10
ATE Considerations and
Constraints
• + Standard Platform, knowledge for troubleshooting more
distributed.
• + Optimized for high speed testing
– Known state hardware pre-loaded to minimize setup time
after the first test is run.
– Parallel Measurements.
– Driver cards close to DUT to minimize settling time.
• - Current configuration unable to generate 2.488 GB/s Patterns.
• - Most ATE Testers do not integrate analog, Digital and RF. RF
should be Sub-Millimeter Microwave range (18 GHz).
• - Fast Digital Pins needed (155 MB/s for 2.488 for low speed
side and 622 MB/s for 10 GB/s low speed side).
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 11
Rack and Stack Solution
• We first proposed developing a hybrid Rack and
Stack solution built around a low cost ATE platform.
– ATE provides
• Test Head
• DC pin parametric Measurements.
• Generic programming environment.
– Hybridization:
• Add Generic RF interface to test head.
• Add RF Rack and Stack Equipment.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 12
ATE REQUIREMENTS FOR
HYBRIDIZATION
• 80/20RULE:
• ATE tester should have sufficient pin card bandwidth to carry at
least 80 % of the test load.
• ATE tester must have sufficient bandwidth in the RF path to the
test head to provide a path for supplemental RF Equipment
(less than 20% of test load).
• ATE must have an accessible and stable 10 MHz Analog
Master clock to synchronize the OEM RF Test Equipment to the
ATE tester pin cards.
• ATE must have an RF Configuration module to provide
customization for different families of codes.
• ATE must have sufficient Digital and Analog pin count.
• ATE must provide sufficient measurement speed to justify cost.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 13
LTX FUSION HF/HYBRID
• LTX Fusion HF available with Analog, Digital and RF test capability.
– RF Path provides 16 channels (20 GHz) from the test head to the
RF configuration module and to the 3GHz ATE RF Measurement
section.
– High Speed Digital Pins (2.488 GB/s) in development.
– Standard Current Digital Pins lacked sufficient speed for high
speed side of Mux/Demux, but sufficient for low speed side.
– LTX accepted proposal to build an OEM/ATE Hybrid of the Fusion
HF, built on RF interface.
• Integrated 3 GHz OEM Bit Error Rate Tester added to the Fusion
HF for the 2.488 GB/s test vectors and clock.
• 2.488 GB/s High Speed Digital Pin Cards (HSDC) under
development at LTX.
• LTX developed phase noise technique jitter measurement to extend
jitter measurement capability.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 14
TRCV012G5 Test List
• SUMMARY
• Continuity
• Leakage
• Current
• Functional
• Logic Levels Search
• Operational Tests
• Data to clock delay
• VSWR
• Generated Jitter
• AST Phase shift
• Ring Osc test
• Output parametrics
• Jitter Transfer
• Jitter Generation
• Limiting Amp sensetivity
• Limiting Amp analog loss of signal
• Jitter Tolerance
• Bit Error rate
• Number of tests: 172
• 3 Vcc levels
• Total Tests: 516
• Test time: 70 seconds
(not optimized)
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 15
TTRN012G5 Test List
• SUMMARY
• Continuity
• Leakage
• Current
• Functional
• Logic Levels Search
• Operational Tests
• Data Setup and Hold
• Generated Jitter
• Ring Osc test
• Output parametrics
• Jitter Generation
• Limiting Amp sensetivity
• Limiting Amp analog loss of signal
• Jitter Tolerance
• Bit Error rate
• .
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 16
Test Head Installation, Covers off.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 17
10 MHz Reference
• OEM RF Equipment is
synchronized to the ATE
Tester by connecting
the ATE Analog Master
Clock to the 10 MHz
Reference input on the
OEM Pattern
Generator.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 18
LTX Fusion HF with Manual
Contactor and OEM Rack.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 19
Prober Dock
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 20
17 inch DUT Board, Top View
Card is 17 inches
to provide space for
RF Switches and
components
around the periphery.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 21
DUT Board Bottom View, RF
Switches.
o 20 GHz RF Connectors(16) to RF-
SCM.
o RF Switches (18 GHz).
o 3 GHz Pogo pins (1000) for Digital
and Analog tester cards.
o DC Pogo pins to RF-SCM.
Note:
Number of RF pins for OEM Equipment
could be expanded.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 22
Test Head RF-SCM, RF
Distribution Layer)
Top Cover removed.
Showing:
o RF Switches.
o RF Bias Tee’s.
o RF Splitters.
o HS Digital and
Analog Pogo Pins.
o RF Connectors
Around Perimeter.
o RF-SCM Pogo pins
(outer pogo ring).
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 23
RF-SCM Removed
High Speed Digital and
Analog Pogo Pins
RF Brick OSSP 20 GHz quad
connectors
RF OEM OSSP 20 GHz quad
connectors (lower right
corner and upper right).
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 24
RF OEM Interface Panel
RF OEM interface
at rear of test head
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 25
RF OEM Rack
RF Rack Connected to
Test Head.
Future:
Quick Connect
Interface
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 26
Aries RF Socket
• Fingers extend over 50 ohm
microstrip traces on board.
• Device is inserted, DUT pins
are pushed against socket
fingers which are in turn
pushed down over the 50
ohm fingers on the DUT
board.
• Parasitic pin inductance is
limited to the thickness of the
fingers.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 27
Tronix Socket
• DUT pin are pressed against
a polyamide Membrane,
which has conductive
features patterned on the
membrane. Material has
diamond dust impregnated in
it. Contact is then pressed
against the 50 ohm DUT
board microstrip line.
• Specified at 1 million
insertions.
• Bandwidth can be increased
by reducing membrane
thickness at the cost of life .
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 28
DUT Board Contactor Interface
• 50 Ohm fingers on
DUT board.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 29
Membrane
• RF Testing requires high bandwidth
path.
– 3rd Harmonic clock is 7.5 GHz.
– 5th Harmonic clock is 12.5
GHz.
• Circuit requires precision inductor
with less than 500 femto farads of
parasitic capacitance. This will be
implemented as a spiral inductor on
the polyamide membrane.
• Probe planarity and registration
does not degrade over time and is
not a variable. Good for higher pin
count codes.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 30
Membrane
• Top of Membrane card.
• Core is replaced when needed.
• This is an early card from the
2.488 GB/s GaAs CDR probe
station.
• A 17 inch RF probe card is under
development at Cascade. This
provides room for RF switches
and components around the
periphery.
• Wentworth Labs can provide a 17
inch probe card with a needle
probe ring or Cobra ring for
lower speed testing capability
with the new probe card format.
• TSK prober being modified for the
17 inch docking mechanisim.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 31
Picture of Membrane RF Launch
• RF interconnect bump to
connect core to probe card.
• Bump to connect to die.
• Semi-Rigid to RF finger on
Probe card.
Ground,
signal
ground
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 32
Eye Diargram 2.488 GB/s
Membrane Probe test.
• 2.488 GB/s eye
diagram from GaAs
CDR wafer probe test
set.
• Cascade Membrane Probe
Card.
• Anritsu Bert.
• Tektonics Sampling Scope.
• BICMOS Membrane card being
fabricated.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 33
Membrane Contact Sensor
• Contact sensor
improves contact
consistency to assure
good RF contact.
• Membrane is spring loaded
and can tolerate more over
travel than needle probe
cards.
• Membrane Bumps are
robust and can tolerate
some degree of abuse.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 34
Membrane
• Air jets have been
incorporated into the
Membrane to clean the
wafer before probing.
• It is important to remove
any particles from the
wafer before touchdown
as they can become
lodged in the membrane.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 35
Membrane Air Cleaning Control
• Controller for Membrane Air
jets.
• The cleaning cycle moves in a
serpentine down the wafer. Air
is only applied as the wafer
moves in one direction to
minimize blow-back.
• Cleaning pressure for GaAs
wafers is set to 70 PSI.
• A sub micron filter is included
in the air stream.
• Air is turned off during probe to
prevent the risk of ESD build
up on the membrane.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 36
Reduction of Contact Resistance for
Probing Aluminum Pads
• During probe, Aluminum from
pads deposits on probe.
• Over time, an oxide layer forms.
• As more wafers are probed, more
aluminum/oxide layers form.
• Probe resistance rises.
• To maintain low contact
resistance, circular scrub on
ceramic substrate needed during
cleaning cycle.
• Closed loop cleaning prevents
excessive probe wear.
• This method used to eliminate heavy
yield loss due to offsets on a current to
voltage PLL control circuit of the
Aluminum pad version of the Si CDR PLL
control die for the GaAs CDR.
• Probe resistances rises as
oxide layers form.
Aluminum Oxide
Aluminum from Pads
Tungsten Rhenium
Probe Tip.
Closed loop cleaning:
1 Measure probe resistance.
2 Clean when reach high threshold.
3 Clean until probe resistance reaches nominal level.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 37
Internal RF Die Probe Aperture
Laser/Probe Station
• Three color aperture laser
for trace cutting, on either
GaAs or Si and SiN cap
removal.
• Provision for rectangular
probe card holder.
• Internal DC Probe:
– Probes down to sub
micron tip size.
• Internal RF Probe:
– Probes to 10 Micron tip
size, up to 11 GHz,
special probe for 60
GHz .
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 38
Internal Die Probe on Motorized
Manipulator
• 3 GHz Acitve. No ground
(pictured).
• 11 GHz Passive with ground.
• 60 GHz Passive with ground.
• Use Bias Tee to separate RF
and DC components.
• Passive Probes in different
configurations:
• 50 Ohm, unterminated
• 50 Ohm terminated
• 1:1, 1:2, 1:10, 1:20
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 39
FURTHER WORK• 10 GHz development as required:
– Explore 12 GHz OEM BERT and HSDC Digital Cards.
– Verify Jitter capability (phase noise).
• 2.488 GB/s BERT using jitter analyzer to estimate 14 sigma performance by
separating Random and Deterministc Jitter Components.
• Extract Pr pattern vectors from OEM Bert and insert into ATE pin card
memory.
• Explore Cascade package DUT Board to improve RF launch.
• Deploy Membrane Die Probe to enhance package yield.
• Deploy Membrane Solder Bump Array probe for Known Good Die Testing.
• Develop Closed Loop Membrane Probe cleaning cycle to maintain < 200
milli-ohm contact resistance (maintain Q of VCO tank Inductor). Open loop
currently used in RnS needle probe of Si CDR PLL die which requires very
low contact resistance. This uses a circular scrub on a ceramic sub-chuck
cleaning substrate.
• Explore Optical OEM Measurement Instrument Hybridization.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 40
FUTURE WORK
• 40 GB/s and greater testing:
• Explore need to add optical interface to Membrane probe card.
• Explore recombinant photo emission testing.
• Explore Membrane test with existing technology (Coplanar
Waveguide Structures).
• Define RnS vs ATE/Hybrid Test platforms and techniques for
next generation testing.
• Develop Internal die probe techniques for higher bandwidth
codes as required for FMA.
L. Snowden 4/17/00
Lucent Technologies - Proprietary
Use pursuant to Company instructions 41
Acknowledgments
• LUCENT:
• Hybrid ATE: PROJECT LEAD Laird Snowden
• Test Suite definition Laird Snowden
• Test (Cadence and enVision) and NPI Laird Snowden
• Project Approval C level : Paul Tracy
• HSPL Assembly and Test Manager: Pat Reppert.
• Project Manager: Don Fister
• LTX
• Vice President, LTX: Dave Fessler
• Lucent Director of Operations: John LaFlamme
• Market Manager, Netcom: Ken Lanier
• Senior Manager, Fusion Applications Development: Derrick Dupre
• Digital & enVision Software Development: Denny Repsher
• Cadence Software Development: Brent Schusheim
• LTX Field Engineer: Steve Aikens

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Icd lrs may2_00_ate_hyb.

  • 1. Lucent Technologies - Proprietary Use pursuant to Company instructions SONET Testing: 2.5G TTRN / TRCV ATE Test Development On Hybrid LTX FUSION HF Laird Snowden, Jr NETCOM High Speed Physical Layer Test Development
  • 2. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 2 BACKGROUND • Worked on RF Wafer Probe for 1.7 GB/s GaAs Codes, optimized Package Yield using data analysis to re-set wafer limits and develop new tests as required. • Developed at-speed wafer probe for Sonet 2.488 GaAs CDR and Limiting Amp. • Wrote RnS Wafer Test Executive for above codes. • Developed at-speed internal RF Die Probing for FMA. • Worked with Cascade on some preliminary Membrane Card features during its development such as contact sense. • Developed wafer PCM to device performance models for GaAs wafers using Neural Networks.
  • 3. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 3 Considerations • At-Speed Wafer Test. • Known Good Die Solder Bump At-Speed Test. • Short test time required. • High Functional Pin Count. • Variety of Pin Types. • Analog, Digital and RF tests required. • 2.488 GB/s Bit Rate.
  • 4. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 4 Device Test Requirements • High pin count. • RF VSWR test 2.488 GB/s • Multiple Logic Levels and pin types. – CMOS, Open Drain, CML (Current Mode Logic), LVPECL, Analog. • High Speed Timing tests in pico seconds. • High speed BERT Testing 2.488 GB/s • Low speed 32 pin digital 155 MB/s. • Jitter testing (less than 1 pS capability) • FEC rate 15/14 (* Bit Rate). • Analog leakage tests.
  • 5. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 5 TRCV012G5 Pin Out • Demux • 34 155 GB/s LVPECL Outputs. • 2 155 GHz LVPECL Outputs. • 2 155 GHz LVPECL Inputs. • 2 2.488 GB/s CML Outputs. • 2 2.488 GHz CML Outputs. • 2 2.488 GB/s Analog Inputs. • 10 CMOS Inputs. • 9 Analog Inputs. • 2 Analog Outputs. • 2 Open Drain Outputs. • 2 2.488 GB/s CML Inputs. • 16 VCCD Power Pins. • 3 VCCLA Power Pins. • 4 VCCA Power Pins. • 24 GND Pins. • CML= Current Mode Logic.
  • 6. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 6 TTRN012G5 Mux Pin Out • MUX • 4 CML 2.488 GB/s Output Pins. • 2 CML 2.488 GHz Output Pins. • 2 CML Input Pins. • 4 Analog Input Pins. • 2 Analog Output Pins. • 9 CMOS Input Pins. • 2 CMOS Output Pins. • 36 LVPECL Input Pins. • 4 LVPECL Output Pins. • 5 VCCA Power Pins. • 21 VCCD Power Pins. • 24 Gnd Pins. • CML= Current Mode Logic.
  • 7. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 7 DIE TEMPERATURE CONTROL • One additional constraint is the need to test this part at 125 degrees Celsius die temperature. This is verified by measuring an ESD diode Voltage drop with 100 uA current applied. • Coefficients for temperature conversion developed by profiling the diode without power applied except for forward bias. Self heating is minimized by reading the Voltage drop immediately after applying bias. • Air temperature over package is set for correct die temperature.
  • 8. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 8 Optimum Test Platform • Neither type of platform in current configurations met device test requirements. • REQUIREMENTS: – Analog Test – Digital Test – RF Test – Support for high throughput: – Short Test Time. – Dockable to Handler or Prober. – Distributed knowledge of hardware. – Distributed knowledge of software.
  • 9. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 9 Rack and Stack Considerations And Constraints • + High Speed RF path can be managed. • + Custom test routines easily programmed. • + Flexible, can integrate any GPIB bus equipment. • + Hardware changes can be implemented quickly. • - No Test Head for docking to Prober or Handler available. • - Large digital pin count difficult to manage. • - Verification must be developed for each code. • - Specialized knowledge required for troubleshooting. • - Test Time not optimal.
  • 10. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 10 ATE Considerations and Constraints • + Standard Platform, knowledge for troubleshooting more distributed. • + Optimized for high speed testing – Known state hardware pre-loaded to minimize setup time after the first test is run. – Parallel Measurements. – Driver cards close to DUT to minimize settling time. • - Current configuration unable to generate 2.488 GB/s Patterns. • - Most ATE Testers do not integrate analog, Digital and RF. RF should be Sub-Millimeter Microwave range (18 GHz). • - Fast Digital Pins needed (155 MB/s for 2.488 for low speed side and 622 MB/s for 10 GB/s low speed side).
  • 11. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 11 Rack and Stack Solution • We first proposed developing a hybrid Rack and Stack solution built around a low cost ATE platform. – ATE provides • Test Head • DC pin parametric Measurements. • Generic programming environment. – Hybridization: • Add Generic RF interface to test head. • Add RF Rack and Stack Equipment.
  • 12. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 12 ATE REQUIREMENTS FOR HYBRIDIZATION • 80/20RULE: • ATE tester should have sufficient pin card bandwidth to carry at least 80 % of the test load. • ATE tester must have sufficient bandwidth in the RF path to the test head to provide a path for supplemental RF Equipment (less than 20% of test load). • ATE must have an accessible and stable 10 MHz Analog Master clock to synchronize the OEM RF Test Equipment to the ATE tester pin cards. • ATE must have an RF Configuration module to provide customization for different families of codes. • ATE must have sufficient Digital and Analog pin count. • ATE must provide sufficient measurement speed to justify cost.
  • 13. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 13 LTX FUSION HF/HYBRID • LTX Fusion HF available with Analog, Digital and RF test capability. – RF Path provides 16 channels (20 GHz) from the test head to the RF configuration module and to the 3GHz ATE RF Measurement section. – High Speed Digital Pins (2.488 GB/s) in development. – Standard Current Digital Pins lacked sufficient speed for high speed side of Mux/Demux, but sufficient for low speed side. – LTX accepted proposal to build an OEM/ATE Hybrid of the Fusion HF, built on RF interface. • Integrated 3 GHz OEM Bit Error Rate Tester added to the Fusion HF for the 2.488 GB/s test vectors and clock. • 2.488 GB/s High Speed Digital Pin Cards (HSDC) under development at LTX. • LTX developed phase noise technique jitter measurement to extend jitter measurement capability.
  • 14. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 14 TRCV012G5 Test List • SUMMARY • Continuity • Leakage • Current • Functional • Logic Levels Search • Operational Tests • Data to clock delay • VSWR • Generated Jitter • AST Phase shift • Ring Osc test • Output parametrics • Jitter Transfer • Jitter Generation • Limiting Amp sensetivity • Limiting Amp analog loss of signal • Jitter Tolerance • Bit Error rate • Number of tests: 172 • 3 Vcc levels • Total Tests: 516 • Test time: 70 seconds (not optimized)
  • 15. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 15 TTRN012G5 Test List • SUMMARY • Continuity • Leakage • Current • Functional • Logic Levels Search • Operational Tests • Data Setup and Hold • Generated Jitter • Ring Osc test • Output parametrics • Jitter Generation • Limiting Amp sensetivity • Limiting Amp analog loss of signal • Jitter Tolerance • Bit Error rate • .
  • 16. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 16 Test Head Installation, Covers off.
  • 17. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 17 10 MHz Reference • OEM RF Equipment is synchronized to the ATE Tester by connecting the ATE Analog Master Clock to the 10 MHz Reference input on the OEM Pattern Generator.
  • 18. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 18 LTX Fusion HF with Manual Contactor and OEM Rack.
  • 19. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 19 Prober Dock
  • 20. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 20 17 inch DUT Board, Top View Card is 17 inches to provide space for RF Switches and components around the periphery.
  • 21. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 21 DUT Board Bottom View, RF Switches. o 20 GHz RF Connectors(16) to RF- SCM. o RF Switches (18 GHz). o 3 GHz Pogo pins (1000) for Digital and Analog tester cards. o DC Pogo pins to RF-SCM. Note: Number of RF pins for OEM Equipment could be expanded.
  • 22. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 22 Test Head RF-SCM, RF Distribution Layer) Top Cover removed. Showing: o RF Switches. o RF Bias Tee’s. o RF Splitters. o HS Digital and Analog Pogo Pins. o RF Connectors Around Perimeter. o RF-SCM Pogo pins (outer pogo ring).
  • 23. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 23 RF-SCM Removed High Speed Digital and Analog Pogo Pins RF Brick OSSP 20 GHz quad connectors RF OEM OSSP 20 GHz quad connectors (lower right corner and upper right).
  • 24. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 24 RF OEM Interface Panel RF OEM interface at rear of test head
  • 25. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 25 RF OEM Rack RF Rack Connected to Test Head. Future: Quick Connect Interface
  • 26. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 26 Aries RF Socket • Fingers extend over 50 ohm microstrip traces on board. • Device is inserted, DUT pins are pushed against socket fingers which are in turn pushed down over the 50 ohm fingers on the DUT board. • Parasitic pin inductance is limited to the thickness of the fingers.
  • 27. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 27 Tronix Socket • DUT pin are pressed against a polyamide Membrane, which has conductive features patterned on the membrane. Material has diamond dust impregnated in it. Contact is then pressed against the 50 ohm DUT board microstrip line. • Specified at 1 million insertions. • Bandwidth can be increased by reducing membrane thickness at the cost of life .
  • 28. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 28 DUT Board Contactor Interface • 50 Ohm fingers on DUT board.
  • 29. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 29 Membrane • RF Testing requires high bandwidth path. – 3rd Harmonic clock is 7.5 GHz. – 5th Harmonic clock is 12.5 GHz. • Circuit requires precision inductor with less than 500 femto farads of parasitic capacitance. This will be implemented as a spiral inductor on the polyamide membrane. • Probe planarity and registration does not degrade over time and is not a variable. Good for higher pin count codes.
  • 30. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 30 Membrane • Top of Membrane card. • Core is replaced when needed. • This is an early card from the 2.488 GB/s GaAs CDR probe station. • A 17 inch RF probe card is under development at Cascade. This provides room for RF switches and components around the periphery. • Wentworth Labs can provide a 17 inch probe card with a needle probe ring or Cobra ring for lower speed testing capability with the new probe card format. • TSK prober being modified for the 17 inch docking mechanisim.
  • 31. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 31 Picture of Membrane RF Launch • RF interconnect bump to connect core to probe card. • Bump to connect to die. • Semi-Rigid to RF finger on Probe card. Ground, signal ground
  • 32. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 32 Eye Diargram 2.488 GB/s Membrane Probe test. • 2.488 GB/s eye diagram from GaAs CDR wafer probe test set. • Cascade Membrane Probe Card. • Anritsu Bert. • Tektonics Sampling Scope. • BICMOS Membrane card being fabricated.
  • 33. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 33 Membrane Contact Sensor • Contact sensor improves contact consistency to assure good RF contact. • Membrane is spring loaded and can tolerate more over travel than needle probe cards. • Membrane Bumps are robust and can tolerate some degree of abuse.
  • 34. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 34 Membrane • Air jets have been incorporated into the Membrane to clean the wafer before probing. • It is important to remove any particles from the wafer before touchdown as they can become lodged in the membrane.
  • 35. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 35 Membrane Air Cleaning Control • Controller for Membrane Air jets. • The cleaning cycle moves in a serpentine down the wafer. Air is only applied as the wafer moves in one direction to minimize blow-back. • Cleaning pressure for GaAs wafers is set to 70 PSI. • A sub micron filter is included in the air stream. • Air is turned off during probe to prevent the risk of ESD build up on the membrane.
  • 36. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 36 Reduction of Contact Resistance for Probing Aluminum Pads • During probe, Aluminum from pads deposits on probe. • Over time, an oxide layer forms. • As more wafers are probed, more aluminum/oxide layers form. • Probe resistance rises. • To maintain low contact resistance, circular scrub on ceramic substrate needed during cleaning cycle. • Closed loop cleaning prevents excessive probe wear. • This method used to eliminate heavy yield loss due to offsets on a current to voltage PLL control circuit of the Aluminum pad version of the Si CDR PLL control die for the GaAs CDR. • Probe resistances rises as oxide layers form. Aluminum Oxide Aluminum from Pads Tungsten Rhenium Probe Tip. Closed loop cleaning: 1 Measure probe resistance. 2 Clean when reach high threshold. 3 Clean until probe resistance reaches nominal level.
  • 37. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 37 Internal RF Die Probe Aperture Laser/Probe Station • Three color aperture laser for trace cutting, on either GaAs or Si and SiN cap removal. • Provision for rectangular probe card holder. • Internal DC Probe: – Probes down to sub micron tip size. • Internal RF Probe: – Probes to 10 Micron tip size, up to 11 GHz, special probe for 60 GHz .
  • 38. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 38 Internal Die Probe on Motorized Manipulator • 3 GHz Acitve. No ground (pictured). • 11 GHz Passive with ground. • 60 GHz Passive with ground. • Use Bias Tee to separate RF and DC components. • Passive Probes in different configurations: • 50 Ohm, unterminated • 50 Ohm terminated • 1:1, 1:2, 1:10, 1:20
  • 39. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 39 FURTHER WORK• 10 GHz development as required: – Explore 12 GHz OEM BERT and HSDC Digital Cards. – Verify Jitter capability (phase noise). • 2.488 GB/s BERT using jitter analyzer to estimate 14 sigma performance by separating Random and Deterministc Jitter Components. • Extract Pr pattern vectors from OEM Bert and insert into ATE pin card memory. • Explore Cascade package DUT Board to improve RF launch. • Deploy Membrane Die Probe to enhance package yield. • Deploy Membrane Solder Bump Array probe for Known Good Die Testing. • Develop Closed Loop Membrane Probe cleaning cycle to maintain < 200 milli-ohm contact resistance (maintain Q of VCO tank Inductor). Open loop currently used in RnS needle probe of Si CDR PLL die which requires very low contact resistance. This uses a circular scrub on a ceramic sub-chuck cleaning substrate. • Explore Optical OEM Measurement Instrument Hybridization.
  • 40. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 40 FUTURE WORK • 40 GB/s and greater testing: • Explore need to add optical interface to Membrane probe card. • Explore recombinant photo emission testing. • Explore Membrane test with existing technology (Coplanar Waveguide Structures). • Define RnS vs ATE/Hybrid Test platforms and techniques for next generation testing. • Develop Internal die probe techniques for higher bandwidth codes as required for FMA.
  • 41. L. Snowden 4/17/00 Lucent Technologies - Proprietary Use pursuant to Company instructions 41 Acknowledgments • LUCENT: • Hybrid ATE: PROJECT LEAD Laird Snowden • Test Suite definition Laird Snowden • Test (Cadence and enVision) and NPI Laird Snowden • Project Approval C level : Paul Tracy • HSPL Assembly and Test Manager: Pat Reppert. • Project Manager: Don Fister • LTX • Vice President, LTX: Dave Fessler • Lucent Director of Operations: John LaFlamme • Market Manager, Netcom: Ken Lanier • Senior Manager, Fusion Applications Development: Derrick Dupre • Digital & enVision Software Development: Denny Repsher • Cadence Software Development: Brent Schusheim • LTX Field Engineer: Steve Aikens

Editor's Notes

  1. Hw changes, not generic, do not have to go thru committee to maintain generic compatability.