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Fast 8-transistor XOR-XNOR circuit

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I
ILA SHARMA
1 of 15
Proposed circuit for fast XOR-XNOR operations Presented by: Ila Sharma(102001) Harsh Magotra (102012)
Introduction to our Idea Considering the earlier designs for XOR-XNOR CIRCUIT, we are introducing an idea to make the circuit more fast, noise immune, low voltage consuming…… so we have come with a circuit having less no. of CMOS and posses all the above said features.
What is XOR GATE?
What is XNOR gate?
XOR Circuit VDD a b a b XOR gate using CMOS
XNOR Circuit VDD b a a b XNOR using CMOS
Primitive XOR-XNOR CIRCUIT ,[object Object]
Have 10 transistors
Consume more power
More time delay
Skewed output,[object Object]
Individual units of proposed XOR-XNOR circuit
Comparison between the two Earlier circuit Proposed circuit XOR Circuit VDD a b a b
XNOR Circuit VDD b a a b Earlier circuit Proposed circuit
Design metrics How to evaluate the performance of the circuit??? Cost Speed Power dissipation Delays Noise tolerance

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Fast 8-transistor XOR-XNOR circuit

  • 1. Proposed circuit for fast XOR-XNOR operations Presented by: Ila Sharma(102001) Harsh Magotra (102012)
  • 2. Introduction to our Idea Considering the earlier designs for XOR-XNOR CIRCUIT, we are introducing an idea to make the circuit more fast, noise immune, low voltage consuming…… so we have come with a circuit having less no. of CMOS and posses all the above said features.
  • 3. What is XOR GATE?
  • 4. What is XNOR gate?
  • 5. XOR Circuit VDD a b a b XOR gate using CMOS
  • 6. XNOR Circuit VDD b a a b XNOR using CMOS
  • 7.
  • 11.
  • 12. Individual units of proposed XOR-XNOR circuit
  • 13. Comparison between the two Earlier circuit Proposed circuit XOR Circuit VDD a b a b
  • 14. XNOR Circuit VDD b a a b Earlier circuit Proposed circuit
  • 15. Design metrics How to evaluate the performance of the circuit??? Cost Speed Power dissipation Delays Noise tolerance
  • 16. Noise tolerance we use the noise immunity curves, NIC to measure the noise-tolerance of XOR-XNOR circuits. The noise immunity curve ,NIC of a digital gate is a locus of points (Tn, Vn) for which the gate just makes a logic error. The higher the NIC of a gate, the less susceptible is the gate to noise.
  • 17. conclusion A new XOR-XNOR circuit implementation has been proposed and it seems that our proposal may be particularly suited for low voltage requirements. From our point of view the most important output of the described proposal is emerging hope that proposed circuit would find use in fast arithmetic operations and will be more noise immune.