Introduction to FPGA,VHDL

1. Introduction To VHDL
Prepared by :
Eng .Amr Ez-Eldin Rashed
Lecturer Assistan
Misr engineering and technology
Amr_rashed2@hotmail.com
Tel:0106539901
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2. References VHDL programming by examples” Douglas L. Perry” VHDL starter guide” Sudhakar Yalamanchili” VHDL programming logic Circuit design with VHDL “Volnei A.pedroni” RTL Hardware Design Using VHDL. PONG P. CHU Digital fundamentals using VHDL”FLOYED” DSP with FPGA “U. Meyer” FPGA implementation of neural network Digital implementation of ANN from VHDL description to FPGA implementation ”www.springerlink.com”
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3. 3
Cont.
Architecture of FPGA and CPLDs :a tutorial .
VHDL cookbook .
The design warrior’s guide to FPGA’s
Web sites:
www.opencores.com.(free Ips)
www.mentorgraphics .com
 www.altera.com
www.xilinx.com
www.mathworks.com
WWW.VHDL-online.de/tutorial

4. Microcontroller
(sometimes abbreviated μC, uC or MCU) is a small computer on A microcontroller a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. Program memory in the form of NOR flash or OTP ROM is also often included on chip, as well as a typically small amount of RAM. Microcontrollers are designed for embedded applications, in contrast to the microprocessors used in personal computers or other general purpose applications.
used in automatically controlled products and devices, such as automobile engine control systems, implantable medical devices, remote controls, office machines, appliances, power tools, and toys. By reducing the size and cost compared to a design that uses a separate microprocessor, memory, and input/output devices, microcontrollers make it economical to digitally control even more devices and processes. Mixed signal microcontrollers are common, integrating analog components needed to control non-digital electronic systems.
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5. Microcontroller
A micro-controller is a single integrated circuit, commonly with the following features:
central processing unit - ranging from small and simple 4-bit processors to complex 32- or 64-bit processors
discrete input and output bits, allowing control or detection of the logic state of an individual package pin
serial input/output such as serial ports (UARTs)
other serial communications interfaces like I²C, Serial Peripheral Interface and Controller Area Network for system interconnect
peripherals such as timers, event counters, PWM generators, and watchdog
volatile memory (RAM) for data storage
ROM, EPROM, EEPROM or Flash memory for program and operating parameter storage
clock generator - often an oscillator for a quartz timing crystal, resonator or RC circuit
many include analog-to-digital converters
in-circuit programming and debugging support
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8720 F18 PICmicrocontroller in an package TQFPpin -80

6. Vendors , programming languages
Microchip(PIC 16,18,..)
Intel,
Atmel,
Motorola.
Programming languages:
Assembly
Basic
C
Fortran ,java
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7. DSP
A digital signal processor (DSP) is a specialized microprocessor with an optimized architecture for the fast operational needs of digital signal processing.
Hardware features visible through DSP instruction sets commonly include:
Hardware modulo addressing, allowing circular buffers to be implemented without having to constantly test for wrapping.
A memory architecture designed for streaming data, using DMA extensively and expecting code to be written to know about cache hierarchies and the associated delays.
Driving multiple arithmetic units may require memory architectures to support several accesses per instruction cycle
Separate program and data memories (Harvard architecture), and sometimes concurrent access on multiple data busses
Special SIMD (single instruction, multiple data) operations
Some processors use VLIW techniques so each instruction drives multiple arithmetic units in parallel
Special arithmetic operations, such as fast multiply-accumulates (MACs). Many fundamental DSP algorithms, such as FIR filters or the Fast Fourier transform (FFT) depend heavily on multiply-accumulate performance.
Bit-reversed addressing, a special addressing mode useful for calculating FFTs
Special loop controls, such as architectural support for executing a few instruction words in a very tight loop without overhead for instruction fetches or exit testing
Deliberate exclusion of a memory management unit. DSPs frequently use multi-tasking operating systems, but have no support for virtual memory or memory protection. Operating systems that use virtual memory require more time for context switching among processes, which increases latency
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8. PLC
A programmable logic controller (PLC) or programmable controller is a digital computer used for automation of electromechanical processes, such as control of machinery on factory assembly lines, amusement rides, or lighting fixtures. PLCs are used in many industries and machines. Unlike general-purpose computers, the PLC is designed for multiple inputs and output arrangements, extended temperature ranges, immunity to electrical noise, and resistance to vibration and impact. Programs to control machine operation are typically stored in battery-backed or non-volatile memory. A PLC is an example of a real time system since output results must be produced in response to input conditions within a bounded time, otherwise unintended operation will result.
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9. Vendors , programming languages
Vendors:
1-LG
2-SIEMENS
3-PEP
Languages:
1- FBD (Function block diagram),
2- LD (Ladder diagram),
3- ST (Structured text, similar to the Pascal programming language),
4-IL (Instruction list, similar to assembly language) and SFC (Sequential function chart).
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10. 10
Definitions of Relevant Terminology
Field-Programmable Device (FPD) — a general term that refers to any type of integrated circuit used for implementing digital hardware
Can be configured by end user or “in system”
Another name for FPD is programmable logic devices (PLD) .

11. Programmable Logic Devices
Programmable logic device(PLD) is an IC that contains large no. of gates, flip- flops etc. , can be configured or programmed by the user .
PLDs are typically build with an array of AND gates and an array of OR gates.
11
AND Array
OR Array
input
output

12. General Structure of PLDs
Buffer/inverter
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13. Programmable Logic Devices
Types of PLDs:-
•Programmable read only memory (PROM)
•Programmable logic array (PLA)
•Programmable array logic (PAL)
•Complex programmable logic device (CPLD)
•Field programmable gate array (FPGA)
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14. Programmable Logic Devices
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GAL: gate array logic

15. 15
PLA — a Programmable Logic Array (PLA) is a relatively small FPD that contains two levels of logic, an AND-plane and an OR-plane, where both levels are programmable .
PAL — a Programmable Array Logic (PAL) is a relatively small FPD that has programmable AND- plane followed by a fixed OR-plane .
SPLD — refers to any type of Simple PLD, usually either a PLA or PAL
PLA and PAL

16. Programmable Logic Devices
Programming by blowing fuses.
(a) Before programming.
(b) After programming.
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17. PLD notations
(a) Unprogrammed AND-gate.
(b) Unprogrammed OR-gate.
(c) Programmed AND-gate realizing the term a*c.
(d) Programmed OR-gate realizing
the term a + b.
(e) Special notation for an AND gate having all its input fuses intact.
(f) Special notation for an OR gate having all its input fuses intact.
(g) AND gate with fixedinputs.
(h) OR gate with fixed inputs.
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18. 18
ROM
ROM – fixed AND –plane and fixed OR -plane
Input
output
Fixed AND
Fixed OR

19. Structure of a PROM
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20. PROM
ROM provides full decoding of variables:
Each intersection (cross point) in the ROM is often implemented with a fuse.
Blow out unnecessary connections according to the truth table
•“1”means connected(marked as X)
•“0” means unconnected
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21. PROM
EXAMPLE:
F1= Σ(0,1,2,5,7)
F2=Σ(1,2,4,6)
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22. PLA Structure
22

23. PLA Structure
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24. PLA
PLA does not provide full decoding of the variables Only generated desired min-terms you need.
More than 1 product terms can be shared among OR gates.
The OR array Ors together the product terms to form the outputs.
EXAMPLE:
F0 = A’B’+ AC’
F1 = B + AC’
F2 = A’B’+ BC’
F3 = AC + B
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25. PLA
F0 = A’B’+ AC’
F1 = B + AC’
F2 = A’B’+ BC’
F3 = AC + B
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26. PLA
F0 = A’B’+ AC’
F1 = B + AC’
F2 = A’B’+ BC’
F3 = AC + B
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27. PLA
F0 = A’B’+ AC’
F1 = B + AC’
F2 = A’B’+ BC’
F3 = AC + B
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28. PAL
PAL has a fixed OR array and a programmable AND array
Easier to program but not as flexible as PLA.
One of the outputs is fed back as two inputs of the AND gates.
Unlike PLA, a product term cannot be shared among gates.
Each function can be simplified by itself without common terms.
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29. PAL
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30. World of Integrated Circuits
Integrated Circuits
Full-Custom
ASICs
Semi-Custom
ASICs
User
Programmable
PLD
FPGA
PAL
PLA
PML
LUT
(Look-Up Table)
MUX
Gates

31. ASIC
An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC. Intermediate between ASICs and industry standard integrated circuits, like the 7400 or the 4000 series, are application specific standard products (ASSPs).
As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 million. Modern ASICs often include entire 32-bit processors, memory blocks including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a SoC (system-on-a-chip). Designers of digital ASICs use a hardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs.
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32. PLDs Versus ASIC
Application Specific Integrated Circuit (ASIC):
longer design cycle
faster performance
lower cost if produced in high volume
Programmable chips (PLD):
 Good for medium to low volume products.
If you need more than 10,000 chips, go for ASIC or hard copy

33. Hard Copy
An option to migrate FPGA into structured ASIC
 Removing all configuration circuitry
 High volume production availability
 40% less power
 The internal delays are reduced

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Field programmable gate arrays (FPGAs) are digital integrated circuits (Ics) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks .
FPGA — is an FPD featuring a general structure that allows very high logic capacity.
FPGAs offer more narrow logic resources .
FPGAs also offer a higher ratio of flip-flops to logic resources than do CPLDs.
APGA: analog programmable gate array(under research)
HCPLDs — high-capacity PLDs: a single acronym that refers to both CPLDs and FPGAs
What are FPGAs?

35. Very high logic capacity
Used for implementing digital hardware
Customized as per needs of the user by programming
Configurable as many time as you want
Low starting cost, Low risk
FPGA features

36. Complex PLD
CPLD — a more Complex PLD that consists of an arrangement of multiple SPLD-like blocks
on a single chip.(Enhanced PLD(EPLD),super PAL ,Mega PAL, and others ).
CPLDs feature logic resources with a wide number of inputs (AND planes) .
offer a low ratio of flip-flops to logic resources
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37. An array of uncommitted circuit elements, called logic blocks, and interconnect resources.
Two-level of programming:
Logic blocks
Interconnect resources
FPGA : Field Programmable Gate Array

38. FPGA : Field Programmable Gate Array
Switch Box (S-Box)
Pads
Connection Box (C-Box)
Lookup table (LUT)

39. Lookup Tables (LUTs)
 Implemented by memory
 2-bit address  4 memory entries
 E.g. AND gate

40. Logic Box (LB)
Logic Box consists of a LUT, a flip-flop and MUXs to allow different signal paths.
D-FF: Common one-phase clock.

41. Connection Box (C-Box)
Handles connections from LB to Pads or S-Box

42. Switch Box (S-Box)
Connects tracks from C-Boxes with each other

43. Putting all these together …
Overall structure of the layout of the chip
Your design

44. 44
Introduction (Cont’d)
Interconnect — the wiring resources in an FPD.
Programmable Switch — a user programmable switch that can connect a logic element to an interconnect wire, or one interconnect wire to another .
Logic Block — a relatively small circuit block that is replicated in an array in an FPD.
Logic Capacity — the amount of digital logic that can be mapped into a single FPD.

45. 45
Introduction (Cont’d)
Logic Density—the amount of logic per unit area in an FPD.
Speed-Performance — measures the maximum operable speed of a circuit when implemented in an FPD.
For combinational circuits, it is set by the longest delay through any path .
Sequential circuits , it is the maximum clock frequency for which the circuit functions properly.

46. 46
What can FPGAs be used for ?
In the mid_1980s FPGAs were largely used to implement glue logic (large logical blocks ,functions ,or devices).
During the early 1990s as the size and sophistication of FPGAs started to increase ,their big markets at that time were in the telecommunications and networking arenas.
By the early of 2000s high-performance FPGAs Containing millions of gates had become available
Some of these devices feature embedded microprocessor cores, high-speed (I/o) interfaces, and the like

47. 47
What can FPGAs be used for ?
Today’s FPGA`s can be used to implement just about anything including communication devices and software-defined radios ;radar ,image, and other DSP applications; all the way up to (SoC) components that contain both S/W and H/W elements .

48. FPGA Advantages
Fast digital design, no wait to obtaining a target chip.
The design can be implemented on the FPGA and tested at once.
FPGAs are good prototypes.
After final design, the product is so small size.
The designer can be used the same FPGA more than design.

49. FPGA Applications
New CPU or DSP cores.
Computer architecture expirements.
Build lab test equipment –clock and pulse.
Telecommunications protocol analyzer.
Sigma-delta DAC.
Digital modulator,modem etc.
Neural network.

50. Programming languages based design flow
-VHDL
V H I S C : Very High Speed Integrated circuit
Hardware
Description
Language.
-Verilog HDL
-AHDL(Altera HDL) ,
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51. Programming languages based design flow
-Labview system
-JAVA
-impulse-C ,handel-C .
-SA-C (single assignment compiler) for image processing applications.
-stream c:convert c code to VHDL code.
-matlab 2007A(7.4) simulink HDL coder toolbox .
-SystemC : language C++ with additional elements hardware-based
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52. About VHDL
 It describes the behavior of an electronic circuit or system, from which the physical circuit or system can then be attained (implemented).
Designed by IBM, Texas Instruments, an Intermetrics as part of the DoD (department of defense ) funded VHSIC program
Standardized by the IEEE in 1987:
IEEE 1076-1987
Enhanced version of the language defined in 1993:
IEEE 1076-1993
• Additional standardized packages provide definitions
of data types and expressions of timing data
– IEEE 1164 (data types)
– IEEE 1076.3 (numeric)
– IEEE 1076.4 (timing)
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53. 53
VHDL vs. Verilog
Commercially Developed
Government Developed
C based
Ada based
Mildly Type Cast
Strongly Type Cast
Easier to Learn
Difficult to learn
Less Powerful
More Powerful

54. 54
FPGA vendors
Xilinx ,AT&T (major competitor) .
Altera .
Actel , Quick logic and Cypress (antifuse based) .
Lattic
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55. EDA Tools
EDA(Electronic Design Automation )tools available for circuit synthesis ,implementation ,and simulation using VHDL .
Altera’s Quartus Π,Max plus Π (for Alter’s CPLD/FPGA chips).
Xilinx’s ISE suite (Xilinx's CPLD/FPGA chips).
Specialized EDA companies :
Mentor Graphics , Synopsis ,Synplicity , Leonardo Spectrum and ModelSim .
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56. Computer Aided Design(CAD) flow
56

57. CAD flow
A typical CAD system for SPLDs or CPLDs would include software for the following tasks:
 Initial
Design entry (schematic diagram or hdl text or mixture of both)
Logic optimization (algorithms are employed to optimize the circuits .
Device fitting .
 Simulation ( verify correct operation)
 Configuration (file loaded into a programming unit ).
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58. The Design process For FPGAs
The design process for FPGAs is similar to that for CPLDs, but additional tools are needed to support the increased complexity of the chips.
The major difference is in the “device fitter” step where FPGAs require at least three steps:
A technology mapper to map from basic logic gates into the FPGA’s logic blocks.
Placement to choose which specific logic blocks to use in the FPGA .
A router to allocate the wire segments in the FPGA to interconnect the logic blocks.
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59. CMOS IC Design Alternatives
59
STANDARD
IC
ASIC
FULL
CUSTOM
SEMI-
CUSTOM
FIELD
PROGRAM-
MABLE
STANDARD
CELL
GATE ARRAY,
SEA OF GATES
CPLD
FPGA

60. ASIC
60
Standard cells
Like multiplier or adder
(MPGA)Gate array
mask programmable IC
FPGA
User programmable
PLA
For simple tasks
In the field of programmable logic devices (CPLD , FPGA).
In the field of ASIC (Application specific integrated circuits).

61. A Final note
Contrary to regular computer programs
which are sequential, its statements are inherently concurrent (parallel).
 For that reason, VHDL is usually referred to as a code rather than a program.
 In VHDL , only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are executed sequentially.
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62. Translation of VHDL code into a circuit
62

63. 63

64. Description of the code
ENTITY, which is a description of the pins (PORTS) of the circuit .
An ARCHITECTURE, which describes how the circuit should function (behavior ,structure)
there are several ways of implementing the equations described in the ARCHITECTURE .
the actual circuit will depend on the compiler/optimizer being used and, more importantly, on the target technology .
64

65. Actual circuit for PLD or FPGA
65

66. Actual circuit for ASIC
66

67. Simulation results from VHDL design
67
The input pins (characterized by an inward arrow with an I marked inside) The output pins (characterized by an outward arrow with an O marked inside)

68. Fundamental sections of a basic VHDL code.
68

69. A standalone piece of VHDL code is composed of at least three fundamental sections:
LIBRARY declarations: Contains a list of all libraries to be used in the design. For example: ieee , std , work , etc.
 ENTITY: Specifies the I/O pins of the circuit.
 ARCHITECTURE: Contains the VHDL code proper, which describes how the circuit should behave (function).
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70. Fundamental parts of a LIBRARY.
70

71. Design Entity
Design Entity - most basic building block of a design.
One entity can have
many different architectures.
entity declaration
architecture 1
architecture 2
architecture 3
design entity

72. ECE 449 – Computer Design Lab
Entity Declaration
 Entity Declaration describes the interface of the component, i.e. input and output ports.
entity AND2_OP is port( A, B: in std_logic; Z : out std_logic ); end AND2_OP;
Reserved words
Entity name
Port names
Port type
Semicolon
No Semicolon
Port modes (data flow directions)

73. Architecture Declaration
Describes an implementation of a design entity.
Architecture declaration example:
architecture MODEL of AND2_OP is begin Z <= A and B; end MODEL;

74. Entity Declaration & Architecture
library IEEE; use IEEE.std_logic_1164.all; entity AND2_OP is port( A, B: in std_logic; Z : out std_logic); end AND2_OP; architecture MODEL of AND2_OP is begin Z <= A and B; end MODEL;

75. 75
Signal modes

76. ECE 449 – Computer Design Lab
Mode In
A
Entity
Port signal
Driver resides
outside the entity
طرف للقراءة فقط
ويظهر علي يمين
المعادلة

77. ECE 449 – Computer Design Lab
Mode out
Entity
Port signal
Driver resides
inside the entity
Can’t read out
within an entity
Z
C<=Z
C
طرف للكتابة
فقط ويظهر علي
شمال المعادلة

78. Mode out with signal
Port signal
Entity
Driver resides
inside the entity
Signal Int can be
read inside the entity
Int
C
Z
Z<= Int
C<= Int

79. Mode inout
Signal can be
read inside the entity
Entity
Port signal
Driver may reside
both inside and outside
the entity
A
يوضع يمين او
شمال المعادلة ولكن
في الوقت الواحد
يعمل وظيفة واحدة
مثل data bus

80. Mode buffer
Entity
Port signal
Driver resides
inside the entity
Port signal Z can be
read inside the entity
C
Z
C<= Z
طرف خرج
يمكن قراءته مثل
حالة ال
counter

81. Port Modes
The Port Mode of the interface describes the direction in which data travels with respect to the component
In: Data comes in this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment.
Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment.
Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment.
Buffer: Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement the signal can appear on the left and right sides of the <= operator

82. Design in mentor graphics

83. Simulation

84. Half adder

85. Simulation

86. Asynchronous DFF

87. Simulation

88. Synchronous DFF

89. Simulation

90. Dual edge DFF

91. Simulation

92. DFF plus NAND Gate

93. Code

94. Simulation

95. Full Adder Using Half Adder
U0
U1
a
b
cin
cout
s
a
b
a
b
c
s
c
s
Signal x1
Signal x2
Signal x0

96. Code

97. Simulation

98. Component & package
98

99. Example
Signal w

100. Declarations In The Main Code

101. Declarations In a Package

102. Inverter.vhd

103. Nand_2.vhd

104. Nand_3.vhd

105. Project.vhd

106. Project.vhd

107. Components Declared in a Package

108. my_components.vhd

109. Project2.vhd
To use package

110. 2 bit adder
2 _bit
adder
2 bit
2 bit
3 bit
A
B

111. 2_bit adder
Full adder
Half adder
Y(0)
Y(1)
Y(2)
A(0)
B(0)
A(1)
B(1)
Signal x

112. program

113. Simulation

114. 2_bit multiplier
Y=a*b
2_bit
2_bit
4_bit

115. Half adder
A(0)
A(1)
A(1)
B(0)
A(0)
B(1)
A(1)
B(1)
x0
x1
x3
x2
Y(0)
Half adder
Y(1)
Y(3)
Y(2)
c
s
c
s
a
b
a
b

116. code

117. code

118. simulation

119. 10 bit adder
adder
A 10 bit
b
10 bit
Y
11 bit

120. code

121. simulation

122. 4-bit adder with concatenation
122

123. Simulation
123

124. 124
Data types

125. Pre-Defined Data Types
VHDL contains a series of pre-defined data types, specified through the IEEE 1076 and IEEE 1164 standards. More specifically, such data type definitions can be found in the following packages / libraries:
Package standard of library std: Defines BIT, BOOLEAN, INTEGER, and REAL
data types.
Package std_logic_1164 of library ieee: Defines STD_LOGIC and STD_ULOGIC
data types.
Package std_logic_arith of library ieee: Defines SIGNED and UNSIGNED
data types, plus several data conversion functions, like conv_integer(p),
conv_unsigned(p, b), conv_signed(p, b), and conv_std_logic_vector(p, b).
Packages std_logic_signed and std_logic_unsigned of library ieee: Contain functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type SIGNED or UNSIGNED, respectively
125

126. Examples
SIGNAL x: BIT;
-- x is declared as a one-digit signal of type BIT.
SIGNAL y: BIT_VECTOR (3 DOWNTO 0);
-- y is a 4-bit vector, with the leftmost bit being the MSB.
SIGNAL w: BIT_VECTOR (0 TO 7);
-- w is an 8-bit vector, with the rightmost bit being the MSB
126

127. std_logic type Demystified
Value
Meaning
‘_’
Don’t care
‘X’
Forcing (Strong driven) Unknown
‘0’
Forcing (Strong driven) 0
‘1’
Forcing (Strong driven) 1
‘Z’
High Impedance
‘W’
Weak (Weakly driven) Unknown
‘L’
Weak (Weakly driven) 0. Models a pull down.
‘H’
Weak (Weakly driven) 1. Models a pull up.
synthesizable

128. std_ulogic type Demystified
Value
Meaning
‘U’
Not Initialized (unresolved)
‘X’
Forcing (Strong driven) Unknown
‘0’
Forcing (Strong driven) 0
‘1’
Forcing (Strong driven) 1
‘Z’
High Impedance
‘W’
Weak (Weakly driven) Unknown
‘L’
Weak (Weakly driven) 0. Models a pull down.
‘H’
Weak (Weakly driven) 1. Models a pull up.
‘-’
Don't Care
9_level logic system

129. Std_logic vesus std_unlogic
•A resolution function examines all the drivers on a shared signal and determines the value to be assigned to the signal
•Using a LUT in the IEEE 1164 package
Std_logic
Std_ulogic
•Unresolved std_logic
•Multiple drivers  error
•Used to detect design errors

130. More on std_logic Meanings (1)
‘1’
‘0’
‘X’
Contention on the bus
•Value of all signals at the beginning of simulation
•Value of all signals that remain un-driven throughout simulation
U
X

131. More on std_logic Meanings (2)

132. More on std_logic Meanings (3)
•Do not care.
•Can be assigned to outputs for the case of invalid inputs (may produce significant improvement in resource utilization after synthesis).
‘-’
Resolved logic system (std_logic)

133. Another data types
BOOLEAN: True, False.
INTEGER: 32-bit integers (from 2,147,483,647 to 2,147,483,647).
NATURAL: Non-negative integers (from 0 to 2,147,483,647).
REAL: Real numbers ranging from 1.0E38 to 1.0E38. Not synthesizable.
Physical literals: Used to inform physical quantities, like time, voltage, etc. Useful
in simulations. Not synthesizable.
Character literals: Single ASCII character or a string of such characters. Not
synthesizable.
SIGNED and UNSIGNED: data types defined in the std_logic_arith package of
the ieee library. They have the appearance of STD_LOGIC_VECTOR, but accept
arithmetic operations, which are typical of INTEGER data types
133

134. Example
x0 <= '0'; -- bit, std_logic, or std_ulogic value '0‘
x1 <= "00011111"; -- bit_vector, std_logic_vector,
-- std_ulogic_vector, signed, or unsigned
x2 <= "0001_1111"; -- underscore allowed to ease visualization
x3 <= "101111" -- binary representation of decimal 47
134

135. Example
x4 <= B"101111" -- binary representation of decimal 47
x5 <= O"57" -- octal representation of decimal 47
x6 <= X"2F" -- hexadecimal representation of decimal 4
n<= 1200; -- integer
m<= 1_200; -- integer, underscore allowed
IF ready THEN... -- Boolean, executed if ready=TRUE
y<= 1.2E-5; -- real, not synthesizable
q<=d after 10 ns; -- physical, not synthesizable
135

136. Legal and illegal operations between data of different types
SIGNAL a: BIT;
SIGNAL b: BIT_VECTOR(7 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: INTEGER RANGE 0 TO 255
a<= b(5); -- legal (same scalar type : bit )
b(0) <= a; -- legal (same scalar type : bit )
c<= d(5); -- legal (same scalar type : std_logic )
d(0) <= c; -- legal (same scalar type : std_logic )
a<=c;-- illegal (type mismatch: bit x std_logic )
b<=d;-- illegal (type mismatch: bit _vector x
-- STD_LOGIC_VECTOR)
e<=b; -- illegal (type mismatch: integer x bit _vector )
e<=d;-- illegal (type mismatch: integer x
-- STD_LOGIC_VECTOR)
136

137. CONSTANT
CONSTANT serves to establish default values. Its syntax is shown below.
CONSTANT name : type := value;
Examples:
CONSTANT set_bit : BIT := '1';
CONSTANT datamemory : memory := ( ('0','0','0','0'),
('0','0','0','1'),
 ('0','0','1','1') );
137

138. constant
A CONSTANT can be declared in a PACKAGE, ENTITY, or ARCHITECTURE.
When declared in a package, it is truly global, for the package can be used by several entities.
When declared in an entity (after PORT), it is global to all architectures that follow that entity.
Finally, when declared in an architecture (in its declarative part), it is global only to that architecture’s code. The most common places to find a CONSTANT declaration is in an ARCHITECTURE or in a PACKAGE.
138

139. SIGNAL
SIGNAL serves to pass values in and out the circuit, as well as between its internal units.
 In other words, a signal represents circuit interconnects (wires).
 For instance,all PORTS of an ENTITY are signals by default. Its syntax is the following:
SIGNAL name : type [range] [:= initial_value];
139

140. Example
Examples:
SIGNAL control: BIT := '0';
SIGNAL count: INTEGER RANGE 0 TO 100;
SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0);
140

141. The declaration of a SIGNAL can be made in the same places as the declaration of a CONSTANT (described above).
A very important aspect of a SIGNAL, when used inside a section of sequential code (PROCESS, for example), is that its update is not immediate.
 In other words, its new value should not be expected to be ready before the conclusion of the corresponding PROCESS, FUNCTION or PROCEDURE.
Recall that the assignment operator for a SIGNAL is ‘‘<=’’ (Ex.: count<=35;).
Another aspect that might affect the result is when multiple assignments are made to the same SIGNAL. The compiler might complain and quit synthesis, or might infer the wrong circuit (by considering only the last assignment, for example).
141

142. Count Ones #1 (not OK)
142

143. comment
Notice also in the solution above that the internal signal temp (line 11) seems unnecessary,
because ones could have been used directly. However, to do so, the mode
of ones would need to be changed from OUT to BUFFER (line 7), because ones is
assigned a value and is also read (used) internally. Nevertheless, since ones is a genuine
unidirectional (OUT) signal, the use of an auxiliary signal (temp) is an adequate
design practice.
143

144. VARIABLE
Contrary to CONSTANT and SIGNAL, a VARIABLE represents only local information.
It can only be used inside a PROCESS, FUNCTION, or PROCEDURE (that is, in sequential code), and its value can not be passed out directly.
On the other hand, its update is immediate, so the new value can be promptly used in the next line of code.
To declare a VARIABLE, the following syntax should be used:
 VARIABLE name : type [range] [:= init_value];
144

145. example
Examples:
VARIABLE control: BIT := '0';
VARIABLE count: INTEGER RANGE 0 TO 100;
VARIABLE y: STD_LOGIC_VECTOR (7 DOWNTO 0) := "10001000";
145

146. variable
Since a VARIABLE can only be used in sequential code,
its declaration can only be done in the declarative part of a PROCESS, FUNCTION, or PROCEDURE.
Recall that the assignment operator for a VARIABLE is ‘‘:=’’ (Ex.: count:=35;).
Also, like in the case of a SIGNAL, the initial value in the syntax above is not synthesizable, being only considered in simulations.
146

147. Count Ones #2 (OK)
LIBRARY ieee;
 USE ieee.std_logic_1164.all;
---------------------------------------
 ENTITY count_ones IS
 PORT ( din: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
 ones: OUT INTEGER RANGE 0 TO 8);
END count_ones;
147

148. architecture
 ARCHITECTURE ok OF count_ones IS
 BEGIN
PROCESS (din)
 VARIABLE temp: INTEGER RANGE 0 TO 8;
BEGIN
 temp := 0;
 FOR i IN 0 TO 7 LOOP
 IF (din(i)='1') THEN
 temp := temp + 1;
 END IF;
 END LOOP;
ones <= temp;
 END PROCESS;
 END ok;
148

149. SIGNAL versus VARIABLE
149

150. Ram
150

151. ram
151

152. 152

153. ALU
153

154. Tabel
154

155. code
155

156. 156