CMOS switches and logic gates

1. ECE2030
Introduction to Computer Engineering
Lecture 4: CMOS Network
Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean Lee
School of Electrical and Computer EngineeringSchool of Electrical and Computer Engineering
Georgia TechGeorgia Tech

2. CMOS Inverter
• Connect the following terminals of a PMOS and an NMOS
– Gates
– Drains
Vin Vout
Vdd
Gnd
Vout
Vin
Vin
Vin = HIGH
Vout = LOW (Gnd)
ONON
OFFOFF
Vdd
Gnd
Vout
Vin
Vin
Vin = LOW
Vout = HIGH (Vdd)
ONON
OFFOFF
Vdd
PMOS
Ground
NMOS

3. CMOS Voltage Transfer Characteristics
Vdd
Gnd
Vin Vout
PMOS
NMOS
OFF: V_GateToSource < V_Threshold
LINEAR (or OHMIC): 0< V_DrainToSource < V_GateToSource - V_Threshold
SATURATION: 0 < V_GateToSource - V_Threshold < V_DrainToSource
Note that in the CMOS Inverter → V_GateToSource = V_in

4. Pull-Up and Pull-Down Network
• CMOS network consists of a Pull-UP
Network (PUN) and a Pull-Down
Network (PDN)
• PUN consists of a set of PMOS
transistors
• PDN consists of a set of NMOS
transistors
• PUN and PDN implementations are
complimentary to each other
– PMOS ↔ NOMS
– Series topology ↔ Parallel topology
….
I0
I1
In-1
OUPTUT
Vdd
PUN
Gnd
PDN

5. PUN/PDN of a CMOS Inverter
A B
0 1
1 Z
A B
0 Z
1 0
A B
0 1
1 0
Pull-Up
Network
Pull-Down
Network
Combined
CMOS
Network
Vdd
A
Gnd
B
CMOS Inverter

6. Gate Symbol of a CMOS Inverter
Vdd
A
Gnd
B
CMOS Inverter
A B
B = Ā

7. PUN/PDN of a NAND Gate
A B C
0 0 1
0 1 1
1 0 1
1 1 Z
A B C
0 0 Z
0 1 Z
1 0 Z
1 1 0
Pull-Up
Network
Pull-Down
Network
Vdd
A
B
A B
C

8. PUN/PDN of a NAND Gate
A B C
0 0 1
0 1 1
1 0 1
1 1 Z
A B C
0 0 Z
0 1 Z
1 0 Z
1 1 0
A B C
0 0 1
0 1 1
1 0 1
1 1 0
Pull-Up
Network
Pull-Down
Network
Combined
CMOS
Network
Vdd
A
B
A B
C

9. NAND Gate Symbol
A B C
0 0 1
0 1 1
1 0 1
1 1 0
Vdd
A
B
A B
C
A
B
C
Truth Table
BAC ⋅=

10. 0
PUN/PDN of a NOR Gate
A B C
0 0 1
0 1 Z
1 0 Z
1 1 Z
A B C
0 0 Z
0 1 0
1 0 0
1 1 0
Pull-Up
Network
Pull-Down
Network
Vdd
A
C
B
A B

11. 1
PUN/PDN of a NOR Gate
A B C
0 0 1
0 1 Z
1 0 Z
1 1 Z
A B C
0 0 Z
0 1 0
1 0 0
1 1 0
A B C
0 0 1
0 1 0
1 0 0
1 1 0
Pull-Up
Network
Pull-Down
Network
Combined
CMOS
Network
A
C
B
A B
Vdd

12. 2
NOR Gate Symbol
A B C
0 0 1
0 1 0
1 0 0
1 1 0
A
B
C
Truth Table
A
C
B
A B
BAC +=
Vdd

13. 3
How about an AND gate
Vdd
A
B
A
Vdd
Gnd
C
NAN
D
Inverter
B
C = A B
A
B
C

14. 4
An OR Gate
A
B
A B
Vdd
Vdd
Gnd
C
Inverter
NOR
A
B
C
BAC +=

15. 5
What’s the Function of the following CMOS Network?
A B C
0 0 Z
0 1 1
1 0 1
1 1 Z
A B C
0 0 0
0 1 Z
1 0 Z
1 1 0
A B C
0 0 0
0 1 1
1 0 1
1 1 0
Pull-Up
Network
Pull-Down
Network
Combined
CMOS
Network
Function = XORXOR
Vdd
A
B
A
A
A
B
B
B
C

16. 6
Yet Another XOR CMOS Network
Vdd
A
B
A A
A
B
B
B
C
A B C
0 0 Z
0 1 1
1 0 1
1 1 Z
A B C
0 0 0
0 1 Z
1 0 Z
1 1 0
A B C
0 0 0
0 1 1
1 0 1
1 1 0
Pull-Up
Network
Pull-Down
Network
Combined
CMOS
Network
Function = XORXOR

17. 7
Exclusive-OR (XOR) Gate
Vdd
A
B
A A
A
B
B
B
C
A B C
0 0 0
0 1 1
1 0 1
1 1 0
A
B
C
Truth Table
BABABAC ⊕=⋅+⋅=

18. 8
How about XNORXNOR Gate
A B C
0 0 1
0 1 0
1 0 0
1 1 1
A
B
C
Truth Table
BABABAC ⊕=⋅+⋅=
How do we draw the
corresponding CMOS network
given a Boolean equation?

19. 9
How about XNORXNOR Gate
A B C
0 0 1
0 1 0
1 0 0
1 1 1
A
B
C
Truth Table
BABAC ⋅+⋅=
Vdd
A
B
A A
A
B
B
B
C
Vdd
XOR
Inverter

20. 0
A Systematic Method (I)
Start from Pull-Up Network
• Each variable in the given Boolean eqn corresponds to
a PMOS transistor in PUN and an NMOS transistor in
PDN
• Draw PUNPUN using PMOS based on the Boolean eqn
– ANDAND operation drawn in seriesseries
– OROR operation drawn in parallelparallel
• Invert each variablevariable of the Boolean eqn as the gate
input for each PMOS in the PUN
• Draw PDNPDN using NMOS in complementary form
– Parallel (PUN) to series (PDN)
– Series (PUN) to parallel (PDN)
• Label with the same inputs of PUN
• Label the output

21. 1
A Systematic Method (II)
Start from Pull-Down Network
• Each variable in the given Boolean eqn corresponds to a PMOS
transistor in PUN and an NMOS transistor in PDN
• Invert the Boolean eqn
• With the Right-Hand Side of the newly inverted equation, Draw
PDNPDN using NMOS
– ANDAND operation drawn in seriesseries
– OROR operation drawn in parallelparallel
• Label each variablevariable of the Boolean eqn as the gate input for
each NMOS in the PDN
• Draw PUNPUN using PMOS in complementary form
– Parallel (PUN) to series (PDN)
– Series (PUN) to parallel (PDN)
• Label with the same inputs of PUN
• Label the output

22. 2
Systematic Approaches
• Note that both methods lead to exactly the same
implementation of a CMOS network
• The reason to invert Output equation in (II) is
because
– Output (F) is conducting to “ground”, i.e. 0, when there is
a path formed by input NMOS transistors
– Inversion will force the desired result from the equation
• Example
– F=Ā·C + B: When (A=0 and C=1) or B=1, F=1. However, in
the PDN (NMOS) of a CMOS network, F=0, i.e. an inverse
result.
– Revisit how a NAND CMOS network is implemented
• Inverting each PMOS input in (I) follow the same
reasoning

23. 3
Example 1 (Method I)
BCAF +⋅=
In series
In parallel
Vdd
(1) Draw the Pull-Up Network

24. 4
Example 1 (Method I)
BCAF +⋅=
In series
In parallel
Vdd
(2) Assign the complemented input
A
C
B

25. 5
Example 1 (Method I)
BCAF +⋅=
In series
In parallel
Vdd
(3) Draw the Pull-Down Network in
the complementary form
A
C
B
A C

26. 6
Example 1 (Method I)
BCAF +⋅=
In series
In parallel
Vdd
(3) Draw the Pull-Down Network in
the complementary form
A
C
B
A C
B

27. 7
Example 1 (Method I)
BCAF +⋅=
In series
In parallel
Vdd
Label the output F
A
C
B
A C
B
F

28. 8
Example 1 (Method I)
BCAF +⋅=
In series
In parallel
Vdd
A
C
B
A C
B
F
A B C F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
Truth Table

29. 9
Drawing the Schematic using Method II
BCAF +⋅=
BC)A(F
BCAF
BCAF
⋅+=
⋅⋅=
+⋅=
Vdd
A
C
B
A C
B
F
This is exactly the same
CMOS network with the
schematic by Method I

30. 0
An Alternative for XNOR Gate (Method I)
A B C
0 0 1
0 1 0
1 0 0
1 1 1
A
B
C
Truth Table
BABAC ⋅+⋅=
Vdd
A
B
A
B
A
A B
B
C

31. 1
Example 3
)C(ABDAF +⋅+⋅=
Start from the innermost term
A
B D
AC
A D

32. 2
Example 3
)C(ABDAF +⋅+⋅=
Start from the innermost term
A
B D
AC
A D
A
C

33. 3
Example 3
)C(ABDAF +⋅+⋅=
Start from the innermost term
A
B D
AC
A D
A
C
B

34. 4
Example 3
)C(ABDAF +⋅+⋅=
Start from the innermost term
A
B D
AC
A D
A
C
B
Vdd
F
Pull-Up
Network
Pull-Down
Network

35. 5
Example 4
))C(ABDA()D(EF +⋅+⋅⋅+=
Start from the innermost term
A
B D
AC
A D
A
C
B
Vdd
F
E D
E
D
Pull-Down
Network
Pull-Up
Network

36. 6
Another Example
BCAF +⋅= How ??