3. Microprocessor
• Microprocessor (µP) is the “brain” of a computer
that has been implemented on one
semiconductor chip.
• The word comes from the combination micro and
processor.
• Processor means a device that processes
whatever(binary numbers, 0’s and 1’s)
To process means to manipulate. It describes all
manipulation.
Micro - > extremely small
3
4. Definition of a Microprocessor.
The microprocessor is a
programmable device that takes in numbers,
performs on them arithmetic or logical
operations according to the program stored in
memory and then produces other numbers as
a result.
4
5. Microprocessor ?
A microprocessor is multi
programmable clock driven
register based semiconductor
device that is used to fetch ,
process & execute a data
within fraction of seconds.
5
6. Applications
• Calculators
• Accounting system
• Games machine
• Instrumentation
• Traffic light Control
• Multi user, multi-function environments
• Military applications
• Communication systems
6
12. Intel 4004
Introduced in 1971.
It was the first microprocessor
by Intel.
It was a 4-bit µP.
Its clock speed was 740KHz.
It had 2,300 transistors.
It could execute around
60,000 instructions per
second.
12
15. Intel 8008
Introduced in 1972.
It was first 8-bit µP.
Its clock speed was
500 KHz.
Could execute
50,000 instructions
per second.
15
16. Intel 8080
Introduced in 1974.
It was also 8-bit µP.
Its clock speed was
2 MHz.
It had 6,000
transistors.
16
17. Intel 8085 Introduced in 1976.
It was also 8-bit µP.
Its clock speed was 3 MHz.
Its data bus is 8-bit and
address bus is 16-bit.
It had 6,500 transistors.
Could execute 7,69,230
instructions per second.
It could access 64 KB of
memory.
It had 246 instructions.
17
19. INTEL 8086
Introduced in 1978.
It was first 16-bit µP.
Its clock speed is 4.77 MHz, 8 MHz
and 10 MHz, depending on the
version.
Its data bus is 16-bit and address
bus is 20-bit.
It had 29,000 transistors.
Could execute 2.5 million
instructions per second.
It could access 1 MB of memory.
It had 22,000 instructions.
It had Multiply and Divide
instructions.
19
20. INTEL 8088
Introduced in 1979.
It was also 16-bit µP.
It was created as a
cheaper version of
Intel’s 8086.
It was a 16-bit processor
with an 8-bit external
bus.
20
21. INTEL 80186 & 80188
Introduced in 1982.
They were 16-bit µPs.
Clock speed was 6 MHz.
80188 was a cheaper
version of 80186 with an
8-bit external data bus.
21
22. INTEL 80286
Introduced in 1982.
It was 16-bit µP.
Its clock speed was 8
MHz.
Its data bus is 16-bit
and address bus is 24-
bit.
It could address 16 MB
of memory.
It had 1,34,000
transistors.
22
24. INTEL 80386
Introduced in 1986.
It was first 32-bit µP.
Its data bus is 32-bit
and address bus is 32-
bit.
It could address 4 GB of
memory.
It had 2,75,000
transistors.
Its clock speed varied
from 16 MHz to 33 MHz
depending upon the
various versions.
24
25. INTEL 80486
Introduced in 1989.
It was also 32-bit µP.
It had 1.2 million
transistors.
Its clock speed varied
from 16 MHz to 100
MHz depending upon
the various versions.
8 KB of cache memory
was introduced.
25
26. INTEL PENTIUM
Introduced in 1993.
It was also 32-bit µP.
It was originally named
80586.
Its clock speed was 66
MHz.
Its data bus is 32-bit
and address bus is 32-
bit.
26
27. INTEL PENTIUM PRO
Introduced in 1995.
It was also 32-bit µP.
It had 21 million
transistors.
Cache memory:
8 KB for instructions.
8 KB for data.
27
28. INTEL PENTIUM II
Introduced in 1997.
It was also 32-bit µP.
Its clock speed was 233
MHz to 500 MHz.
Could execute 333
million instructions per
second.
28
29. INTEL PENTIUM II XEON
Introduced in 1998.
It was also 32-bit µP.
It was designed for
servers.
Its clock speed was 400
MHz to 450 MHz.
29
30. INTEL PENTIUM III
Introduced in 1999.
It was also 32-bit µP.
Its clock speed varied
from 500 MHz to 1.4
GHz.
It had 9.5 million
transistors.
30
31. INTEL PENTIUM IV
Introduced in 2000.
It was also 32-bit µP.
Its clock speed was from
1.3 GHz to 3.8 GHz.
It had 42 million
transistors.
31
32. INTEL DUAL CORE
Introduced in 2006.
It is 32-bit or 64-bit µP.
32
37. Basic Terms
• Bit: A digit of the binary number { 0 or 1 }
• Nibble: 4 bit Byte: 8 bit word: 16 bit
• Double word: 32 bit
• Data: binary number/code operated by an
instruction
• Address: Identification number for memory
locations
• Clock: square wave used to synchronize various
devices in µP
• Memory Capacity = 2^n ,
n->no. of address lines
37
38. BUS CONCEPT
• BUS: Group of conducting lines that carries data ,
address & control signals.
CLASSIFICATION OF BUSES:
1.DATA BUS: group of conducting lines that carries
data.
2. ADDRESS BUS: group of conducting lines that
carries address.
3.CONTROL BUS: group of conducting lines that
carries control signals {RD, WR etc}
CPU BUS: group of conducting lines that directly
connected to µP
SYSTEM BUS: group of conducting lines that carries
data , address & control signals in a µP system
38
39. TRISTATE LOGIC
3 logic levels are:
• High State (logic 1)
• Low state (logic 0)
• High Impedance state
High Impedance: output is not being driven to any defined logic level
by the output circuit.
39
40. Basic Microprocessors System
Input
Devices
Processing
Data into
Information
Output
Devices
Control
Unit
Secondary Storage Devices
Arithmetic-
Logic
Unit
Primary Storage
Unit
Central Processing Unit
Keyboard,
Mouse
etc
Monitor
Printer
Disks, Tapes, Optical Disks
40
42. UNIT 1 Syllabus
• Hardware Architecture, pinouts
• Functional Building Blocks of Processor
• Memory organization
• I/O ports and data transfer concepts
• Timing Diagram
• Interrupts.
42
45. X1 & X2
Pin 1 and Pin 2 (Input)
45
These are also called
Crystal Input Pins.
8085 can generate clock
signals internally.
To generate clock
signals internally, 8085
requires external inputs
from X1 and X2.
46. RESET IN and RESET OUT
Pin 36 (Input) and Pin 3 (Output)
46
RESET IN:
◦ It is used to reset the
microprocessor.
◦ It is active low signal.
◦ When the signal on this
pin is low for at least 3
clocking cycles, it forces
the microprocessor to
reset itself.
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
47. RESET IN and RESET OUT
Pin 36 (Input) and Pin 3 (Output)
47
Resetting the
microprocessor means:
◦ Clearing the PC and IR.
◦ Disabling all interrupts
(exceptTRAP).
◦ Disabling the SOD pin.
◦ All the buses (data,
address, control) are tri-
stated.
◦ Gives HIGH output to
RESET OUT pin.
48. RESET IN and RESET OUT
Pin 36 (Input) and Pin 3 (Output)
48
RESET OUT:
◦ It is used to reset the peripheral
devices and other ICs on the
circuit.
◦ It is an output signal.
◦ It is an active high signal.
◦ The output on this pin goes high
whenever RESET IN is given low
signal.
◦ The output remains high as long
as RESET IN is kept low.
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
49. SID and SOD
Pin 4 (Input) and Pin 5 (Output)
49
SID (Serial Input
Data):
o It takes 1 bit input from
serial port of 8085.
o Stores the bit at the 8th
position (MSB) of the
Accumulator.
o RIM (Read Interrupt
Mask) instruction is used
to transfer the bit.
50. SID and SOD
Pin 4 (Input) and Pin 5 (Output)
50
SOD (Serial Output
Data):
o It takes 1 bit from
Accumulator to serial port
of 8085.
o Takes the bit from the 8th
position (MSB) of the
Accumulator.
o SIM (Set Interrupt Mask)
instruction is used to
transfer the bit.
51. Interrupt Pins
51
Interrupt:
• It means interrupting the normal execution of the
microprocessor.
• When microprocessor receives interrupt signal, it discontinues
whatever it was executing.
• It starts executing new program indicated by the interrupt
signal.
• Interrupt signals are generated by external peripheral devices.
• After execution of the new program, microprocessor goes
back to the previous program.
52. Sequence of StepsWheneverThere is
an Interrupt
52
Microprocessor completes execution of current
instruction of the program.
PC contents are stored in stack.
PC is loaded with address of the new program.
After executing the new program, the
microprocessor returns back to the previous
program.
It goes to the previous program by reading the top
value of stack.
54. Classification of Interrupts
54
Maskable and Non-Maskable
Vectored and Non-Vectored
EdgeTriggered and LevelTriggered
Priority Based Interrupts
55. Maskable Interrupts
55
Maskable interrupts are those interrupts
which can be enabled or disabled.
Enabling and Disabling is done by
software instructions.
57. Non-Maskable Interrupts
57
The interrupts which are always in
enabled mode are called non-maskable
interrupts.
These interrupts can never be disabled
by any software instruction.
TRAP is a non-maskable interrupt.
58. Vectored Interrupts
58
The interrupts which have fixed memory
location for transfer of control from
normal execution.
Each vectored interrupt points to the
particular location in memory.
60. Vectored Interrupts
60
The addresses to which program control
goes:
Absolute address is calculated by
multiplying the RST value with 0008 H.
Name Vectored Address
RST 7.5 003C H (7.5 x 0008 H)
RST 6.5 0034 H (6.5 x 0008 H)
RST 5.5 002C H (5.5 x 0008 H)
TRAP 0024 H (4.5 x 0008 H)
61. Non-Vectored Interrupts
61
The interrupts which don't have fixed
memory location for transfer of control
from normal execution.
The address of the memory location is
sent along with the interrupt.
INTR is a non-vectored interrupt.
62. EdgeTriggered Interrupts
62
The interrupts which are triggered at
leading or trailing edge are called edge
triggered interrupts.
RST 7.5 is an edge triggered interrupt.
It is triggered during the leading
(positive) edge.
63. LevelTriggered Interrupts
63
The interrupts which are triggered at high
or low level are called level triggered
interrupts.
RST 6.5
RST 5.5
INTR
TRAP is edge and level triggered interrupt.
64. Priority Based Interrupts
64
Whenever there exists a simultaneous
request at two or more pins then the
pin with higher priority is selected by the
microprocessor.
Priority is considered only when there
are simultaneous requests.
66. TRAP
Pin 6 (Input)
66
It is an non-maskable interrupt.
It has the highest priority.
It cannot be disabled.
It is both edge and level
triggered.
It means TRAP signal must go
from low to high.
And must remain high for a
certain period of time.
TRAP is usually used for power
failure and emergency shutoff.
67. RST 7.5
Pin 7 (Input)
67
It is a maskable interrupt.
It has the second highest
priority.
It is positive edge triggered
only.
The internal flip-flop is
triggered by the rising
edge.
The flip-flop remains high
until it is cleared by RESET
IN.
68. RST 6.5
Pin 8 (Input)
68
It is a maskable interrupt.
It has the third highest
priority.
It is level triggered only.
The pin has to be held high
for a specific period of
time.
RST 6.5 can be enabled by
EI instruction.
It can be disabled by DI
instruction.
69. RST 5.5
Pin 9 (Input)
69
It is a maskable
interrupt.
It has the fourth highest
priority.
It is also level triggered.
The pin has to be held
high for a specific period
of time.
This interrupt is very
similar to RST 6.5.
70. INTR
Pin 10 (Input)
70
It is a maskable interrupt.
It has the lowest priority.
It is also level triggered.
It is a general purpose
interrupt.
By general purpose we
mean that it can be used to
vector microprocessor to
any specific subroutine
having any address.
71. INTA
Pin 11 (Output)
71
It stands for interrupt
acknowledge.
It is an out going signal.
It is an active low signal.
Low output on this pin
indicates that
microprocessor has
acknowledged the INTR
request.
72. Address and Data Pins
72
Address Bus:
• The address bus is used to send address to
memory.
• It selects one of the many locations in
memory.
• Its size is 16-bit.
73. Address and Data Pins
73
Data Bus:
• It is used to transfer data between
microprocessor and memory.
• Data bus is of 8-bit.
74. AD0 – AD7
Pin 19-12 (Bidirectional)
74
These pins serve the dual
purpose of transmitting lower
order address and data byte.
During 1st clock cycle, these pins
act as lower half of address.
In remaining clock cycles, these
pins act as data bus.
The separation of lower order
address and data is done by
address latch.
75. A8 – A15
Pin 21-28 (Unidirectional)
75
These pins carry the
higher order of address
bus.
The address is sent from
microprocessor to
memory.
These 8 pins are switched
to high impedance state
during HOLD and RESET
mode.
76. ALE
Pin 30 (Output)
76
It is used to enable Address
Latch.
It indicates whether bus
functions as address bus or data
bus.
If ALE = 1 then
◦ Bus functions as address bus.
If ALE = 0 then
◦ Bus functions as data bus.
77. S0 and S1
Pin 29 (Output) and Pin 33 (Output)
77
S0 and S1 are called Status
Pins.
They tell the current
operation which is in progress
in 8085.
S0 S1 Operation
0 0 Halt
0 1 Write
1 0 Read
1 1 Opcode Fetch
78. IO/M
Pin 34 (Output)
78
This pin tells whether I/O
or memory operation is
being performed.
If IO/M = 1 then
◦ I/O operation is being
performed.
If IO/M = 0 then
◦ Memory operation is being
performed.
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
79. IO/M
Pin 34 (Output)
79
The operation being performed is indicated by
S0 and S1.
If S0 = 0 and S1 = 1 then
◦ It indicatesWRITE operation.
If IO/M = 0 then
◦ It indicates Memory operation.
Combining these two we get MemoryWrite
Operation.
81. RD
Pin 32 (Output)
81
RD stands for Read.
It is an active low signal.
It is a control signal used
for Read operation either
from memory or from
Input device.
A low signal indicates that
data on the data bus must
be placed either from
selected memory location
or from input device.
82. WR
Pin 31 (Output)
82
WR stands for Write.
It is also active low signal.
It is a control signal used
for Write operation either
into memory or into
output device.
A low signal indicates that
data on the data bus must
be written into selected
memory location or into
output device.
83. READY
Pin 35 (Input)
83
This pin is used to
synchronize slower
peripheral devices with
fast microprocessor.
A low value causes the
microprocessor to
enter into wait state.
The microprocessor
remains in wait state
until the input at this pin
goes high.
84. HOLD
Pin 38 (Input)
84
HOLD pin is used to request
the microprocessor for DMA
transfer.
A high signal on this pin is a
request to microprocessor
to relinquish the hold on
buses.
This request is sent by DMA
controller.
Intel 8257 and Intel 8237 are
two DMA controllers.
85. HLDA
Pin 39 (Output)
85
HLDA stands for Hold
Acknowledge.
The microprocessor uses
this pin to acknowledge the
receipt of HOLD signal.
When HLDA signal goes high,
address bus, data bus, RD,
WR, IO/M pins are tri-
stated.
This means they are cut-off
from external environment.
86. HLDA
Pin 39 (Output)
86
The control of these
buses goes to DMA
Controller.
Control remains at
DMA Controller until
HOLD is held high.
When HOLD goes low,
HLDA also goes low
and the microprocessor
takes control of the
buses.
87. VSS andVCC
Pin 20 (Input) and Pin 40 (Input)
87
+5V power supply is
connected toVCC.
Ground signal is
connected toVSS.
88. THE 8085 AND ITS BUSSES
The 8085 is an 8-bit general purpose
microprocessor that can address 64K Byte of
memory.
It has 40 pins and uses +5V for power. It can run
at a maximum frequency of 3 MHz.
-The pins on the chip can be grouped into 6
groups:
Address Bus.
Data Bus.
Control and Status Signals.
Power supply and frequency.
Externally Initiated Signals.
Serial I/O ports. 88
89. The Address and Data Busses
The address bus has 8 signal lines A8 – A15 which are
unidirectional.
The other 8 address bits are multiplexed (time shared)
with the 8 data bits.
So, the bits AD0 – AD7 are bi-directional and serve
as A0 – A7 and D0 – D7 at the same time.
During the execution of the instruction, these
lines carry the address bits during the early part,
then during the late parts of the execution, they
carry the 8 data bits.
In order to separate the address from the data, we
can use a latch to save the value before the function
of the bits changes. 89
92. Accumulator
It is an 8 bit register
For any arithmetic and logical instruction one of the data
should be in this register
It is used for storing the result of any arithmetic and
logical manipulations.
It is also called as A register
All the data which are sent to I/O devices are sent via
A register.
92
93. Temporary register
It is used to hold the data during the
operation of arithmetic and logical operation
93
94. Sign Flag
If the D7 bit of the accumulator is set then
this flag is set i.e 1 meaning that the result is
in negative.
Ex. 7-8 = -1
94
95. Carry flag
During the arithmetic operation if a carry occurs then this
flag is set.
Ex. F1+1F= 101
Carry
95
96. Zero flag
During the arithmetic/ logical
operation if the result is zero then this
flag is set.
Ex. FF-FF = 00
96
97. Parity flag
After the of the arithmetic and logical
operation if the result is even then this flag is
set.
Ex. 0A-02 = 08
97
98. Auxiliary carry flag
During BCD arithmetic operation when a carry is
generated by D3 bit and passed on to D4 bit then
this flag is set.
Ex. 1F+11 = 0001 1111 +
0001 0001
= 0010 0000
98
99. Timing and control
It synchronizes all the operation with the
clock and generates the communication
between the microprocessor and
peripherals
99
100. Instruction Register and decoder
The instruction is loaded in the
instruction register
The decoder decodes them and establishes
the operation that has to be performed
100
101. Register array
The W and Z register are temporary
registers
Used to hold the 8 bit data during the
execution and it is used internally .
It is not used by the programmer.
101
103. Arithmetic and Logical unit
It is an 8 bit register
It is used for performing addition,
subtraction and logical operation.
AND, OR, NOT, XOR, CMP are
some of the logical operation.
103
104. Program Counter
It is a 16 bit register
It is used to point out the address of
the next instruction which is to be
executed
104Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
105. Stack pointer
It is a 16 bit register
It points the starting address of the stack .
105
106. Register Array
B, C, D, E, H and L are general purpose
register
All are 8 bit register
If the are combined as BC, DE and HL
they can store 16 bit data
106
108. 8085 Communication with Memory
Involves the following three steps
1. Identify the memory location (with address)
2. Generate Timing & Control signals
3. Data transfer takes place
108
116. Memory-mapped I/O
8085 uses its 16-bit address bus to identify a
memory location
Memory address space: 0000H to FFFFH
8085 needs to identify I/O devices also
I/O devices can be interfaced using
addresses from memory space
8085 treats such an I/O device as a memory
location
This is called Memory-mapped I/O
116
117. Peripheral-mapped I/O
8085 has a separate 8-bit addressing scheme
for I/O devices
I/O address space: 00H to FFH
This is called Peripheral-mapped I/O or
I/O-mapped I/O
117
118. 8085 Communication with I/O devices
Involves the following three steps
1. Identify the I/O device (with address)
2. Generate Timing & Control signals
3. Data transfer takes place
8085 communicates with a I/O device only if
there is a Program Instruction to do so
118
120. 2.Generate Timing & Control Signals
Memory-mapped I/O
Reading Input: IO/M = 0, RD = 0
Write to Output: IO/M = 0, WR = 0
Peripheral-mapped I/O
Reading Input: IO/M = 1, RD = 0
Write to Output: IO/M = 1, WR = 0
3. Data transfer takes place
120
121. 8085 Communication with I/O devices
Involves the following three steps
Identify the I/O device (with address)
Generate Timing & Control signals
Data transfer takes place
8085 communicates with a I/O device only if
there is a Program Instruction to do so
121
122. Peripheral I/O Instructions
IN Instruction
Inputs data from input device into the
accumulator
It is a 2-byte instruction
Format: IN 8-bit port address
Example: IN 01H
122
123. OUT Instruction
Outputs the contents of accumulator to an
output device
It is a 2-byte instruction
Format: OUT 8-bit port address
Example: OUT 02H
123
124. ----------Example Program----------
WAP to read a number from input port (port
address 01H) and display it on ASCII display
connected to output port (port address 02H)
IN 01H ;reads data value 03H (example)into
;accumulator, A = 03H
MVI B, 30H;loads register B with 30H
ADD B ;A = 33H, ASCII code for 3
OUT 02H ;display 3 on ASCII display
124
125. Memory-mapped I/O Instructions
I/O devices are identified by 16-bit addresses
8085 communicates with an I/O device as if it
were one of the memory locations
Memory related instructions are used
For e.g. LDA, STA
LDA 8000H
Loads A with data read from input device with
16-bit address 8000H
STA 8001H
Stores (Outputs) contents of A to output
device with 16-bit address 8001H 125
126. ----------Example Program----------
WAP to read a number from input port (port
address 8000H) and display it on ASCII
display connected to output port (port
address 8001H)
LDA 8000H;reads data value 03H (example)into
;accumulator, A = 03H
MVI B, 30H;loads register B with 30H
ADD B ;A = 33H, ASCII code for 3
STA 8001H;display 3 on ASCII display
126
128. Timing Diagram is a graphical representation. It
represents the execution time taken by each
instruction in a graphical format. The execution
time is represented in T-states.
Instruction Cycle:
The time required to execute an instruction .
Machine Cycle:
The time required to access the memory or
input/output devices .
T-State:
•The machine cycle and instruction cycle takes
multiple clock periods.
•A portion of an operation carried out in one
system clock period is called as T-state.
128
133. OPCODE FETCH
• The Opcode fetch cycle, fetches the instructions from memory
and delivers it to the instruction register of the microprocessor
• Opcode fetch machine cycle consists of 4 T-states.
T1 State:
During the T1 state, the contents of the program counter are
placed on the 16 bit address bus. The higher order 8 bits are
transferred to address bus (A8-A15) and lower order 8 bits are
transferred to multiplexed A/D (AD0-AD7) bus.
ALE (address latch enable) signal goes high. As soon as
ALE goes high, the memory latches the AD0-AD7 bus. At
the middle of the T state the ALE goes low
133
134. T2 State:
During the beginning of this state, the RD’ signal goes low
to enable memory. It is during this state, the selected memory
location is placed on D0-D7 of the Address/Data multiplexed
bus.
T3 State:
In the previous state the Opcode is placed in D0-D7 of the A/D
bus. In this state of the cycle, the Opcode of the A/D bus is
transferred to the instruction register of the microprocessor.
Now the RD’ goes high after this action and thus disables the
memory from A/D bus.
T4 State:
In this state the Opcode which was fetched from the memory
is decoded.
134
136. • These machine cycles have 3 T-states.
T1 state:
• The higher order address bus (A8-A15) and lower order address
and data multiplexed (AD0-AD7) bus. ALE goes high so that the
memory latches the (AD0-AD7) so that complete 16-bit address
are available.
The mp identifies the memory read machine cycle from the
status signals IO/M’=0, S1=1, S0=0. This condition indicates the
memory read cycle.
T2 state:
• Selected memory location is placed on the (D0-D7) of the A/D
multiplexed bus. RD’ goes LOW
T3 State:
• The data which was loaded on the previous state is transferred
to the microprocessor. In the middle of the T3 state RD’ goes
high and disables the memory read operation. The data which
was obtained from the memory is then decoded.
136
138. • These machine cycles have 3 T-states.
T1 state:
• The higher order address bus (A8-A15) and lower order address
and data multiplexed (AD0-AD7) bus. ALE goes high so that the
memory latches the (AD0-AD7) so that complete 16-bit address
are available.
The mp identifies the memory read machine cycle from the
status signals IO/M’=0, S1=0, S0=1. This condition indicates the
memory read cycle.
T2 state:
• Selected memory location is placed on the (D0-D7) of the A/D
multiplexed bus. WR’ goes LOW
T3 State:
• In the middle of the T3 state WR’ goes high and disables the
memory write operation. The data which was obtained from
the memory is then decoded.
138
144. Timing diagram for IN C0H
• Fetching the Opcode DBH from the memory
4125H.
• Read the port address C0H from 4126H.
• Read the content of port C0H and send it to
the accumulator.
• Let the content of port is 5EH.
144
145. It require 3 m/c cycles
10 T states
opcode fetch(4T)
memory read(3T)
I/O read(3T)
145
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
149. Timing diagram for MVI B, 43h
• Fetching the Opcode 06H from the memory
2000H. (OF machine cycle)
• Read (move) the data 43H from memory
2001H. (memory read)
149
156. Types of Interrupts
• Interrupts of 8085 can be classified as
– Maskable (RST 7.5, RST 6.5, RST 5.5, INTR)
– Non-maskable (TRAP)
• An interrupt is a request for attention/service
• 8085 may choose to service/not-service a
maskable interrupt
• 8085 cannot ignore a service request from a
non-maskable interrupt
156
157. Interrupt process
• 8085 is executing its main program
• an interrupt is generated by an external
device
• 8085 pauses execution of main program
• 8085 calls the Interrupt service routine
• 8085 executes the Interrupt service routine
• 8085 returns to execution of main program
(from where it was paused)
157
158. Example: Blinking LED Display with
Interrupt-based Display-Pattern change
8085
Input
Switches
LED
Display
RST 7.5
(Display-Pattern)
Interrupt Switch
Peripheral-mapped I/OInterrupt I/O
158
159. Interrupt Service Routine (ISR)
• It is a subroutine
• 8085 calls an ISR in response to an
interrupt request by an external device
• ISRs must be located in memory at pre-
determined addresses known as Interrupt
Vectors
159
160. Interrupt Vector Table of 8085
Interrupt Interrupt Vector
TRAP 0024H
RST 7.5 003CH
RST 6.5 0034H
RST 5.5 002CH
Please Note: INTR is a non-vectored interrupt
160
161. Using Vectored Interrupts of 8085
• By default, all the vectored interrupts (except
TRAP) of 8085 are disabled
• 8085 vectored interrupts are enabled with
two instructions: EI and SIM
• EI (Enable Interrupt): 1-byte instruction that
sets the Interrupt Enable flip-flop
– It is internal to the processor & can be set or reset
by using software instructions
161
162. Using Vectored Interrupts
Step-1
• Set Interrupt Enable flip-flop by using EI
instruction to enable the interrupt process
Step-2
• Use SIM (Set Interrupt Mask) instruction to
set mask for RST 7.5, 6.5 and 5.5
interrupts
162
163. SIM Instruction
• It is a 1-byte instruction
• Reads Accumulator contents
• Enables/Disables interrupts accordingly
• Used for three different functions
– Set mask for RST 7.5, 6.5, 5.5 interrupts
– Additional control for RST 7.5
– Implement serial I/O
163
164. Accumulator bit pattern for SIM
D7 D6 D5 D4 D3 D2 D1 D0
SOD SDE XXX R7.5 MSE M7.5 M6.5 M5.5
0 = Available, 1 = Masked
Mask Set Enable, 0 = bits 0-2 ignored
1 = mask is set
IF 1, RESET RST 7.5
If 1, bit 7 is output to
serial output data latch
Serial Output Data,
ignored if bit 6 = 0 164
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
165. 8085 Interrupt process for
Vectored-Interrupts
1. Enables Interrupt process by writing the EI
instruction in the main program
2. Set interrupt mask using SIM instruction
3. 8085 monitors the status of all interrupt
lines during the execution of each
instruction
165
166. 4. When 8085 detects an interrupt signal from
an external device
• It completes execution of current
instruction
• Disables the Interrupt Enable flip-flop
5. Executes a CALL to Interrupt Vector
location for that interrupt
• Before the CALL is made, 8085 stores
return address in main program on stack
8085 Interrupt process for
Vectored-Interrupts (Cont.)
166
167. 6. 8085 executes the ISR written at the
specified interrupt vector location
• ISR should include the EI instruction to
Enable Interrupt again
• At the end of ISR, RET instruction
transfers the program control back to the
main program
8085 Interrupt process for
Vectored-Interrupts (Cont.)
167
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
168. PROGRAMMING OF 8085 PROCESSOR
UNIT
2
168
Presented by
C.GOKUL,AP/EEE
Velalar College of Engg & Tech , Erode
169. UNIT 2 Syllabus
• Instruction -format and addressing
modes
• Assembly language format – Data
transfer, data manipulation& control
instructions
• Programming: Loop structure with
counting & Indexing – Look up table -
Subroutine instructions - stack.
169
171. Addressing Modes of 8085
• Format of a typical Assembly language instruction is
given below-
[Label:] Mnemonic [Operands] [;comments]
HLT
MVI A, 20H
MOV M, A ;Copy A to memory location whose
address is stored in register pair HL
LOAD: LDA 2050H ;Load A with contents of memory
location with address 2050H
READ: IN 07H ;Read data from Input port with
address 07H
171
172. • The various formats of specifying operands
are called addressing modes
• Addressing modes of 8085
1. Register Addressing
2. Immediate Addressing
3. Memory Addressing
4. Input/Output Addressing
172
173. 1. Register Addressing
• Operands are one of the internal registers of
8085
• Examples-
MOV A, B
ADD C
173
174. 2. Immediate Addressing
• Value of the operand is given in the
instruction itself
• Example-
MVI A, 20H
LXI H, 2050H
ADI 30H
SUI 10H
174
175. 3. Memory Addressing
• One of the operands is a memory location
• Depending on how address of memory
location is specified, memory addressing is of
two types
– Direct addressing
– Indirect addressing
175
176. 3(a) Direct Addressing
• 16-bit Address of the memory location is
specified in the instruction directly
• Examples-
LDA 2050H ;load A with contents of memory
location with address 2050H
STA 3050H ;store A with contents of memory
location with address 3050H
176
177. 3(b) Indirect Addressing
• A memory pointer register is used to store the
address of the memory location
• Example-
MOV M, A ;copy register A to memory location
whose address is stored in register
pair HL
30HA 20H
H
50H
L
30H2050H
177
178. 4. Input/Output Addressing
• 8-bit address of the port is directly specified in
the instruction
• Examples-
IN 07H
OUT 21H
178
180. Instruction set
An instruction is a binary pattern designed
inside a microprocessor to perform a specific
function.
A group of instruction together called as
instruction set.
Group of instruction set is called as a
program.
180
181. Classification of instruction set
According to word size or byte size it is
classified into 3 types.
1 - byte instruction
2 - byte instruction and
3 - byte instruction
181
182. 1. One-byte Instructions
• Includes Opcode and Operand in the same byte
• Examples-
Opcode Operand Binary Code Hex Code
MOV C, A 0100 1111 4FH
ADD B 1000 0000 80H
HLT 0111 0110 76H
182
185. Instruction Set of 8085
An instruction is a binary pattern designed inside a
microprocessor to perform a specific function.
The entire group of instructions that a
microprocessor supports is called Instruction
Set.
8085 has 246 instructions.
Each instruction is represented by an 8-bit binary
value.
These 8-bits of binary value is called Op-Code or
Instruction Byte.
185Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
186. Classification of Instruction Set
DataTransfer Instruction
Arithmetic Instructions
Logical Instructions
Branching Instructions
Control Instructions
186
187. 1.DataTransfer Instructions
These instructions move data between
registers, or between memory and
registers.
These instructions copy data from source
to destination(without changing the
original data ).
187
188. Opcode Operand
MOV Rd, Rs
M, Rs
Rd, M
This instruction copies the contents of the source
register into the destination register. (contents of the
source register are not altered)
If one of the operands is a memory location, its location
is specified by the contents of the HL registers.
Example: MOV B, C or MOV B, M
MOV-Copy from source to destination
188
189. A 20 B 20
A F
B 30 C
D E
H 20 L 50
A 20 B
BEFORE EXECUTION AFTER EXECUTION
MOV B,A
A F
B 30 C
D E
H 20 L 50
A F
B C
D E
H 20 L 50
A F
B C 40
D E
H 20 L 50
MOV M,B
MOV C,M
40 40
30
189
190. Opcode Operand
MVI Rd, Data
M, Data
The 8-bit data is stored in the destination register or
memory.
If the operand is a memory location, its location is
specified by the contents of the H-L registers.
Example: MVI B, 60H or MVI M, 40H
MVI-Move immediate 8-bit
190
191. A F
B C
D E
H L
A F
B 60 C
D E
H L
AFTER EXECUTIONBEFORE EXECUTION
MVI B,60H
40HL=2050
2051H
204FH 204F
2051H
MVI M,40H
BEFORE EXECUTION AFTER EXECUTION
HL=2050
191
192. LDA-Load accumulator
Opcode Operand
LDA 16-bit address
The contents of a memory location, specified by a 16-bit
address in the operand, are copied to the accumulator.
The contents of the source are not altered.
Example: LDA 2000H
192
194. Opcode Operand
LDAX B/D Register Pair
The contents of the designated register pair point to a memory
location.
This instruction copies the contents of that memory location into
the accumulator.
The contents of either the register pair or the memory location are
not altered.
Example: LDAX D
LDAX-Load accumulator indirect
194
195. A F
B C
D 20 E 30
A 80 F
B C
D 20 E 30
80 80
AFTER EXECUTIONBEFORE EXECUTION
LDAX D
2030H
2030H
195
196. Opcode Operand
LXI Reg. pair, 16-bit data
This instruction loads 16-bit data in the register pair.
Example: LXI H, 2030 H
LXI-Load register pair immediate
196Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
197. A F
B C
H L
A 80 F
B C
H 90 L 30
30
90
50
AFTER EXECUTIONBEFORE EXECUTION
LXI H,
2030
2030H
9030H
2031H
M=50
197
198. Opcode Operand
LHLD 16-bit address
This instruction copies the contents of memory location
pointed out by 16-bit address into register L.
It copies the contents of next memory location into
register H.
Example: LHLD 2030 H
LHLD-Load H and L registers direct
198
199. A F
B C
H L
A 80 F
B C
H 85 L 00
00
85
60
AFTER EXECUTIONBEFORE EXECUTION
LHLD
2030
2030H 8500H
M=60
199
200. Opcode Operand
STA 16-bit address
The contents of accumulator are copied into the memory
location specified by the operand.
Example: STA 2000H
STA-Store accumulator direct
200
202. Opcode Operand
STAX Reg. pair
The contents of accumulator are copied into the memory
location specified by the contents of the register pair.
Example: STAX B
STAX-Store accumulator indirect
202
203. B 85 C 00
A=1AH
BEFORE EXECUTION AFTER EXECUTION
STAX B
1A8500H
203
204. Opcode Operand
SHLD 16-bit address
The contents of register L are stored into memory
location specified by the 16-bit address.
The contents of register H are stored into the next
memory location.
Example: SHLD 2550H
SHLD-Store H and L registers direct
204
205. D E
H 70 L 80
BEFORE EXECUTION AFTER EXECUTION
SHLD
8500
80
70
8500H
8501H
205
206. Opcode Operand
XCHG None
The contents of register H are exchanged with the
contents of register D.
The contents of register L are exchanged with the
contents of register E.
Example: XCHG
XCHG-Exchange H and L with D and E
206
207. D 20 E 40
H 70 L 80
D 70 E 80
H 20 L 40
BEFORE EXECUTION AFTER EXECUTION
XCHG
207
208. Opcode Operand
SPHL None
This instruction loads the contents of H-L pair into SP.
Example: SPHL
SPHL-Copy H and L registers to the
stack pointer
208
209. H 25 L 00
SP
BEFORE EXECUTION
AFTER EXECUTION
SPHL
SP 2500
H 25 L 00
209
210. Opcode Operand
XTHL None
The contents of L register are exchanged with the
location pointed out by the contents of the SP.
The contents of H register are exchanged with the next
location (SP + 1).
Example: XTHL
XTHL-Exchange H and L with top of
stack
210
211. H 30 L 40
SP 2700
BEFORE EXECUTION
50
60
H
60
L
50
SP 2700
40
30
AFTER EXECUTION
XTHL
2700H
2701H
2702H
2700H
2701H
2702H
L=SP
H=(SP+1)
211
212. Opcode Operand Description
PCHL None Load program counter with H-
L contents
The contents of registers H and L are copied into the
program counter (PC).
The contents of H are placed as the high-order byte and
the contents of L as the low-order byte.
Example: PCHL
212Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
213. Opcode Operand
PUSH Reg. pair
The contents of register pair are copied onto stack.
SP is decremented and the contents of high-order
registers (B, D, H,A) are copied into stack.
SP is again decremented and the contents of low-order
registers (C, E, L, Flags) are copied into stack.
Example: PUSH B
PUSH-Push register pair onto stack
213
215. Opcode Operand
POP Reg. pair
The contents of top of stack are copied into register pair.
The contents of location pointed out by SP are copied to the
low-order register (C, E, L, Flags).
SP is incremented and the contents of location are
copied to the high-order register (B, D, H,A).
Example: POP H
POP- Pop stack to register pair
215
217. Opcode Operand
IN 8-bit port address
The contents of I/O port are copied into accumulator.
Example: IN 8C H
IN- Copy data to accumulator from a
port with 8-bit address
217
218. 10 A
10 A 10
BEFORE EXECUTION
AFTER EXECUTION
IN 80H
PORT
80H
PORT
80H
218
219. Opcode Operand
OUT 8-bit port address
The contents of accumulator are copied into the I/O
port.
Example: OUT 78H
OUT- Copy data from accumulator to a
port with 8-bit address
219
220. 10 A 40
40 A 40
BEFORE EXECUTION
AFTER EXECUTION
OUT 50H
PORT
50H
PORT
50H
220
221. 2.Arithmetic Instructions
These instructions perform the
operations like:
◦ Addition
◦ Subtract
◦ Increment
◦ Decrement
221Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
222. Addition
Any 8-bit number, or the contents of register, or
the contents of memory location can be added to
the contents of accumulator.
The result (sum) is stored in the accumulator.
No two other 8-bit registers can be added
directly.
Example: The contents of register B cannot be
added directly to the contents of register C.
222
223. Opcode Operand Description
ADD R
M
Add register or memory to
accumulator
The contents of register or memory are added to the
contents of accumulator.
The result is stored in accumulator.
If the operand is memory location, its address is specified by
H-L pair.
Example: ADD B or ADD M
ADD
223
224. B C 05
D E
H L
B C 05
D E
H L
AFTER EXECUTIONBEFORE EXECUTION
B C
D E
H 20 L 50
B C
D E
H 20 L 50
AFTER EXECUTION
BEFORE EXECUTION
A 09A 04
ADD C
A=A+C
ADD M
A=A+M
10
10
2050 2050
A 04
A 14
04+05=09
04+10=14 224
225. Opcode Operand Description
ADC R
M
Add register or memory to
accumulator with carry
The contents of register or memory and Carry Flag (CY) are added to the
contents of accumulator.
The result is stored in accumulator.
If the operand is memory location, its address is specified by H-L pair.
All flags are modified to reflect the result of the addition.
Example: ADC B or ADC M
ADC
225
226. B C 05
D E
H L
A 50
B C 20
D E
H L
A 56
AFTER EXECUTIONBEFORE EXECUTION
ADC C
A=A+C+CY
CY 01
CY 1
A 06 A 37
H 20 L 50
H 20 L 50
ADC M
A=A+M+CY
AFTER EXECUTIONBEFORE EXECUTION
30 302050H 2050H
06+1+30=37
50+05+01=56
226
227. Opcode Operand Description
ADI 8-bit data Add immediate to accumulator
The 8-bit data is added to the contents of accumulator.
The result is stored in accumulator.
All flags are modified to reflect the result of the addition.
Example: ADI 45 H
ADI
227
229. Opcode Operand Description
ACI 8-bit data Add immediate to
accumulator with carry
The 8-bit data and the Carry Flag (CY) are added to
the contents of accumulator.
The result is stored in accumulator.
All flags are modified to reflect the result of the
addition.
Example: ACI 45 H
ACI
229
230. CY 1
A 05
AFTER EXECUTIONBEFORE EXECUTION
ACI 20H
A=A+DATA
(8)+CY
A 26
05+20+1=26 230
231. Opcode Operand Description
DAD Reg. pair Add register pair to H-L pair
The 16-bit contents of the register pair are added to
the contents of H-L pair.
The result is stored in H-L pair.
If the result is larger than 16 bits, then CY is set.
No other flags are changed.
Example: DAD B or DAD D
DAD
231
232. D 12 E 34
H 23 L 45
D 12 E 34
H 35 L 79
BEFORE EXECUTION AFTER EXECUTION
DAD D
DAD D HL=HL+DE
DAD B HL=HL+BC
1234
2345 +
-------
3579
232
233. Subtraction
Any 8-bit number, or the contents of register, or
the contents of memory location can be
subtracted from the contents of accumulator.
The result is stored in the accumulator.
Subtraction is performed in 2’s complement form.
If the result is negative, it is stored in 2’s
complement form.
No two other 8-bit registers can be subtracted
directly.
233
234. Opcode Operand Description
SUB R
M
Subtract register or memory
from accumulator
The contents of the register or memory location are
subtracted from the contents of the accumulator.
The result is stored in accumulator.
If the operand is memory location, its address is specified by
H-L pair.
All flags are modified to reflect the result of subtraction.
Example: SUB B or SUB M
SUB
234
235. B C 04
D E
H L
B C 04
D E
H L
AFTER EXECUTIONBEFORE EXECUTION
B C
D E
H 20 L 50
B C
D E
H 20 L 50
AFTER EXECUTION
BEFORE EXECUTION
A 05A 09
SUB C
A=A-C
SUB M
A=A-M
10
10
2050 2050
A 14
A 04
09-04=05
14-10=04 235
236. Opcode Operand Description
SBB R
M
Subtract register or memory
from accumulator with borrow
The contents of the register or memory location and Borrow Flag (i.e. CY)
are subtracted from the contents of the accumulator.
The result is stored in accumulator.
If the operand is memory location, its address is specified by H-L pair.
All flags are modified to reflect the result of subtraction.
Example: SBB B or SBB M
SBB
236
237. B C 05
D E
H L
A 08
B C 05
D E
H L
A 02
AFTER EXECUTIONBEFORE EXECUTION
SBB C
A=A-C-CY
CY 01
CY 1
A 06 A 03
H 20 L 50
H 20 L 50
SBB M
A=A-M-CY
AFTER EXECUTIONBEFORE EXECUTION
02 022050H 2050H
08-05-01=02
06-02-1=03
237
238. Opcode Operand Description
SUI 8-bit data Subtract immediate from
accumulator
The 8-bit data is subtracted from the contents of the
accumulator.
The result is stored in accumulator.
All flags are modified to reflect the result of subtraction.
Example: SUI 05H
SUI
238
240. Opcode Operand Description
SBI 8-bit data Subtract immediate from
accumulator with borrow
The 8-bit data and the Borrow Flag (i.e. CY) is subtracted
from the contents of the accumulator.
The result is stored in accumulator.
All flags are modified to reflect the result of subtraction.
Example: SBI 45 H
SBI
240
241. CY 1
A 25
AFTER EXECUTIONBEFORE EXECUTION
SBI 20H
A=A-DATA
(8)-CY
A 04
25-20-01=04
241
242. Increment / Decrement
The 8-bit contents of a register or a
memory location can be incremented or
decremented by 1.
The 16-bit contents of a register pair can
be incremented or decremented by 1.
Increment or decrement can be
performed on any register or a memory
location.
242Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
243. Opcode Operand Description
INR R
M
Increment register or
memory by 1
The contents of register or memory location are incremented
by 1.
The result is stored in the same place.
If the operand is a memory location, its address is specified by
the contents of H-L pair.
Example: INR B or INR M
INR
243
244. B 10 C
D E
H L
A
B 11 C
D E
H L
A
AFTER EXECUTIONBEFORE EXECUTION
H
20
L
50
H
20
L
5010 112050H 2050H
AFTER EXECUTIONBEFORE EXECUTION
INR M
M=M+1
B 10 C
D E
H L
A
BEFORE EXECUTION
INR B
R=R+1
10+1=11
10+1=11 244
245. Opcode Operand Description
INX R Increment register pair by 1
The contents of register pair are incremented by 1.
The result is stored in the same place.
Example: INX H or INX B or INX D
INX
245
246. B C
D E
H 10 L 20
B C
D E
H 10 L 21
AFTER EXECUTIONBEFORE EXECUTION
SPSP
INX H
RP=RP+1
1020+1=1021
246
247. Opcode Operand Description
DCR R
M
Decrement register or
memory by 1
The contents of register or memory location are decremented
by 1.
The result is stored in the same place.
If the operand is a memory location, its address is specified by
the contents of H-L pair.
Example: DCR B or DCR M
DCR
247
248. B C
D E 19
H L
A
AFTER EXECUTION
B C
D E 20
H L
A
BEFORE EXECUTION
DCR E
R=R-1
H
20
L
50
H
20
L
5021 202050H
AFTER EXECUTIONBEFORE EXECUTION
DCR M
M=M-1
2050H
21-1=20
20-1=19
248
249. Opcode Operand Description
DCX R Decrement register pair by 1
The contents of register pair are decremented by 1.
The result is stored in the same place.
Example: DCX H or DCX B or DCX D
DCX
249
250. B C
D E
H 10 L 21
B C
D E
H 10 L 20
AFTER EXECUTIONBEFORE EXECUTION
SPSP
DCX H
RP=RP-1
250
251. 3.Logical Instructions
These instructions perform logical operations on
data stored in registers, memory and status flags.
The logical operations are:
◦ AND
◦ OR
◦ XOR
◦ Rotate
◦ Compare
◦ Complement
251
252. AND, OR, XOR
Any 8-bit data, or the contents of register,
or memory location can logically have
◦ AND operation
◦ OR operation
◦ XOR operation
with the contents of accumulator.
The result is stored in accumulator.
252
253. Opcode Operand Description
ANA R
M
Logical AND register or
memory with accumulator
The contents of the accumulator are logically ANDed with the contents of
register or memory.
The result is placed in the accumulator.
If the operand is a memory location, its address is specified by the contents
of H-L pair.
S, Z, P are modified to reflect the result of the operation.
CY is reset and AC is set.
Example: ANA B or ANA M.
253
254. B 10 C
D E
H L
A
B 0F C
D E
H L
A 0A
AFTER EXECUTION
ANA B
A=A and R
B 0F C
D E
H L
A AA
BEFORE EXECUTION
CY AC CY 0 AC 1
AFTER EXECUTIONBEFORE EXECUTION
CY AC CY 0 AC 1
A 11A 55
H 20 L 50 H 20 L 50
B3 B3
2050H
ANA M
A=A and M
2050H
1010 1010=AAH
0000 1111=0FH
0000 1010=0AH
0101 0101=55H
1011 0011=B3H
0001 0001=11H
254
255. Opcode Operand Description
ANI 8-bit data Logical AND immediate with
accumulator
The contents of the accumulator are logically ANDed with the
8-bit data.
The result is placed in the accumulator.
S, Z, P are modified to reflect the result.
CY is reset,AC is set.
Example: ANI 86H.
255
256. CY AC
A B3
AFTER EXECUTIONBEFORE EXECUTION
CY
0
AC 1
A 33
ANI 3FH
A=A and DATA(8)
1011 0011=B3H
0011 1111=3FH
0011 0011=33H
256
257. Opcode Operand Description
ORA R
M
Logical OR register or memory with
accumulator
The contents of the accumulator are logically ORed with the contents of the
register or memory.
The result is placed in the accumulator.
If the operand is a memory location, its address is specified by the contents of H-L
pair.
S, Z, P are modified to reflect the result.
CY and AC are reset.
Example: ORA B or ORA M.
257
258. AFTER EXECUTIONBEFORE EXECUTION
CY AC
ORA B
A=A or R
1010 1010=AAH
0001 0010=12H
1011 1010=BAH
B 12 C
D E
H L
A AA
B 12 C
D E
H L
A BA
CY 0 AC 0
258
259. AFTER EXECUTIONBEFORE EXECUTION
CY AC
ORA M
A=A or M
0101 0101=55H
1011 0011=B3H
1111 0111=F7H
H 20 L 50
A 55 A F7
CY
0
AC 0
H 20 L 50
B3 B3
2050H 2050H
259
260. Opcode Operand Description
ORI 8-bit data Logical OR immediate with
accumulator
The contents of the accumulator are logically ORed with the
8-bit data.
The result is placed in the accumulator.
S, Z, P are modified to reflect the result.
CY and AC are reset.
Example: ORI 86H.
260
261. CY AC
A B3
AFTER EXECUTIONBEFORE EXECUTION
CY
0
AC
0
A BB
ORI 08H
A=A or DATA(8)
1011 0011=B3H
0000 1000=08H
1011 1011=BBH
261
262. Opcode Operand Description
XRA R
M
Logical XOR register or
memory with accumulator
The contents of the accumulator are XORed with the contents of
the register or memory.
The result is placed in the accumulator.
If the operand is a memory location, its address is specified by the
contents of H-L pair.
S, Z, P are modified to reflect the result of the operation.
CY and AC are reset.
Example: XRA B or XRA M.
262
263. B 10 C
D E
H L
A
B C 2D
D E
H L
A 87
AFTER EXECUTION
XRA C
A=A xor R
B C 2D
D E
H L
A AA
BEFORE EXECUTION
CY AC CY 0 AC 0
1010 1010=AAH
0010 1101=2DH
1000 0111=87H
263
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
264. H 20 L 50
A 55
AFTER EXECUTION
XRA M
A=A xor M
BEFORE EXECUTION
CY AC CY 0 AC 0
0101 0101=55H
1011 0011=B3H
1110 0110=E6H
H 20 L 50
A E6
B3 B3
2050H 2050H
264
265. Opcode Operand Description
XRI 8-bit data XOR immediate with
accumulator
The contents of the accumulator are XORed with the 8-
bit data.
The result is placed in the accumulator.
S, Z, P are modified to reflect the result.
CY and AC are reset.
Example: XRI 86H.
265
266. CY AC
A B3
AFTER EXECUTIONBEFORE EXECUTION
CY
0
AC
0
A 8A
XRI 39H
A=A xor DATA(8)
1011 0011=B3H
0011 1001=39H
1000 1010=8AH
266
267. Compare
Any 8-bit data, or the contents of register,
or memory location can be compares for:
◦ Equality
◦ Greater Than
◦ LessThan
with the contents of accumulator.
The result is reflected in status flags.
267
268. Opcode Operand Description
CMP R
M
Compare register or
memory with accumulator
The contents of the operand (register or memory) are
compared with the contents of the accumulator.
Both contents are preserved .
268
269. B 10 C
D E
H L
A
B C
D 20 E
H L
A 10
AFTER EXECUTION
CMP D
A-R
B C
D 20 E
H L
A 10
BEFORE EXECUTION
CY Z CY 01 Z 0
AFTER EXECUTIONBEFORE EXECUTION
CY Z CY 0
ZF 1
A B8A B8
H 20 L 50 H 20 L 50
B8 B8
2050H
CMP M
A-M
2050H
A>R: CY=0
A=R: ZF=1
A<R: CY=1
A>M: CY=0
A=M: ZF=1
A<M: CY=1
10<20:CY=01
B8=B8 :ZF=01
269
270. Opcode Operand Description
CPI 8-bit data Compare immediate with
accumulator
The 8-bit data is compared with the contents of
accumulator.
The values being compared remain unchanged.
270
271. CY Z
A BA
AFTER EXECUTIONBEFORE EXECUTION
CY
0
AC
0
A BA
CPI 30H
A-DATA
A>DATA: CY=0
A=DATA: ZF=1
A<DATA: CY=1
BA>30 : CY=00 271
272. Rotate
Each bit in the accumulator can be shifted
either left or right to the next position.
272
273. Opcode Operand Description
RLC None Rotate accumulator left
Each binary bit of the accumulator is rotated left by one
position.
Bit D7 is placed in the position of D0 as well as in the Carry
flag.
CY is modified according to bit D7.
S, Z, P,AC are not affected.
Example: RLC.
273
275. Opcode Operand Description
RRC None Rotate accumulator right
Each binary bit of the accumulator is rotated right by one
position.
Bit D0 is placed in the position of D7 as well as in the Carry
flag.
CY is modified according to bit D0.
S, Z, P,AC are not affected.
Example: RRC.
275
277. Opcode Operand Description
RAL None Rotate accumulator left
through carry
Each binary bit of the accumulator is rotated left by one
position through the Carry flag.
Bit D7 is placed in the Carry flag, and the Carry flag is placed
in the least significant position D0.
CY is modified according to bit D7.
S, Z, P,AC are not affected.
Example: RAL.
277
279. Opcode Operand Description
RAR None Rotate accumulator right
through carry
Each binary bit of the accumulator is rotated right by one
position through the Carry flag.
Bit D0 is placed in the Carry flag, and the Carry flag is placed
in the most significant position D7.
CY is modified according to bit D0.
S, Z, P,AC are not affected.
Example: RAR.
279Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
281. Complement
The contents of accumulator can be
complemented.
Each 0 is replaced by 1 and each 1 is
replaced by 0.
281
282. Opcode Operand Description
CMA None Complement accumulator
The contents of the accumulator are complemented.
No flags are affected.
Example: CMA. A=A’
A 00 A FF
BEFORE EXECUTION AFTER EXECUTION
282
283. Opcode Operand Description
CMC None Complement carry
The Carry flag is complemented.
No other flags are affected.
Example: CMC => c=c’
BEFORE EXECUTION
AFTER EXECUTION
C 00 C FF
283
284. Opcode Operand Description
STC None Set carry
The Carry flag is set to 1.
No other flags are affected.
Example: STC CF=1
S-set (1) C-clear (0)
284
285. 4.Branching Instructions
The branch group instructions
allows the microprocessor to change
the sequence of program either
conditionally or under certain test
conditions.The group includes,
(1) Jump instructions,
(2) Call and Return instructions,
(3) Restart instructions,
285
286. Opcode Operand Description
JMP 16-bit
address
Jump unconditionally
The program sequence is transferred to the memory
location specified by the 16-bit address given in the
operand.
Example: JMP 2034 H.
286
287. Opcode Operand Description
Jx 16-bit
address
Jump conditionally
The program sequence is transferred to the memory
location specified by the 16-bit address given in the
operand based on the specified flag of the PSW.
Example: JZ 2034 H.
287
288. Jump Conditionally
Opcode Description Status Flags
JC Jump if Carry CY = 1
JNC Jump if No Carry CY = 0
JZ Jump if Zero Z = 1
JNZ Jump if No Zero Z = 0
JPE Jump if Parity Even P = 1
JPO Jump if Parity Odd P = 0
A-Above , B-Below , C-Carry , Z-Zero , P-Parity
288
289. Opcode Operand Description
CALL 16-bit
address
Call unconditionally
The program sequence is transferred to the memory
location specified by the 16-bit address given in the
operand.
Before the transfer, the address of the next instruction after
CALL (the contents of the program counter) is pushed onto
the stack.
Example: CALL 2034 H.
289
290. Call Conditionally
Opcode Description Status Flags
CC Call if Carry CY = 1
CNC Call if No Carry CY = 0
CP Call if Positive S = 0
CM Call if Minus S = 1
CZ Call if Zero Z = 1
CNZ Call if No Zero Z = 0
CPE Call if Parity Even P = 1
CPO Call if Parity Odd P = 0
290
291. Opcode Operand Description
RET None Return unconditionally
The program sequence is transferred from the subroutine
to the calling program.
The two bytes from the top of the stack are copied into
the program counter, and program execution begins at
the new address.
Example: RET.
291
292. Return Conditionally
Opcode Description Status Flags
RC Return if Carry CY = 1
RNC Return if No Carry CY = 0
RP Return if Positive S = 0
RM Return if Minus S = 1
RZ Return if Zero Z = 1
RNZ Return if No Zero Z = 0
RPE Return if Parity Even P = 1
RPO Return if Parity Odd P = 0
292
293. Opcode Operand Description
RST 0 – 7 Restart (Software Interrupts)
The RST instruction jumps the control to one of eight
memory locations depending upon the number.
These are used as software instructions in a program to
transfer program execution to one of the eight locations.
Example: RST 1 or RST 2 ….
293
296. Opcode Operand Description
NOP None No operation
No operation is performed.
The instruction is fetched and decoded but no operation
is executed.
Example: NOP
296
297. Opcode Operand Description
HLT None Halt
The CPU finishes executing the current instruction and
halts any further execution.
An interrupt or reset is necessary to exit from the halt
state.
Example: HLT
297
298. Opcode Operand Description
DI None Disable interrupt
The interrupt enable flip-flop is reset and all the
interrupts except the TRAP are disabled.
No flags are affected.
Example: DI
298Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
299. Opcode Operand Description
EI None Enable interrupt
The interrupt enable flip-flop is set and all interrupts
are enabled.
No flags are affected.
This instruction is necessary to re-enable the
interrupts (except TRAP).
Example: EI
299
300. Opcode Operand Description
RIM None Read Interrupt Mask
This is a multipurpose instruction used to read the status
of interrupts 7.5, 6.5, 5.5 and read serial data input bit.
The instruction loads eight bits in the accumulator with
the following interpretations.
Example: RIM
300
302. Opcode Operand Description
SIM None Set Interrupt Mask
This is a multipurpose instruction and used to implement
the 8085 interrupts 7.5, 6.5, 5.5, and serial data output.
The instruction interprets the accumulator contents as
follows.
Example: SIM
302
305. Example Data Transfer (Copy)
Operations / Instructions
1. Load a 8-bit number 4F in
register B
2. Copy from Register B to
Register A
3. Load a 16-bit number
2050 in Register pair HL
4. Copy from Register B to
Memory Address 2050
5. Copy between Input /
Output Port and
Accumulator
MVI B, 4FH
MOV A,B
LXI H, 2050H
MOV M,B
OUT 01H
IN 07H
305
306. Example Arithmetic
Operations / Instructions
1. Add a 8-bit number 32H to
Accumulator
2. Add contents of Register B to
Accumulator
3. Subtract a 8-bit number 32H
from Accumulator
4. Subtract contents of Register
C from Accumulator
5. Increment the contents of
Register D by 1
6. Decrement the contents of
Register E by 1
ADI 32H
ADD B
SUI 32H
SUB C
INR D
DCR E
306
307. Example Logical & Bit Manipulation
Operations / Instructions
1. Logically AND Register H
with Accumulator
2. Logically OR Register L with
Accumulator
3. Logically XOR Register B
with Accumulator
4. Compare contents of
Register C with Accumulator
5. Complement Accumulator
6. Rotate Accumulator Left
ANA H
ORA L
XRA B
CMP C
CMA
RAL
307
308. Example Branching
Operations / Instructions
1. Jump to a 16-bit Address
2080H if Carry flag is SET
2. Unconditional Jump
3. Call a subroutine with its 16-bit
Address
4. Return back from the Call
5. Call a subroutine with its 16-bit
Address if Carry flag is RESET
6. Return if Zero flag is SET
JC 2080H
JMP 2050H
CALL 3050H
RET
CNC 3050H
RZ
308
309. Writing a Assembly Language Program
• Steps to write a program
–Analyze the problem
–Develop program Logic
–Write an Algorithm
–Make a Flowchart
–Write program Instructions using
Assembly language of 8085
309
310. Program 8085 in Assembly language to add two 8-
bit numbers and store 8-bit result in register C.
1. Analyze the problem
– Addition of two 8-bit numbers to be done
2. Program Logic
– Add two numbers
– Store result in register C
– Example
10011001 (99H) A
+00111001 (39H) D
11010010 (D2H) C
310
311. 1. Get two numbers
2. Add them
3. Store result
4. Stop
• Load 1st no. in register D
• Load 2nd no. in register E
3. Algorithm
Translation to 8085
operations
• Copy register D to A
• Add register E to A
• Copy A to register C
• Stop processing
311
312. 4. Make a Flowchart
Start
Load Registers D, E
Copy D to A
Add A and E
Copy A to C
Stop
• Load 1st no. in register D
• Load 2nd no. in register E
• Copy register D to A
• Add register E to A
• Copy A to register C
• Stop processing
312
313. 5. Assembly Language Program
1. Get two numbers
2. Add them
3. Store result
4. Stop
a) Load 1st no. in register D
b) Load 2nd no. in register E
a) Copy register D to A
b) Add register E to A
a) Copy A to register C
a) Stop processing
MVI D, 2H
MVI E, 3H
MOV A, D
ADD E
MOV C, A
HLT
313
314. Program 8085 in Assembly language to add two 8-
bit numbers. Result can be more than 8-bits.
1. Analyze the problem
– Result of addition of two 8-bit numbers can
be 9-bit
– Example
10011001 (99H) A
+10011001 (99H) B
100110010 (132H)
– The 9th bit in the result is called CARRY bit.
314
315. 0
• How 8085 does it?
– Adds register A and B
– Stores 8-bit result in A
– SETS carry flag (CY) to indicate carry bit
10011001
10011001
A
B
+
99H
99H
10011001 A1
CY
00110010 99H32H
315
316. • Storing result in Register memory
10011001
A
32H1
CY
Register CRegister B
Step-1 Copy A to C
Step-2
a) Clear register B
b) Increment B by 1
316
317. 2. Program Logic
1. Add two numbers
2. Copy 8-bit result in A to C
3. If CARRY is generated
– Handle it
4. Result is in register pair BC
317
318. 1. Load two numbers
in registers D, E
2. Add them
3. Store 8 bit result in C
4. Check CARRY flag
5. If CARRY flag is SET
• Store CARRY in
register B
6. Stop
• Load registers D, E
3. Algorithm
Translation to 8085
operations
• Copy register D to A
• Add register E to A
• Copy A to register C
• Stop processing
• Use Conditional
Jump instructions
• Clear register B
• Increment B
• Copy A to register C
318
319. 4. Make a Flowchart
Start
Load Registers D, E
Copy D to A
Add A and E
Copy A to C
Stop
If
CARRY
NOT SET
Clear B
Increment B
False
True
319
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
320. 5. Assembly Language Program
MVI D, 2H
MVI E, 3H
MOV A, D
ADD E
MOV C, A
HLT
• Load registers D, E
• Copy register D to A
• Add register E to A
• Copy A to register C
• Stop processing
• Use Conditional
Jump instructions
• Clear register B
• Increment B
• Copy A to register C
JNC END
MVI B, 0H
INR B
END:
320
337. What is Microcontroller?
Micro Controller
337
Very Small A mechanism that controls
the operation of a machine
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
338. CPU for Computers
No RAM, ROM, I/O on CPU chip itself
Example: Intel's x86, Motorola’s 680x0
338
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
341. Microprocessor
CPU is stand-alone, RAM,
ROM, I/O, timer are
separate
Designer can decide on the
amount of ROM, RAM and
I/O ports.
Expansive
General-purpose
Microcontroller
CPU, RAM, ROM, I/O and timer
are all on a single chip
Fix amount of on-chip ROM, RAM,
I/O ports
For applications in which cost,
power and space are critical
Not Expansive
Single-purpose
341
342. Home
Appliances, intercom, telephones, security systems, garage door
openers, answering machines, fax machines, home computers,
TVs, cable TV tuner, VCR, camcorder, remote controls, video
games, cellular phones, musical instruments, sewing machines,
lighting control, paging, camera, pinball machines, toys, exercise
equipment etc.
Office
Telephones, computers, security systems, fax machines,
microwave, copier, laser printer, color printer, paging etc.
Auto
Trip computer, engine control, air bag, ABS, instrumentation,
security system, transmission control, entertainment, climate
control, cellular phone, keyless entry
342
345. UNIT 3 Syllabus
• Architecture of 8051
• Special Function Registers(SFRs)
• I/O Pins Ports and Circuits {Pin Diagram}
• Instruction set
• Addressing modes
• Assembly language programming
345
346. The 8051 is a subset of the 8052
The 8031 is a ROM-less 8051
Add external ROM to it
You lose two ports, and leave only 2 ports for I/O
operations
346
348. Intel introduced 8051, developed in the year
1981.
The 8051 is an 8-bit controller.
D0-D7 DATA LINES
A0-A15 ADDRESS LINES
348
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
354. EA/VPP
• EA, “external access’’
• EA = 0, 8051 microcontroller access from
external program memory (ROM) only.
• EA = 1, then it access internal and external
program memories (ROMS).
354
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
355. I/O Port Pins
• The four 8-bit I/O ports
Port 0 { P0.0-P0.7 } – 8 pins
Port 1 { P1.0-P1.7 } – 8 pins
Port 2 { P2.0-P2.7 } – 8 pins
Port 3 { P3.0-P3.7 } – 8 pins
355
356. Port 3
• Port 3 can be used as input or output.
• Port 3 has the additional function of
providing some extremely important
signals
356
357. Pin Description Summary
PIN TYPE NAME AND FUNCTION
Vss I Ground: 0 V reference.
Vcc I Power Supply + 5V.
P0.0 - P0.7
I/O Port 0: Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and data
memory.
P1.0 - P1.7
I/O Port 1: Port 1 is an 8-bit bi-directional simple I/O port.
P2.0 - P2.7
I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits the
high order address byte
P3.0 - P3.7
I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also
serves special features as explained.
357
358. Pin Description Summary
PIN TYPE NAME AND FUNCTION
RST I Reset: resets the device.
ALE O Address Latch Enable:
When ALE=0, it provides data D0-D7
When ALE=1, it has address A0-A7
PSEN* O Program Store Enable:
For External Code Memory, PSEN = 0
For External Data Memory, PSEN = 1
EA*/VPP I External Access Enable/Programming Supply Voltage:
EA = 0, 8051 microcontroller access from external
program memory (ROM) only.
EA = 1, then it access internal and external program
memories (ROMS).
358
362. Program Counter(PC) : The program
counter always points to the address of the
next instruction to be executed.
Stack Pointer Register (SP) : It is an 8-bit
register which stores the address of the
stack top.
ALU: perform arithmetic & logical operations
Flags : Carry(C),Auxiliary Carry(AC),
Overflow(O) & Parity(P)
362
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
363. Timing & Control: Timing and control unit
synchronises all microcontroller operations
with clock & generates control signals.
DPTR: (Data Pointer) - 16 bit
DPH-Data Pointer High – 8 bit
DPL-Data Pointer Low – 8 bit
DPTR Register is usually used for storing data and
intermediate results.
363
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
369. Program Status Word [PSW]
C AC F0 RS1 RS0 OV F1 P
Register Bank Select
Carry
Auxiliary Carry
User Flag 0
Parity
User Flag 1
Overflow
369
00-Bank 0
01-Bank 1
10-Bank 2
11-Bank 3
370. Data Pointer Register (DPTR)
It consists of two separate registers:
DPH (Data Pointer High) &
DPL (Data Pointer Low).
370
371. Stack Pointer (SP) Register
371
P0, P1, P2, P3 – Input / Output Registers
8 bit
8 bit
8 bit
8 bit
8 bit
373. INTERRUPTS
• An interrupt is an external or internal event that
interrupts the microcontroller to inform it that a device
needs its service
• A single microcontroller can serve several devices by two
ways:
1. Interrupt
2. Polling
373
374. Interrupt
– Upon receiving an interrupt signal, the
microcontroller interrupts whatever it is doing
and serves the device.
– The program which is associated with the
interrupt is called the interrupt service routine
(ISR) .
374Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
375. Steps in Executing an Interrupt
1. It finishes the instruction it is executing and saves the address of
the next instruction (PC) on the stack.
2. It also saves the current status of all the interrupts internally (i.e:
not on the stack).
3. It jumps to a fixed location in memory, called the interrupt
vector table, that holds the address of the ISR.
4. The microcontroller gets the address of the ISR from the
interrupt vector table and jumps to it.
5. It starts to execute the interrupt service subroutine until it
reaches the last instruction of the subroutine which is RETI
(return from interrupt).
6. Upon executing the RETI instruction, the microcontroller returns
to the place where it was interrupted.
375
376. Steps in executing an interrupt
• Finish current instruction and saves the PC on stack.
• Jumps to a fixed location in memory depend on type
of interrupt
• Starts to execute the interrupt service routine until
RETI (return from interrupt)
• Upon executing the RETI the microcontroller returns
to the place where it was interrupted. Get pop PC
from stack
377. Interrupt Sources
• Original 8051 has 6 sources of interrupts
– Reset (RST)
– Timer 0 overflow (TF0)
– Timer 1 overflow (TF1)
– External Interrupt 0 (INT0)
– External Interrupt 1 (INT1)
– Serial Port events (RI+TI)
{Reception/Transmission of Serial Character}
379. 8051 Interrupt related Registers
• The various registers associated with the use of
interrupts are:
– TCON - Edge and Type bits for External Interrupts 0/1
– SCON - RI and TI interrupt flags for RS232 {SERIAL
COMMUNICATION}
– IE - interrupt Enable
– IP - Interrupts priority
379
380. Enabling and Disabling an Interrupt
• The register called IE (interrupt enable) that is
responsible for enabling (unmasking) and disabling
(masking) the interrupts.
380
381. Interrupt Enable (IE) Register
• EA : Global enable/disable.
• --- : Reserved for additional interrupt hardware.
• ES : Enable Serial port interrupt.
• ET1 : Enable Timer 1 control bit.
• EX1 : Enable External 1 interrupt.
• ET0 : Enable Timer 0 control bit.
• EX0 : Enable External 0 interrupt.
MOV IE,#08h
or
SETB ET1
--
381
389. Data Transfers
Synchronous ----- Usually occur when
peripherals are located within the same
computer as the CPU. Close proximity
allows all state bits change at same
time on a common clock.
Asynchronous ----- Do not require that
the source and destination use the
same system clock.
389
390. MEMORY DEVICES I/O DEVICES
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode
390
391. interface memory (RAM, ROM, EPROM'...)
or I/O devices to 8086 microprocessor.
Several memory chips or I/O devices can
connected to a microprocessor. An address
decoding circuit is used to select the
required I/O device or a memory chip.
391
392. IO mapped IO V/s Memory Mapped
IO
Memory Mapped IO
IO is treated as memory.
16-bit addressing.
More Decoder Hardware.
Can address 216=64k
locations.
Less memory is available.
IO Mapped IO
IO is treated IO.
8- bit addressing.
Less Decoder
Hardware.
Can address 28=256
locations.
Whole memory address
space is available.
392
393. Memory Mapped IO
• Memory Instructions are
used.
• Memory control signals
are used.
• Arithmetic and logic
operations can be
performed on data.
• Data transfer b/w register
and IO.
IO Mapped IO
• Special Instructions are
used like IN, OUT.
• Special control signals
are used.
• Arithmetic and logic
operations can not be
performed on data.
• Data transfer b/w
accumulator and IO.
393
395. 8255 PPI
• The 8255 chip is also called as Programmable
Peripheral Interface.
• The Intel’s 8255 is designed for use with Intel’s
8-bit, 16-bit and higher capability
microprocessors
• The 8255 is a 40 pin integrated circuit (IC),
designed to perform a variety of interface
functions in a computer environment.
• It is flexible and economical.
395
398. 8255 PIO/PPI
It has 24 input/output lines which may be
individually programmed.
2 groups of I/O pins are named as
Group A (Port-A & Port C Upper)
Group B (Port-B & Port C Lower)
3 ports(each port has 8 bit)
Port A lines are identified by symbols PA0-PA7
Port B lines are identified by symbols PB0-PB7
Port C lines are identified by PC0-PC7 , PC3-PC0
ie: PORT C UPPER(PC7-PC4) , PORT C LOWER(PC3-PC0)
398
399. D0 - D7: data input/output lines for the
device. All information read from and
written to the 8255 occurs via these 8 data
lines.
CS (Chip Select). If this line is a logical 0, the
microprocessor can read and write to the
8255.
RESET : The 8255 is placed into its reset
state if this input line is a logical 1
399
400. • RD : This is the input line driven by the
microprocessor and should be low to
indicate read operation to 8255.
• WR : This is an input line driven by the
microprocessor. A low on this line
indicates write operation.
• A1-A0 : These are the address input lines
and are driven by the microprocessor.
400
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
401. Control Logic
CS signal is the master Chip Select
A0 and A1 specify one of the two I/O Ports
CS A1 A0 Selected
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control
Register
1 X X 8255 is not
selected
401
403. Block Diagram of 8255
(Architecture)
It has a 40 pins of 4 parts.
1. Data bus buffer
2. Read/Write control logic
3. Group A and Group B controls
4. Port A, B and C
403
404. 1. Data bus buffer
This is a tristate bidirectional buffer used
to interface the 8255 to system data bus.
Data is transmitted or received by the
buffer on execution of input or output
instruction by the CPU.
404
405. 2. Read/Write control logic
This unit accepts control signals ( RD, WR ) and
also inputs from address bus and issues
commands to individual group of control blocks
( Group A, Group B).
It has the following pins.
CS , RD , WR , RESET , A1 , A0
405
406. 3. Group A and Group B controls
• These block receive control from the CPU
and issues commands to their respective
ports.
Group A - PA and PCU ( PC7 –PC4)
Group B – PB and PCL ( PC3 –PC0)
a) Port A: This has an 8 bit latched/buffered
O/P and 8 bit input latch. It can be
programmed in 3 modes – mode 0, mode 1,
mode 2.
406
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
407. b) Port B: It can be programmed in mode 0,
mode1
c) Port C : It can be programmed in mode 0
407
411. B3 B2 B1
Bit/pin of port C
selected
0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7
Concerned only with the 8-bits of Port C.
Set or Reset by control word
Ports A and B are not affected
411
412. a) Mode 0 (Simple Input or Output):
• Ports A and B are used as Simple I/O
Ports
• Port C as two 4-bit ports
• Features
– Outputs are latched
– Inputs are not latched
– Ports do not have handshake or
interrupt capability
2. I/O MODE
412
414. b) Mode 1: (Input or Output with
Handshake)
• Handshake signals are exchanged
between MPU & Peripherals
• Features
– Ports A and B are used as Simple I/O Ports
– Each port uses 3 lines from Port C as
handshake signals
– Input & Output data are latched
– interrupt logic supported
414
415. c) Mode 2: Bidirectional Data Transfer
• Used primarily in applications such as data
transfer between two computers
• Features
– Ports A can be configured as the bidirectional
Port
– Port B in Mode 0 or Mode 1.
– Port A uses 5 Signals from Port C as handshake
signals for data transfer
– Remaining 3 Signals from Port C Used as –
Simple I/O or handshake for Port B
415
416. Find control word
(1) Port A: output with handshake
(2) Port B: input with handshake
(3) Port CL: output (4)Port CU: input
Solution:
1 0 1 0 1 1 1 0 = AEH
416
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
417. Port A: Output, Port B: Output,
Port CU: Output, Port CL: Output
Solution:
1 0 0 0 0 0 0 0 = 80H
The control word register for the above ports of Intel
8255 is 80H.
417
418. Port A: Input, Port B: Input,
Port CU: Input, Port CL: Input
Solution:
1 0 0 1 1 0 1 1 = 9BH
The control word register for the above ports of intel
8255 is 9BH.
418
421. 1. This IC is designed to simplify the implementation of the interrupt interface in the 8088
and 8086 based microcomputer systems.
2. This device is known as a ‘Programmable Interrupt Controller’ or PIC.
3. It is manufactured using the NMOS technology and It is available in 28-pin DIP.
4. The operation of the PIC is programmable under software control (Programmable)and it
can be configured for a wide variety of applications.
5. 8259A is treated as peripheral in a microcomputer system.
6. 8259A PIC adds eight vectored priority encoded interrupts to the microprocessor.
7. This controller can be expanded without additional hardware to accept up to 64
interrupt request inputs. This expansion required a master 8259A and eight 8259A
slaves.
8. Some of its programmable features are:
· The ability to accept level-triggered or edge-triggered inputs.
· The ability to be easily cascaded to expand from 8 to 64 interrupt-inputs.
· Its ability to be configured to implement a wide variety of priority schemes.
8259 Programmable Interrupt Controller (PIC)
424. ASSINGMENT OF SIGNALS FOR 8259:
1. D7- D0 is connected to microprocessor data bus D7-D0 (AD7-AD0).
2. IR7- IR0, Interrupt Request inputs are used to request an interrupt and to connect to a slave
in a system with multiple 8259As.
3. WR - the write input connects to write strobe signal of microprocessor.
4. RD - the read input connects to the IORC signal.
5. INT - the interrupt output connects to the INTR pin on the microprocessor from the master,
and is connected to a master IR pin on a slave.
6. INTA - the interrupt acknowledge is an input that connects to the INTA signal on the system.
In a system with a master and slaves, only the master INTA signal is connected.
7. A0 - this address input selects different command words within the 8259A.
8. CS - chip select enables the 8259A for programming and control.
9. SP/EN - Slave Program/Enable Buffer is a dual-function pin.
425. When the 8259A is in buffered mode, this pin is an
output that controls the data bus transceivers in a
large microprocessor-based system.
When the 8259A is not in buffered mode, this pin
programs the device as a master (1) or a slave (0).
CAS2-CAS0, the cascade lines are used as outputs from
the master to the slaves for cascading multiple
8259As in a system.