Welcome to the training module on Samtec High Speed Edge Card Transitions. This training module discusses aspects of the design, simulation, and optimization of edge card connector systems for use in board-to-board riser applications.
The RiseUp ® is Samtec's high speed connector system featuring a high speed interface boards with embedded ground planes to mate with the edge card connectors. In this figure, Samtec used two standard HSEC8 Series edge card connectors and a matched impedance PCB with an embedded HSC8 ground plane for greatly improved performance over traditional connector sets for elevated board stacking. The RU8 series system was modeled completely form the transition from PCB to edge card.
Here is the 3D mechanical model for the high speed connector system. This 3D modeling method is used to provide accurate models for all sections of the RiseUp final Inch PCB, including contact body, PCB, internal contact pins, and riser card which is inserted into the connector system. The three dimensional structures are modeled using a combination of CST Microwave Studio an Sigrity BroadBand SPICE.
Initially in many of connector systems designed in 1990s, the first priority of the connector design was cost, which means make it as cheap as possible. The second priority was the mechanical robustness. Finally the electrical performance was often the last thing to consider. However, in latest generation in 2000s, connector systems are typically optimized for high electrical performance, then cost, and then mechanical robustness. This is changed the way of the connector design and fabricated. For the electrical performance, the design should be focused on providing shorter interconnect paths and higher density, adding ground planes within the interconnects to control EMIs, using different new manufacturing methods robustness and different raw materials.
An impedance discontinuity, or mismatch, occurs at every point in the transmission path where there is change in impedance the signal “sees.” Reflections occur at impedance discontinuities regardless of whether the impedance discontinuity changes from a higher impedance to a lower one or vice versa. For example, the edge finger contact in the riser card may have low impedance, and the surface mount pad in contact finger may have high impedance. The impedance mismatch will cause signal distortion during the transition. The goal to design high speed transition system is to minimize the impedance discontinuities and lower resonances in the frequency domain which cause signal distortion.
There are several compensation schemes to achieve high performance transitions. Trace modification can be done by fabricating a “neck” in the circuit trace on PCB; narrowing to increase impedance and widening to decreased impedance. In general, low impedance structures need to be compensated meaning they need high impedance added. PCB manufacturers do not always facilitate trace widths necessary due to their tolerances, so trace modification is not generally practical in real manufacturing applications. The plane cutback method cuts the plane back all the way under the pad to provide increased impedance. Another method is the plane antipad method which uses a hole on the plane to increase the impedance.
Plane cutback method is used when edge finger contact pad impedance dominates. It is especially effective for differential transitions where there is good return path control.
Plane antipad method is used for single-ended transitions with higher overall impedance. It can be used for edge finger and surface mount contact pads.
Electromagnetic Compatibility (EMC) is achieved when an active electronic device is capable of operating without emitting electrical noise that could disrupt other electronic devices which may be operating nearby. Such noise is called Electromagnetic Interference (EMI). Modern electromagnetic analysis and design of transmission line structures relies heavily on numerically based EM field solvers incorporated in most commercial system level CAE and CAD tools. Here list what the CST Microwave Studio simulation tool can do for measuring the interconnect system.
A more reasoned approach is to characterize the connector and the PCB as a complete system. Only in this situation can all interactions between the board and the connector be observed and characterized. Therefore, each system must be modeled and/or tested individually to completely characterize its performance. In this figure, all features of connector pins, connector body, PCB, and riser card are modeled.
A time domain plot essentially describes the behavior of a particular characteristic over a certain period of time. A data plot representing time domain behavior will use time as its horizontal axis. At time zero, the characteristic will be measured, or calculated, and a corresponding point will be made on the graph. At a later point in time, another sample is taken, which is again plotted on the graph. Sampling is repeated at defined intervals for the desired time period. The oscilloscope was set up in TDR (time domain reflectometry) mode using 128 averages and a 500-point record length. The horizontal scale was set to 500ps/div to allow the near end connector and a portion of the cable to be displayed. The filtering function was set to 35ps. Measurements were made at the near end of each sample. The impedance measurements included the mated connector and at the center of the HSC8 riser card. The red line is compensated result and green line is non-compensated result.
S-parameters, also known as scattering parameters, are a unified set of frequency domain parameters that can be used to completely define the properties of an electrical device. S-parameters can be mapped directly to parameters such as insertion loss (S21), return loss (S11), and crosstalk (S13, S14), so in theory, they can be used to fully characterize an interconnect path. In the frequency domain plot, the horizontal axis of a data plot represents the frequency of a constant amplitude. The vertical axis represents s-parameters. At the first frequency, such as DC (0 Hz), the device is stimulated with a DC signal, and the s-paramenters is measured or calculated. Its value is then plotted on the Y axis. The frequency of the stimulus signal is then increased, another measurement is made and plotted, and so on. Therefore, a frequency domain plot describes how s-parameters will vary with changes in the frequency of the signal that drives it.
An eye diagram of a signal overlays the signal waveform over many cycles. Each cycle waveform is aligned to a common timing reference, typically a clock. An eye diagram provides a visual indication of the voltage and timing uncertainty associated with the signal. It can be generated by synchronizing an oscilloscope to a timing reference. The vertical thickness of the line bunches in an eye diagram indicate the magnitude of AC voltage noise, whereas the horizontal thickness of the bunches where they cross over is an indication of the AC timing noise or jitter. Fixed DC voltage and timing offsets are indicated by the position of the eye on the screen.
In broad terms, a transmission line is a uniform system or line consisting of two parallel conductors. This means that the dimensions, materials, and cross-section of the line and its surrounding environment remain constant throughout its entire length. Signals transmitted into transmission lines would travel at the speed of light if there were no losses in the material. Although the model structure can support the analysis of a specific signal integrity parameter, the accuracy of an analysis will be dependent on the complexity and quality of the connector model. In the RU8 series, the separable interface employs the use of an edge card connector, the connector model should include the PCB connector mated with the edge finger pad that is recommended for the connector. Typically, models developed from calculations are derived from 2D or 3D field solvers. SPICE models of connectors have been around for years, and certain defacto practices and standards have evolved.
Here is the transmission line model.
The plot describes the TDR response of the HSEC8 with 31 to 80 ohm compensated pad impedance in time domain.
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