High performance domino full adder design under different body biased technology

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High performance domino full adder design under different body biased technology

  1. 1. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 2, March – April (2013), © IAEME125HIGHPERFORMANCEDOMINOFULLADDERDESIGNUNDERDIFFERENTBODYBIASEDTECHNOLOGYSaradindu Panda1, Supriyo Srimani2, Prof. Bansibadan Maji3,Prof. Asish Kumar Mukhopadhyay41,2Dept. of Electronics and Communication Engineering, Narula Institute of Technology,Kolkata, India3Professor & Head, Dept. of Electronics and Communication Engineering, NIT, Durgapur,India4Director, BITM, Santiniketan, Birbhum, West Bengal, India.ABSTRACTWith the advancement in semiconductor technology, chip densities are increasing, sothe power consumption in VLSI circuits has become a major problem of consideration. Morepower consumption reduces the battery life of the devices and increases packaging cost. Inmodern digital VLSI circuits Dynamic domino logic circuits are widely used. Static CMOSlogic circuits are very low speed circuit. Dynamic CMOS circuits, featuring a high speedoperation are used in high performance VLSI designs. In this work, domino Full Adder isdesigned with various body biasing circuit. The proposed design is tested in 150nm and45nm. Moreover Noise, Power and Delay have been compared also.Keywords: Conventional body bias, CMOS, Domino logic, Dynamic power.I. INTRODUCTIONA CMOS circuit can have two kinds of Power consumption- dynamic or static.Dynamic power dissipation takes place due to switching activities and charging anddischarging of load capacitances. Static power consumption is another type of powerdissipation in CMOS circuits [1]. The power consumed in high performance Microprocessorhas increased to levels that impose a fundamental limitation to increasing performance andINTERNATIONAL JOURNAL OF ADVANCED RESEARCH INENGINEERING AND TECHNOLOGY (IJARET)ISSN 0976 - 6480 (Print)ISSN 0976 - 6499 (Online)Volume 4, Issue 2 March – April 2013, pp. 125-133© IAEME: www.iaeme.com/ijaret.aspJournal Impact Factor (2013): 5.8376 (Calculated by GISI)www.jifactor.comIJARET© I A E M E
  2. 2. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 2, March – April (2013), © IAEME126functionality [3]. Domino logic circuit techniques are extensively applied in highperformance microprocessors due to the superior speed and area characteristics of comparedto static CMOS circuits [4]. Domino logic circuits, however, are highly sensitive to noise ascompared to static gates. Now a day’s enhancing the circuit speed without considering thepower is not acceptable in circuit design. So it has become necessity of the VLSI circuits toreduce the dynamic as well as the static power consumption. Leakage currents with sub-threshold source-to-drain leakage, reverse bias junction band-to-band tunneling, gate oxidetunneling, and other current drawn continuously from the power supply cause static powerdissipation. Dynamic switching power is quadratically reduced by lowering the supplyvoltage. Reduction of supply voltage after a certain limit affects the performance of thecircuit, to maintain circuit performance of the circuit it is necessary to decrease the thresholdvoltage as well, but it leads to leakage power dissipation.At reduced threshold voltage, however sub threshold leakage current increaseexponentially. So, lowering leakage currents are, therefore, highly desirable. Domino logiccircuit techniques compared to static CMOS circuits are extensively applied in highperformance microprocessors due to the speed and area characteristics of domino CMOScircuits. It has become a major challenge to design error free operation of domino logiccircuits as on-chip noise becomes more with technology scaling and increasing operatingfrequencies.A portable system must be designed for low power consumption. Supply voltagescaling is an effective way to reduce power consumption. However, threshold voltage cannotbe scaled down with the same rate. So, sub threshold operation is a better option for lowpower applications. The sub threshold logic operates with the power supply ddV less than thethreshold voltage thV of the transistor.In this paper domino FULL ADDER with different substrate biasing techniques aredesigned and their performances are compared. Power consumption, delay, noise are used asparameters in sub threshold region. The designs are tested and compared at 150 nm and 45nm technologies to prove the technology independence of the proposed design.A. Full AdderA and B are the adder inputs, Ci is the carry input, S is the sum output, and Co is the carryoutput. The Boolean expressions for S and Co are given by the following equations:iiiii ABCCBACBACBACBAs +++=⊕⊕= ii ACBCABC ++=0Some logic manipulations can help to reduce the transistor count. The following is anexample of such a reorganized equation set:ii ACBCABC ++=0 )(0 ii CBACABCS +++=Fig:1 shows the circuit diagram of a CMOS Full Adder Circuit and Fig: 2 show the outputwave form of the Full Adder Circuit::
  3. 3. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 2, March – April (2013), © IAEME127Fig. 1 Circuit diagram of a Full Adder Circuit Fig. 2 Output wave form of a Full AdderCircuitII. CIRCUIT TECHNIQUESDynamic domino logic circuits are widely used in modern VLSI circuits. Thesedynamic circuits are often favored in high performance designs because of the speedadvantage offered over static CMOS logic. The main drawbacks of dynamic logic are a lackof design automation, increased power Consumption. As supply voltage is reduced, delayincreases, unless threshold voltage TV is also decreased. The voltage difference between thesource and the substrate BSV also affects the width of the depletion layer and due to changes inthe charge in depletion layer voltage across the oxide also get changed. Therefore theexpression for the threshold voltage is given by:( )OXSBFasFFBTCVqNVV+++=φεφ222The threshold difference due to an applied source-substrate voltage can therefore beexpressed by:( )( )FSBFT VV φφγ 22 −+=∆Where, γ is the body effect parameter given byOXasCqNεγ2=III. STANDARD DOMINO NAND GATEA standard domino NAND gate is as shown in Figure 3. A standard Domino NANDgate consists of one p-type transistor and an n-type dynamic logic block. During pre-chargephase the output node of the dynamic CMOS stage is pre-charged to high logic level. During
  4. 4. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 2, March – April (2013), © IAEME128evaluation phase, the output node of the dynamic CMOS stage is either discharged to a lowlevel or it remains high, means that, the output node may be selectively discharged throughthe n-type logic block depending upon whether there is a path exist to the GND or not. Itdepends upon the inputs of the NMOS logic block. If a path to ground is not formed duringthe evaluation phase, means there is no conducting path exist to the ground, we get the highlogic level at the output. If inputs to the n-type logic blocks are such that it makes aconducting path to the ground, output will be low.Fig. 3 Circuit Diagram of a Domino NAND gate.IV. PROPOSED BODY BIASED FULL ADDERIn order to enhance the performance of the circuit, various body biasing techniquesare used.The substrate of the MOS transistors is connected in six different ways. Six body biasingschemes for the evaluation networks are shown in figure 4.1. The substrate of NMOS is connected to clock and the substrate of PMOS is connectedto supply voltage VDD (SB1).2. The substrate of NMOS and PMOS is connected to clock (SB2).3. The substrate of NMOS is connected to supply voltage VDD and the substrate ofPMOS is connected to Ground (SB3).4. The substrate of NMOS is connected to supply voltage VDD and the substrate ofPMOS is connected to clock (SB4).5. The substrate of NMOS and PMOS both connected to supply voltage VDD (SB5).6. The substrate of NMOS is connected to its source terminal and the substrate of PMOSis connected to clock (SB6).
  5. 5. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 2, March – April (2013), © IAEME129a. b.c. d.e. f.Fig. 4 (a)SB1, (b)SB2, (c)SB3, (d)SB4, (e)SB5, (f)SB6.For 45nm: NMOS: W=0.135u L=0.045u AS=AD0.030375p PS=PD=0.72uPMOS: W=0.27u L=0.045u AS=AD=0.06075p PS=PD=0.99uFor 150nm: NMOS: W=.45u L=.15u AS=AD=.3375p PS=PD=2.4uPMOS: W=.9u L=.15u AS=AD=.675p PS=PD=3.3u
  6. 6. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 2, March – April (2013), © IAEME130V. SIMULATION RESULTThe designs are simulated using 150nm and 45nm technology. The supply voltage in150 nm is 0.4 V and 0.2 V for 45 nm are used. Power consumption, delay, Noise is measured.Fig. 5 Output wave form of a Full Adder Fig. 6 Output wave form of a Full Adder inCircuit 150nm technology Circuit in 45nm technologyFig. 7 Power Consumption at different Fig. 8 Power Consumption at differentbias in 150nm technology bias in 45nm technologyFig. 9 Delay at different bias in 150nm Fig. 10 Delay at different bias in 45nmtechnology technology
  7. 7. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 2, March – April (2013), © IAEME131Fig. 11 Output Noise at different bias in Fig. 12 Output Noise at different bias in150nm technology 45nm technologyTable 1: Comparison of Noise, Power and Delay of Full Adder Circuits under Different Biasand Different Scaling TechnologySB6 biasing, in which the substrate of NMOS is connected to its source terminal and thesubstrate of PMOS is connected to clock condition, shows minimum power consumption,delay. At supply voltage of 0.2V, SB6 biasing condition again shows minimum value ofpower consumption. Similar results are obtained in 150 nm technology at supply voltage of0.4V confirming that the SB6 biasing is the best biasing for domino Full Adder design. Thepower consumption by the gate is least at various supply voltages, when the SB6 biasing isused. The SB2 biased gate shows sudden decrease in delay at supply voltage. The noise isalmost similar in all cases in 45nm as well as 150nm technology. In case of 150 nmtechnology the operating frequency is 1GHz but for 45nm technology the operatingfrequency is 1000MHz. Higher frequency cannot be used in 45nm technology, because due tosmall length collision increase between the carriers so the noise increases. The powerconsumption among t various biasing by the gate SB6 biasing is less than the other biasingschemes.Bias I II III IV V VI150nmNoise(µV)330 340 370 300 350 350Power(nW)7.2 6.1 3.1 7.1 3.52 0.44Delay(pSec)12.3 2.3 5.8 12 6.8 8.7790nmNoise(µV)2.49 2.47 2.52 2.46 2.5 2.5Power(pW)0.936 1.31 1.81 1.71 1.75 0.25Delay(pSec)1.26 1.29 2.4 1 2.3 7.2
  8. 8. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 2, March – April (2013), © IAEME132VI. CONCLUSIONDomino logic circuit techniques compared to static CMOS circuits are extensivelyapplied in high performance microprocessors due to the speed and area characteristics ofdomino CMOS circuits. Comparison of body bias methods using delay, power and noiseindicates ultra-low voltage domino circuits to be realized. Minimum energy in the subthreshold region then depends not only on supply voltage but also on the substrate biasvoltage.Simulation analysis reveals that the Full Adder design using SB6 biasing scheme is anenergy efficient design.VII. ACKNOWLEDGEMENTSThe authors would like to thank Prof. (Dr.) M.R.Kanjilal and Faculty Members,Department of Electronics and Communication Engineering, Narula Institute of Technology,WBUT, for many insightful discussions.REFERENCESJournal Papers[1] Pushpa Raikwal V. Neema, and S. Katiyal, “LOW POWER WITH IMPROVEDNOISE MARGIN FOR DOMINO CMOS NAND GATE”, Proceedings of the InternationalJournal Of Computational Engineering Research / ISSN: 2250–3005.[2] H. Mangalam and K. Gunavathi, “Domino Logic Circuit with Reduced Leakage andImproved Noise Margin”,International Journal of Applied Engineering Research ISSN 0973-4562 Volume 2, Number 4 (2007), pp. 585–593.[3] Aswathy G Nair and Gopakumar M G, “CS-CMOS: A Low-Noise Logic Family forMixed Signal SOCS”, International journal of Electronics and Communication Engineering&Technology (IJECET), Volume 4, Issue 2, 2013, pp. 180 - 190, ISSN Print: 0976- 6464,ISSN Online: 0976 –6472.[4] P.Sreenivasulu, Krishnna veni, Dr. K.Srinivasa Rao and Dr.A.VinayaBabu. “LowPower Design Techniques of CMOS Digital Circuits”, International journal of Electronicsand Communication Engineering &Technology (IJECET), Volume 3, Issue 2, 2012,pp. 199 - 208, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472.Proceedings Papers[5] A. Alvandpour, P. Larsson-Edefors, and C. Svensson, “A Leakage Tolerant Multi-Phase Keeper for Wide Domino Circuits”, Proceedings of the IEEE International Conferenceon Electronics, Circuits and Systems, pp. 209-212, September 1999.[6] V. Kursun and E. G. Friedman, “Low Swing Dual Threshold Voltage Domino Logic”,Proceedings of the ACM/SIGDA Great Lakes Symposium on VLSI, April 2002.[7] R. Ronen et al., “Coming challenges in microarchitecture and architecture”, Proc.IEEE, vol. 89, pp. 325–339, Mar. 2001.
  9. 9. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 2, March – April (2013), © IAEME133BIOGRAPHYSaradindu Panda, He received M.Tech from Jadavpur University in 2007 in VLSIDesign and Microelectronics Technology. He is pursuing his PhD at NIT, Durgapur, WestBengal, India. Presently, he is involved in design and management of low-power and highspeed integrated circuits with Solid State Devices in Nano Regime. He is now faculty in ECEDepartment at Narula Instutute of Technology, Kolkata, India. He has more than 15publications in different International and National Journals and Conference Proceedings.Supriyo Srimani, He is pursuing B.Tech in ECE, Narula Instutute of Technology,Kolkata, India. His research interest in the area of VLSI Low Power Design, ImageProcessing, Signal Processing.Prof. (Dr.) Bansibadan Maji, He is now a senior Professor of ECE Department inNIT, Durgapur, West Bengal, India. He is now Head of The Department of ECE at NIT. Hismain research area on Microwave, Antenna, VLSI Design and Low power Device andCircuits. He has more than 56 publications in different International and National Journalsand Conference Proceedings.Prof. (Dr.) A. K. Mukhopadhyay, He received M.Tech from IIT, Kharagpur,and Ph.D(Engg) from Jadavpur University, India. Currently, he is the Director of BITM,Santiniketan, Birbhum, West Bengal, India. He was the Principal of BCET, Durgapur.Previously he served as the Dean (Academic) and Head of Department of ECE, Dr. B. C. RoyEngineering College, Durgapur. He also worked at Narula Institute of Technology, Kolkata,College of Engineering & Management, Kolaghat, NERIST, Itanagar and IIT, Kharagpur.His current area of research includes Wireless and Mobile Networks and Overlay-basedheterogeneous networks. He has 48 publications mostly in international journal andconference proceedings. He is a Life Fellow of the Institution of Engineers (I), Member,IEEE, Member, IEEE ComSoc, Global Member, ISOC; Sr. Life Member, CSI; Life Member,ISTE, IETE, SSI etc.

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