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Nowak NVSMW-ICMTD'08

Presentation done at IEEE NVSMW-ICMTD conference in June 2008

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Nowak NVSMW-ICMTD'08

  1. 1. On the Influence of Fin Corner Rounding in 3D Nanocrystal Flash Memories E. Nowak , L. Perniola, G. Ghibaudo*, C. Jahan, P. Scheiblin, G. Reimbold, B. De Salvo, F. Boulanger CEA/LETI-Minatec, 38054 Grenoble, France * IMEP/INPG Grenoble, France [email_address]
  2. 2. Outline <ul><li>Introduction </li></ul><ul><li>Model motivations </li></ul><ul><li>Corner region vs. planar region </li></ul><ul><li>Comparison with 3D TCAD simulations </li></ul><ul><li>Comparison with experimental data </li></ul><ul><li>Conclusion </li></ul>
  3. 3. Nanocrystal FinFlash <ul><li>Tri-gate FinFET advantages </li></ul><ul><ul><li>Increased drive current and improved access time in NAND </li></ul></ul><ul><ul><li>Reduced Short Channel Effects </li></ul></ul><ul><ul><li>Ultra-small cell area (NAND) </li></ul></ul><ul><ul><li>Compatibility with multigate CMOS for complex SoC </li></ul></ul><ul><ul><li>SOI cells can be integrated in 3D vertical architectures </li></ul></ul><ul><li>Nanocrystal memory advantages </li></ul><ul><ul><li>Strong immunity to oxide defects </li></ul></ul><ul><ul><li>Improved scalability </li></ul></ul><ul><ul><li>Lower operating voltages </li></ul></ul>BOX source Control Gate Fin
  4. 4. Modeling Fowler-Nordheim operation <ul><li>Issue </li></ul><ul><ul><li>Corners in 3D structure appears critical </li></ul></ul><ul><ul><li>Not available simple models for Fowler-Nordheim operation in complex 3D structures taking corner curvature radius into account </li></ul></ul><ul><li>Our approach </li></ul><ul><ul><li>Physics-based modeling of FN write/erase for trigate FinFLASH with Si-NCs </li></ul></ul>BOX source Control Gate Fin V G
  5. 5. Outline <ul><li>Introduction </li></ul><ul><li>Model motivations </li></ul><ul><li>Corner region vs. planar region </li></ul><ul><li>Comparison with 3D TCAD simulations </li></ul><ul><li>Comparison with experimental data </li></ul><ul><li>Conclusion </li></ul>
  6. 6. 3D TCAD Simulations + <ul><li>3D tunneling simulation  charge trapping depends on local fin curvature radius </li></ul><ul><li>3D transport simulations  fin current density locally dependent on planar/corner regions </li></ul>+ ATLAS user guide, www.silvaco.com
  7. 7. Model presentation (1/2) <ul><li>1D potential & capacitance calculation for planar and corner regions </li></ul><ul><ul><li>top/side  planar geometry </li></ul></ul><ul><ul><li>corner  cylindrical geometry </li></ul></ul>planar geometry corner geometry
  8. 8. Model presentation (2/2) <ul><li>Tunneling module: WKB approximation on the real barrier shape </li></ul><ul><li>Transport module: total programming window </li></ul><ul><li>with </li></ul>
  9. 9. Present model vs. IEDM’07 model * <ul><li>Previous model* based on Green function approach for NC FinFLASH tailored for SOI vs. Body-Tied </li></ul><ul><li>Present model does not need any Green function solution  lighter computationally </li></ul><ul><li>Present model implements tunneling through high-k stacks </li></ul>* L. Perniola et al., Tech. Dig of IEDM, pp.943-946, 2007.
  10. 10. Outline <ul><li>Introduction </li></ul><ul><li>Model motivations </li></ul><ul><li>Corner region vs. planar region </li></ul><ul><li>Comparison with 3D TCAD simulations </li></ul><ul><li>Comparison with experimental data </li></ul><ul><li>Conclusion </li></ul>
  11. 11. <ul><li>Flash need a coupling ratio [ITRS] </li></ul><ul><li>Better control on the floating gate voltage thanks to corner </li></ul>Coupling ratio: planar vs corner regions 1 10 20 30 40 50 0 0.2 0.4 0.6 0.8 1 Curvature radius (nm) Coupling ratio  g planar geometry cylindrical geometry Si/SiO2(5nm)/dots Si/SiO2(13nm)/PolySiN+
  12. 12. Programming window: planar vs. corner regions <ul><li>Corner regions show: </li></ul><ul><li>Bigger programming windows </li></ul><ul><li>Faster dynamics during program and erase operations </li></ul> Vt cylin  Vt plan Rc=5.8nm planar No charge stored 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 0 1 2 3 0 5 10 15 20 -14 -12 -10 -8 -6 -4 -2 0 2 4 (b) (a) Programming windows  Vt [V] Pulse Time t [s] Si HfO2 SiO2 dots Si SiO2 Si Conduction Band Energy [eV] x [nm]
  13. 13. Outline <ul><li>Introduction </li></ul><ul><li>Model motivations </li></ul><ul><li>Corner region vs. planar region </li></ul><ul><li>Comparison with 3D TCAD simulations </li></ul><ul><li>Comparison with experimental data </li></ul><ul><li>Conclusion </li></ul>
  14. 14. Model vs. 3D TCAD simulation <ul><li>Reproduce accurately both </li></ul><ul><ul><li>The trapped charge of each dot </li></ul></ul><ul><ul><li>Programming window </li></ul></ul>Dot A Dot C Dot B Dot D Dot A Dot C Programming windows Δ Vt[V] 10 -7 10 -6 10 -5 10 -4 0 1 2 3 4 Model Simulation Rc=15nm Rc=25nm Pulse Time t [s] 10 -7 10 -6 10 -5 10 -4 -5,0x10 -2 0 Model Simulation Rc=15nm Rc=25nm planar Trapped Charge density Q [C.m -2 ] Pulse Time t [s]
  15. 15. Outline <ul><li>Introduction </li></ul><ul><li>Model motivations </li></ul><ul><li>Corner region vs. planar region </li></ul><ul><li>Comparison with 3D TCAD simulations </li></ul><ul><li>Comparison with experimental data </li></ul><ul><li>Conclusion </li></ul>
  16. 16. Program/Erase Dynamics of LETI devices <ul><li>Good fit obtained on devices with high-k in top dielectrics </li></ul>10 -6 10 -4 10 -2 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 10 -6 10 -4 10 -2 Programming windows  Vt [V] Data Model Vg=8V Vg=10V Vg=12V Vg=14V 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 Data Model Vg=-5V Vg=-7V Vg=-9V Vg=-11V Pulse Time t [s] Pulse Time t [s]
  17. 17. Fin Width & Height impact on Δ VT <ul><li>Δ VT increases when the width and height decrease due to enhanced corner impacts </li></ul>[2] K. Yanagidaira et al., Jpn. J. Appl. Phys., pp.2608-2611, 2005. H=6 nm 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 Programming windows  Vt [V] H=60 nm 0 20 40 60 80 0 20 40 60 80 Fin Width W [nm] Fin Width W [nm] ref. [2] model planar component cylindrical component
  18. 18. Curvature radius impact on Δ VT <ul><li>Δ VT balance from the quantity of injected charge and the area coverage over the fin </li></ul><ul><li>Hemispherical devices behave better than trigate devices </li></ul>Hemispherical R= W/2 6 8 10 12 14 16 18 Curvature radius R [nm] Trigate R  0 10 μ s 100 μ s 10ns  1 s 100ns H=18nm W=36nm Vg=14V 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 2,0 2,2 Programming windows  Vt [V]
  19. 19. Outline <ul><li>Introduction </li></ul><ul><li>Model motivations </li></ul><ul><li>Corner region vs. planar region </li></ul><ul><li>Comparison with 3D TCAD simulations </li></ul><ul><li>Comparison with experimental data </li></ul><ul><li>Conclusion </li></ul>
  20. 20. Conclusion <ul><li>On the model </li></ul><ul><ul><li>Quantitatively fitting dynamics under FN operation for 3D nanocrystal flash memories employing high-k dielectrics </li></ul></ul><ul><ul><li>Approach suitable for compact modeling </li></ul></ul><ul><ul><li>Perspectives: </li></ul></ul><ul><ul><ul><li>Easily extended to various 3D memory device architectures (3G, Ω G , GAA) </li></ul></ul></ul><ul><ul><ul><li>Can be extended to SONOS FinFet devices </li></ul></ul></ul><ul><li>On corner rounding </li></ul><ul><ul><li>Appears to be a critical design parameter </li></ul></ul><ul><ul><li>Hemispherical devices show a higher Δ VT than trigate devices </li></ul></ul>
  21. 21. Device Fabrication <ul><li>SOI wafers, Tsi=30 nm </li></ul><ul><li>Fins patterning with Ebeam lithography and resist trimming </li></ul><ul><li>Sidewall sacrificial oxidation </li></ul><ul><li>Boron implantation for VTH adjustment </li></ul><ul><li>Gate stack deposition process: </li></ul><ul><li>Gate patterning: Ebeam lithography, resist trimming and combined dry and wet etching </li></ul><ul><li>Extension implants + 950°C RTA anneal </li></ul><ul><li>50 nm nitride spacers + 20 nm S/D Si SEG </li></ul><ul><li>S/D implants + 1050°C Spike anneal </li></ul><ul><li>Ni Silicidation + classical Back-end process </li></ul>Buried oxide Si fin Gate C. Jahan et al., NVSMW-ICMTD ‘08 Poly-Si N + SiO2 Si-ncs HTO Si Poly
  22. 22. The evaluation of access resistance allows to calculate the potential drop along the series of on-pass SOI cells in the NAND string, during write/erase steps V* G-stress V D-inhibit V D-inhibit V G-HIGH V G-HIGH Solution : Write/erase operation for SOI arrays at a cell-by-cell or wordline level Purpose : Source/drain of selected cell must be pinned at ground for efficient write/erase Write/Erase of SOI cells in NAND arrays Problem : Efficient W/E operations for NAND arrays of SOI FD FinFlash.
  23. 23. <ul><li>The access resistance for the single cell is around 1 – 100 k Ω range </li></ul><ul><li>In NAND string, the potential drop through the on-pass gates is estimated to be of the order of µV </li></ul><ul><li>FN write/erase performance of single cell can be extrapolated to the selected cell included in the NAND string </li></ul>Access resistance
  24. 24. Scaling limits of Fin Flash devices Thanks to C. Gerardi – STMicroelectronics Y pitch not a concern: L G =30 nm functional devices X pitch is a concern: Enough space to accommodate fin/gate stack/control gate X pitch x = fin + 2d + m = 10nm + 30nm + 5nm = 45 nm F = x/2 = 20-22 nm From ITRS 2007 : 2014 in production
  25. 25. Vt dependence with Radius of curvature <ul><li>Simulation shows: </li></ul><ul><ul><li>Change of Vt with R is of the order of 100mV for GAA device </li></ul></ul><ul><ul><li>A better electrostatic control is obtained for higher curvature radius </li></ul></ul>C.W. Lee et al., Solid State Electronics 51 (2007) pp. 505-510

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  • Archontas

    Apr. 22, 2010

Presentation done at IEEE NVSMW-ICMTD conference in June 2008

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