This document is a resume for Vishal P Mehta. It summarizes his education, skills, work experience and academic projects. He received a Master's degree in Electrical Engineering from UT Dallas and a B.Tech in Electronics Engineering from Sardar Vallabhbhai National Institute of Technology. For work experience, he had internships at Intel and was a Junior Research Fellow at IIT Delhi. His skills include Verilog, C/C++, Python and CAD tools like Cadence and Synopsys. Some of his academic projects included designing an SRAM, ALU and implementing a digital audio processor using Verilog.

1. VISHAL P MEHTA 601 W Renner Road
vishal_mehta@outlook.com Apt #124
+1-979-204-1743 Richardson, Texas- 75080
 CAREER PROFILE
 Exposure toCustom/ASICdesign usingIBM130 nm and performance modelingusingSpice.
 Exposure toComputerArchitecture and SRAMMemoryDesign.
 Hands onexperiencewithMSP430, ARM Cortex M4 andVirtex2Pro.
 EDUCATION
Universityof Texasat Dallas,Richardson,TX January-2104 to December- 2014
Master of Science inElectrical Engineering GPA:3.56/4.0
RelatedCoursework:
MicroprocessorSystems AdvancedVLSI Design VLSIDesign
ComputerArchitecture AdvancedDigital Logic AnalogCircuitDesign
ASIC(ApplicationSpecificIntegratedCircuits) HDL SynthesisandModelling
Sardar Vallabhbhai National Instituteof Technology(NITSurat), July-2007 to May-2011
B.Tech in Electronics Engineering. GPA:8.0/10.0
 WORK EXPERIENCE
Intel (DesignAutomation Intern) Feb-2014 to Aug2014
 Developed anIPQuality/Validation flow fromscratch usingpython toenable designengineersto
validate severalformatsrelatedtoanIP. Extensivelyinvolvedin assistingdesignengineers
providingautomationscriptsinPerl andPython.
Indian Institute of TechnologyDelhi,IIT-Delhi (JuniorResearchFellow) Jun-2011 to Dec-2012
 Designedanembeddedsystem withfeedbackcontrol whichincludedinterfacing MEMS, ADCand
DAC boardsto Xilinx Virtex-2proboardusingVHDL and EDK. Designed,Fabricated12-bitADCand
DAC circuitboards usingAltiumasperprojectspecifications
 TECHNICAL SKILLS
Languages : C, EmbeddedC,C#( basic), Verilog,C++(basic),Perl, Python
CAD Tools : Cadence Virtuoso,Assura,Encounter,Crossfire,Solidworks
SynopsysTools : DesignVision/Compiler,ICC,Primetime,WaveView,LibertyNCX,TetraMax.
Simulators : Modelsim,VCS,Spice,Xilinx-ISESimulater.
Embedded : Xilinx EDK,Code ComposerStudio 5.3,ArduinoIDE, AVRStudio 4
PCB Designing : Altium,Ultiboard,gEDA
OperatingSystems : Windows,Unix
 ACADEMIC PROJECTS
RTL Implementationof Mini StereoDigital AudioProcessor Fall-2014
 Implementingprogrammable finite impulseresponse (FIR) digitalfilterusingIBM130 nm process.
RTL implementation aswell asfunctionalverification of the filterisdone using Verilog. Chip
designedis lowcostandlowpowersince itwill be usedforhearingaid purpose.DesignVisionis
usedto generate the synthesizednetlistandICCisusedforplace and route.
ArithmeticLogic Unit Designand Implementation Spring-2013
 ImplementedALUdesignusingVerilogandIBM130nm Technology. Createdastandardcell library
for realizingthe design.LibraryCharacterizationwasperformedusingNCXandPrimeTime was
usedto findthe critical pathfor the chipdesigned. Encounterwasusedforplacementandrouting
and Spice wasusedformodeling.
1Kbit SRAM designwith6T memory cell for effective Areaand Delay trade-off Summer-2013
 Designed1Kilo-bitSRAMusingIBM130nm TechnologyusingCadence Virtuosoaslayouttool.
Designedas well aslaidoutmanuallydrivercircuitsforRow,ColumnDecoders, buffercircuitfor
Clock,bitline conditioningcircuitsandread/write circuitry.

2. VISHAL P MEHTA 601 W Renner Road
vishal_mehta@outlook.com Apt #124
+1-979-204-1743 Richardson, Texas- 75080
23bX23b Multiplierdesign Summer2013
 Translatedsetof designspecificationsinto functional circuitschematicusingCadence with
optimal delayandactive area. Adaptedthe Booth-2basedmultiplierdesignandusedpartial
productcompressionandRipple carryAddertoperformthe multiplicationonsignedaswell as
unsignednumbers
Optimizing2D PhysicsEngine for EmbeddedSystems Spring-2013
 Implementedelasticphysics (elasticball collision)simulatorfor2D plane onARM Cortex M4.
Processorwouldcompute the future velocitiesof the ballsandwouldsenditreal time tothe GUI.
Optimizedthe code toaccuratelypredictthe future positionof 100 2D objectssimultaneously.
OptimizedCache Designconsideringdifferentbranch predictors Fall-2013
 Fine tunedCache hierarchyof an Alphamicroprocessorfor3individual benchmarks. ExecutedPerl
code whichperformedanumberof iterationsforeachbenchmarkandthenvalueswere plottedto
findthe optimizedcache design.AnalysedCPIusingBimodal and2–level branchpredictors.
Parametersconsideredwere BlockSize,ReplacementPolicies,Associativity,Costandseveral types
of predictors.
Testingof various circuits usingTetraMax: Fall- 2013
 Performedautomatictestpatterngenerationandfaultcoverage of severalcircuitsincluding
ISCAS89 s27 benchmark. Replacednormal flip-flopswithscanflip-flopsandcomparedArea,Power
and Timingof the circuits. Keydesigntool usedDesign VisionSynopsystogenerate netlistand
TetraMax forATPG.
Process Control Using Controller Area Network (CAN) Protocol
 Developed a low cost embedded CAN system using Atmega32 as master and slave controller.
Microchip MCP2515 and MCP2551 were used as CAN controller and Transceiver respectively.