1. Transistor Biasing

2. (Transistor Biasing)
1.
2.
3.
1.
2.
3.
1

3. 1.
Biasing)
2.
(Transistor Biasing)
2

4. 3.
4
1. Fixed Bias Circuit)
2. Emitter-Stabilized
3. Voltage Divider
4. DC DC Bias with
(Transistor Biasing)
3

5. (Transistor Biasing)
3.1 Fixed Bias Circuit)
3.2 Emitter-Stabilized Bi
IB RB
-
-
-
(ß)
RE
(ß)
-
-
4

6. (Transistor Biasing)
3.3 Voltage Divider Bia
3.4 DC DC Bias with Volt
-
–
Input
-
IC, VCE
-
210ER R
5

7. 4.
4.1 Fixed Bias Circuit)
(Transistor Biasing)
4.1 Fixed Bias Circuit)
(a) (b)
1. Input Output 4.1 (b
2. Capacitor
Capacitor
6

8. 0.7 ( )
= 0.3 ( )
,
( 1)
BE
BE
C
FE
B
C B
E C B
E B B
E B C
V V Silicon
V V Germanium
I
h
I
I I
I I I
I I I
I I I
(Transistor Biasing)(
3.
………………………………………
……………………….... 4-6
4. (Kirchhoff's
Voltage Law, KVL)
……………………… 4-1
…………………………………… 4
…………………………………....
……………………………….... 4
7

9. BCC R BE
CC B B BE
CC BE B B
CC BE
B
B
V V V
V I R V
V V I R
V V
I
R
(Kirchhoff's Voltage Law, KVL)
“
(Transistor Biasing)
4.1 (c) Input
4.1 (b)
Input
BR B BV I R
…………....
4-7 …………....
…………....
…………....
8

10. 0
CCC R CE
CC C C CE
CE CC C C
C CE
B BE
E
V V V
V I R V
V V I R
V V
V V
V
(Kirchhoff's Voltage Law, KVL)
(Transistor Biasing)
4.1 (d) Output
4.1 (b)
Output
……….... 4
CR C CV I R 4-11 …….... 4
…….... 4
…………..……....
4-14…………..……....
4-15…………..……....
4-16
9

11. 12 V 0.7 V
47.08 uA
240 kΩ
(50)(47.08 uA ) 2.35 mA
= 12 V (2.35 mA)(2.2 kΩ )
= 6.83 V
0.7 V
6.83 V
CC BE
B
B
C B
CE CC C C
B BE
C CE
V V
I
R
I I
V V I R
V V
V V
1. 4.1 (e) IB, IC, V(Transistor Biasing)
4.1 (e)
* *
2.35 mA 47.08 uA
2.397 mA
E C B
E C
I I I
I I
…….... 4-4
4-3
4-13
4-15
4-14
4-10
10

12. (Transistor Biasing)
4.1

13. (Transistor Biasing)4.2 Emitter-Stabilized
4.2 Emitter-Stabilize
(a) (b)
11

14. 0
( 1)
( 1) 0
( 1)
[ ( 1) ]
-
( 1)
CC B B BE E E
E B
CC BE B B B E
CC BE B B B E
CC BE B B E
CC BE
B
B E
V I R V I R
I I
V V I R I R
V V I R I R
V V I R R
V V
I
R R
0
0
( ) 0
( )
CC C C CE E E
E C
CC C C CE C E
CC CE C C E
CE CC C C E
V I R V I R
I I
V I R V I R
V V I R R
V V I R R
(Transistor Biasing)
4.2 (c) Input 4.2 (d) O
…. 4-6 …. 4-6
…....
4-17
….
4-18
12

15. (Transistor Biasing)4.3 Voltage Divider
4.3 Voltage Divi
(a) (b)
4.3 (a)
13

16. 1 2ThR R R
1 2
2
1 2
2
1 2
1 2
1
2
2
( )
[ ]
CC R R
CC
CC
Th R
CC
Th
V V V IR IR
V I R R
V
I
R R
E V IR
V
E R
R R
(Transistor Biasing)
4.3 (c) 4.3 (d)
4.3 (e) VR2
…..…..….
4-19
...…..….
4-20
14

17. 0
( 1)
( 1) 0
( 1)
[ ( 1) ]
-
( 1)
Th B Th BE E E
E B
Th BE B Th B E
Th BE B Th B E
Th BE B Th E
Th BE
B
Th E
E I R V I R
I I
E V I R I R
E V I R I R
E V I R R
E V
I
R R
(Transistor Biasing)
4.3 (f) ...…..….
4-21
Output
15

18. ' 0
'
' ,
0
0
= ( )
[ ( )]
CC C C B B BE E E
C B C
C C E C
CC C C B B BE C E
C B
CC B C B B BE B E
CC BE B C B B B E
B C B E
CC BE B B C E
V I R I R V I R
I I I
I I I I
V I R I R V I R
I I
V I R I R V I R
V V I R I R I R
I R R R
V V I R R R
I
-
( )
CC BE
B
B C E
V V
R R R
(Transistor Biasing)4.4 DC DC Bias
with Voltage Feedback)
4.4 DC
...…..….
4-22
(a)
(b)
16

19. ' 0
'
' ,
0
( ) 0
( )
CC C C CE E E
C B C
C C E C
CC C C CE C E
CC CE C C E
CE CC C C E
V I R V I R
I I I
I I I I
V I R V I R
V V I R R
V V I R R
(Transistor Biasing)
4.4 (c)
Output
17

20. (Transistor Biasing)