Cse

Digital Techniques S.E. CSE Department of Computer Science & Engg.
LAB MANUAL
DIGITAL TECHNIQUE
ACADEMIC YEAR 2014-15
Dept. of CSE (S E)
SEM-I(2014-15)

DIGITAL TECHNIQUES
INDEX
SR.
NO.
TITLE OF THE
EXPERIMENT
PAGE
NO.
Date of
Performance
Date of
Evaluation
Sign
1 Verification of truth table of
basic and universal logic
gates.
2 Implementation of Boolean
functions using Basic and
Universal Gates.
3 Implementation of reduced
Boolean functions (K – map
technique) from Assignment
No. 2 using basic and
universal gates.
4 Implementation of half
adder and full adder.
5 Implementation of half
subtractor and full
subtractor.
6 Implementation of parity
checker.
7 Implementation of flip flops
using NAND/NOR gates
S-R Flip flop
D flip flop
J-K Flip flop
T Flip flop
8 Implementation of 3 bit
Asynchronous counter.
9 Implementation of
a. Boolean functions from
Assignment No. 2 using
multiplexer ICs.
b. Full adder using 4:1
multiplexers IC.
10 Implementation of Mod 10
(Decade) Counter using IC
7490.
2

SR.
NO.
TITLE OF THE
EXPERIMENT
PAGE
NO.
Date of
Performance
Date of
Evaluation
Sign
11 Implementation of 7
segment display using
decoder/driver7447.
Dept. of CSE (S E)
SEM-I(2014-15)

N B Navale Sinhgad College of Engineering
Department of Computer Science and Engineering
Sub: -Digital Technique
Experiment No. 01
Experiment Name Verification of truth table of basic and universal logic
gates.
Experiment
Performed
Date -
Signature of In-charge
Experiment
Submitted
Date -
Experiment No. 1
4

Aim: To verify the truth-table of all Basic and Universal Gates
Apparatus: IC Trainer Kit, patch chords, power supply, AND(IC 7408), OR
(IC7432), NOT (IC7404), NOR (IC7402), NAND (IC7400), EX-OR (IC7486).
Theory:
Logic gates:-
Any digital system can be constructed by using three types of logic gates.
So they are called as basic gates. These gates are AND gate, OR gate and NOT
gate. There also exist other logical gates, like NAND, NOR, XOR & XNOR
gates. So in this experiment we are going to verify truth tables of all gates. The
basic operations are described below.
AND Operation:-
A circuit which perform the AND operation is as shown in fig(a). Digital
signals are applied at the i/p terminals marked as A,B…N. The o/p is obtained at
the o/p terminal Y and it is a digital signal.
The AND operation is defined as “The o/p of an AND gate is 1, if and only if all
the i/p’s are 1”. Mathematically it is written as
Y=A AND B……AND N
Y=A.B……N
For two i/p
Y = A.B (Boolean equation of 2 i/p AND gate)
AND gate is used to perform logical multiplication.
Logic symbol of AND Gate:
Fig(a)
AND GATE (7408):- PIN configuration and Truth Table
Dept. of CSE (S E)
SEM-I(2014-15)

OR Operation:-
The circuit which performs the OR operation is as shown in fig(b). The
OR operation is defined as “The o/p of an OR gate is 1, if and only if one or
more of it’s i/ps are 1”. Mathematically it is written as
Y=A OR B……OR N
Y=A+B+…+N
For two i/p OR gate
Y=A+B (Boolean equation of 2 i/p OR gate)
It is used to perform logical addition operation.
Logic symbol of OR Gate:-
Fig(b)
OR GATE(7432) :PIN configuration and Truth Table
NOT Operation:-
The circuit which performs the NOT operation is as shown in fig(c). The
NOT gate is an electronic circuit that produces an inverted version of the input
6

logic at it’s output. It is also known as an inverter. If the input variable is A, then
inverted output is known as NOT A. Its logical equation is written as
Y= NOT A
Y=A
And read as “Y equal to NOT A” or “Y is equal to compliment of A.”
Symbol of NOT Gate:
Fig(c)
NOT GATE( 7404): PIN configuration and Truth Table
NAND Operation:-
The Logic NAND Gate is a combination of the digital logic AND gate
followed by an inverter or NOT gate connected in series. The NAND
(Not – AND) gate has an output that is normally at logic level “1” and only goes
“LOW” to logic level “0” when ALL of its inputs are at logic level “1”. The
Logic NAND Gate is the reverse or “Complementary” form of the AND gate.
Its logical equation is written as 
Y=
Symbol of NAND gate:-
Dept. of CSE (S E)
SEM-I(2014-15)

Fig(d)
NAND GATE(7400LS): PIN configuration and Truth Table
NOR Operation:-
The Logic NOR Gate or Inclusive-NOR gate is a combination of the
digital logic OR gate followed by inverter or NOT gate connected together in
series. The NOR (Not – OR) gate has an output that is normally at logic level
“1” and only goes “LOW” ( i.e. to logic level “0” )when ANY of its inputs
is/are at logic level “1”. The Logic NOR Gate is the reverse or
“Complementary” form of the OR gate.
Its logical equation is written as
Y=
Symbol of NOR gate:-
Fig(e)
NOR gate(74LS02):-PIN configuration and Truth Table
8

EXOR Operation:-
The output Y is true if either input A is true OR input B is true:
Y= (A AND NOT B) OR (B AND NOT A)
This is like an OR gate but excluding both inputs being true.
The output is true if inputs A and B are DIFFERENT.
Its logical expression can be written as
Y=AB+AB or
Y=A B
Symbol of the EXOR gate:-
Fig(f)
EX-OR GATE: (74LS86) :-PIN configuration and Truth Table
Specification of the TTL logic gate IC’s:-
1. Requires a +5 V power supply.
2. Gate INPUTS are driven by voltages having two nominal values, e.g. 0V
and 5V representing logic 0 and logic 1 respectively.
Dept. of CSE (S E)
SEM-I(2014-15)

3. The OUTPUT of a gate provides two nominal values of voltage only, e.g.
0V and 5V representing logic 0 and logic 1 respectively.
4. There is always a time delay between an input being applied and the output
responding.
Procedure :
1. Place the IC on IC trainer kit. Connect the Vcc and ground to respective
pins of IC.
2. Connect the inputs to the input switches provided on the IC trainer kit.
3. Connect the outputs to the switches of O/P LEDs .
4. Apply various combinations of inputs according to the truth table.
5. Observe conditions of output LEDs.
Conclusion:-
_____________________________________________________________
_____________________________________________________________
_____________________________________________________________
_____________________________________________________________
_____________________________________________________________
_____________________________________________________________
Answer the following questions:
1) How do you implement three-input and four-input EX-OR logic functions with the
help of two-input EX-OR gates?
2) How can you implement a NOT circuit using a two-input EX-OR gate?
3) How do you implement a three-input EX-NOR function using only two-input EX-NOR
gates?
10

Experiment No. – 02
Experiment Name Implementation of Boolean functions using Basic and
Universal Gates.
Experiment
Performed
Date -
Experiment
Submitted
Date -
Dept. of CSE (S E)
SEM-I(2014-15)

Experiment No. 2
Aim: Implementation of Boolean functions using Basic and Universal Gates.
Apparatus: IC trainer kit, patch chords, Power supply, AND(IC 7408), NAND(IC7400),
OR(IC 7432),NOR( IC7402), NOT (IC 7404).
Theory:
Any digital system can be constructed by using Basic and Universal Gates.
Boolean expressions can be expressed in one of two standard forms either in sum of product
or product of sum form.
Sum of product form(SOP):
It is nothing but sum of two or more product terms. In order to have product of two or more
variables AND gates are used. And output of all AND gate is applied to OR gate in order to
have sum of all product terms. We can implement the same form by using universal gates i.e.
NAND/ NOR gates.
Product of sum form(POS):
12

It consists of product of two or more sum terms. So sum terms are generated by using OR
gates. Outputs of all OR gates are given to one AND gate in order to generate this form. Same
form can be implemented by using NAND/ NOR gates( universal gates).
Implementation of SOP form:
Y= AB’+A’B
Realization using Basic gates
Realization using NAND gates
Realization using NOR gates
Implementation of POS form:
Y= (A+B’)(A’+B)
Realization using Basic gates
Dept. of CSE (S E)
SEM-I(2014-15)

Realization using NAND gates
Realization using NOR gates
Procedure:
1. Place the IC on IC trainer kit. Connect the Vcc and ground to respective pins of
IC.
3. Connect the outputs to O/P LEDs .
5. Observe conditions of output LEDs i.e. verify the truth table.
Conclusion:-
14

1) Implement the Boolean function
F= xy + x’y’+y’z
a. With AND, OR, and inverter gates
Ans:
b. With OR & inverter gates
Ans:
c. With AND & inverter gates
Ans:
d. With NAND & inverter gates
Ans:
Dept. of CSE (S E)
SEM-I(2014-15)

e. With NOR & inverter gates
Ans:
16

Experiment Name
Implementation of reduced Boolean functions (K – map
technique) from Assignment No. 2 using basic and
universal gates.
Experiment
Performed
Date -
Experiment
Submitted
Date -
Experiment No. 3
Aim: Implementation of reduced Boolean functions (K – map technique) using basic and
universal gates.
Apparatus: IC trainer kit, patch chords, Power supply, AND(IC 7408), OR(IC 7432), NOT
(IC 7404), NAND(IC7400), OR(IC 7432),NOR( IC7402).
Dept. of CSE (S E)
SEM-I(2014-15)

Theory:
Universal gates:-
Any digital system can be constructed by using NAND and NOR gates. So they are
called as universal gates. We will be designing the SOP and POS function using the universal
gates.
Sum of Products & Product of Sums
Any Boolean expression can be simplified in many different ways resulting in different
forms of the same Boolean function. All Boolean expressions, regardless of their forms, can
be converted into one of two standard forms; the sum-of-product form and the product-of
sum forms. Standardization makes the evaluation, simplification and implementation of
Boolean expression more systematic and easier.
The Sum-of-Product (SOP):
Writing functions in SOP form means that the inputs of each term are multiplied using AND
function, then all terms are added together using OR function. The variables in each term are
not necessarily all the variables of the function. For example, a SOP of F(A,B,C) may contain
a term that contains only the variable A but not B nor C, in such case the term is not in its
standard SOP form. Standard SOP term must contain all the function variables. From
Boolean algebra thermos (X+X'=1), then if the term is multiplied by (X+X'), it becomes in
the standard SOP form, but its value is not affected.
Example:
F(A,B,C)=A+BC'+A'BC --SOP
Ans: F(A,B,C)=A(B+B')(C+C')+BC'(A+A')+A'BC
F(A,B,C)=ABC+ABC'+AB'C+AB'C'+ ABC'+A'BC'+A'BC
F(A,B,C)=ABC+ABC'+AB'C+AB'C'+A'BC'+A'BC -SSOP
F(A,B,C)=Σm(111,110,101,100,010,011)
F(A,B,C)=Σm(2,3,4,5,6,7). - Minterms
The Product-of-Sum (POS):
Writing functions in POS form means that the inputs of each term are Added together using
OR function then all terms are multiplied together using AND function. The variables in each
term are not necessarily all the variables of the function. For example, a POS of F(A,B,C)
may contain a term that contains only the variable A but not B nor C, in such case the term is
18

not in its standard POS form. Standard POS term must contain all the function variables.
From Boolean algebra thermos (X.X'=0), then if the term is added to (X.X'), it becomes in the
standard POS form, but its value is not affected.
Example:
F(A,B,C)=A.(B+C').(A'+B+C')
Ans: F(A,B,C)=[A+(B.B')+(C.C')].[(B+C')+(A.A')].(A'+B+C')
F(A,B,C)=[(A+B+C).(A+B+C').(A+B'+C).(A+B'+C')].[(A+B+C').(A'+B+C')].
(A+B+C')
F(A,B,C)=(A+B+C).(A+B+C').(A+B'+C).(A+B'+C').(A'+B+C').
F(A,B,C)=πM(000,001,010,011,101)
F(A,B,C)=πM(0,1,2,3,5).
Karnaugh Maps
A Boolean function can be represented by a Karnaugh map in which each cell corresponds to
a minterm. The cells are arranged in such a way that any two immediately adjacent cells
correspond to two minterms of distance 1. There is more than one way to construct a map
with this property.
For a function of two variables, say, f(x, y),
For a function of three variables, say, f(x, y, z)
For a function of four variables: f(w, x, y, z)
Dept. of CSE (S E)
SEM-I(2014-15)

PART A:
SOP Implementation using basic and universal gates.
F(A,B,C,D)=Σm(0,2,5,7,8,9,10,12,13,15).
Truth Table:
A B C D Y
K-map for SOP implementation:
20

Circuit diagram for SOP function using basic gates:
Circuit diagram for SOP function using NAND gate only:
PART B:
POS Implementation using basic and universal gates
F(A,B,C,D)=πM(3,4,5,6,7,9,11,12,13,14,15).
Truth Table:A
B C D Y
Dept. of CSE (S E)
SEM-I(2014-15)

K-map for POS implementation:
Circuit diagram for POS function using basic gates:
Circuit diagram for POS function using NOR gate only:
22

Procedure:
1. Place the IC on IC trainer kit. Connect the Vcc and ground to respective pins of IC.
3. Connect the outputs to O/P LEDs .
Conclusion:-
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
1) Express the following function as a sum of minterms and product of maxterms:
F(A, B, C, D) = B’D+ A’D+ BD
Ans:
2) Convert each of the following expressions into sum of product & product of sum
a. (u+xw)(x+u’v)
Dept. of CSE (S E)
SEM-I(2014-15)

b. x’+ x( x+y’)(y+z’)
Ans:
3) Determine whether the following Boolean equation is true or false.
x’y’+x’z+x’z’=x’z’+y’z’+x’z
Ans:
4) What is the difference between canonical and standard form?
24

Experiment Name Implementation of half adder and full adder.
Experiment
Date -
Performed
Experiment
Submitted
Date -
Dept. of CSE (S E)
SEM-I(2014-15)

Experiment No. 4
Aim: Implementation of Half adder & Full Adder.
Apparatus: IC Trainer Kit, patch chords, power supply, IC7486 (EX-OR), IC74LS08,
IC74LS32.
Theory:
Half adder:
A logic circuit for addition of two 1-bit numbers is referred to as half adder. Here A and B
are two inputs and sum and carry are the two outputs.
Logic circuit of Half adder
Truth table of Half adder:
A B Sum Carry
Equation for sum & carry:
Sum= Carry=
Full adder:
Half adder can be used to add two single bit numbers & it doesn’t consider carry from the
previous addition. If you want to add two or more bits together it becomes slightly harder. In
this case, we need to create a full adder circuits. A full adder accepts inputs A and B plus a
carry-in (Cin) & gives outputs sum(S) and carry(C). Once we have a full adder, then we can
string eight of them together to create a byte-wide adder and cascade the carry bit from one
adder to the next. The logic table for a full adder is slightly more complicated than the tables
we have used for half adder, because now we have 3 input bits. The truth table and the circuit
26

diagram for a full-adder is shown in Figure. If you look at the S bit, it is 1 if an odd number
of ones are present, i.e., S is the XOR of the three inputs. The full adder can be realized as
shown below. Notice that the full adder can be constructed from two half adders and an OR
gate.
Basic Block for Full adder using Half adder and OR gate:
Basic block for Full adder using two half adder and OR gate
Circuit diagram of full adder:
Full adder using two half adder and OR gate
Truth table for Full Adder:
INPUTS OUTPUTS
A B Cin S C
Dept. of CSE (S E)
SEM-I(2014-15)

K-map for SUM (S) = Σm K-Map for CARRY (C) =Σm(
Simplified equation for sum and carry:
S= C=
Procedure :
2. Connect the ICs properly to power supply (pin 14) and ground (pin 7) following the
schematics for different ICs.
4. Connect the outputs to output LEDs .
5. Turn on power to your experimental circuit.
8. When you are done, turn off the power to your experimental circuit.
Conclusion:
________________________________________________________________________________________
_________________________________________________________________________________________
_________________________________________________________________________________________
_________________________________________________________________________________________
_
_________________________________________________________________________________________
28

_
_________________________________________________________________________________________
_
1) Design a combinational circuit with three inputs, x , y , and z , and three outputs, A, B , and C .When the
binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the binary input is 4, 5, 6, or 7,
the binary output is two less than the input.
2) Using four half adders design a full subtractor circuit incrementer. (A circuit that adds one to four bit
binary number)
Dept. of CSE (S E)
SEM-I(2014-15)

3) Assume that the exclusive-OR gate has a propagation delay of 10 ns and that the AND or OR gates have
a propagation delay of 5 ns. What is the total propagation delay time in the four-bit carry look ahead
adder?
Experiment Name Implementation of half subtractor and full subtractor.
Experiment
Date -
Performed
30

Experiment
Submitted
Date -
Experiment No. 5
Aim: Implementation of Half subtractor & Full subtractor.
Apparatus: Trainer Kit, patch chords, power supply, IC7486 (EX-OR), IC74LS08,
IC74LS32 and IC74LS04.
Theory:
Half subtractor:
A logic circuit for subtraction of two 1-bit numbers is referred to as half subtractor. Here A
and B are two inputs and difference and borrow are the two outputs.
Logic circuit of Half subtractor
Truth table of Half subtractor:
Dept. of CSE (S E)
SEM-I(2014-15)

A B Difference borrow
FULL SUBSTRACTOR:
Half subtractor subtracts one bit number from other number but it doesn’t consider borrow
from the previous subtraction, in order to overcome this problem full subtractor can be used.
A full subtractor circuit accepts a minuend (A) and the subtrahend (B) and a borrow (Bin) as
inputs from a previous subtraction and has two outputs subtraction and borrow output. A full
subtractor circuit can be realized by combining two half subtractor circuits and an OR gate as
shown in Fig.
Basic Block for Full subtractor using Half subtractor and OR gate:
Basic block for Full subtractor using two half subtractor and OR gate
Circuit diagram of full subtractor:
Logic circuit of Full subtractor
32

Truth table for Full Subtractor
INPUTS OUTPUTS
A B Bin D Bout
K-map for Difference(D)=Σm
K-Map for Barrow (Bout)=Σm
D= B=
Procedure :
Dept. of CSE (S E)
SEM-I(2014-15)

2. Connect the ICs properly to power supply (pin 14) and ground (pin 7) following the
schematics for different ICs.
4. Connect the outputs to output LEDs .
5. Turn on power to your experimental circuit.
8. When you are done, turn off the power to your experimental circuit.
Conclusion:
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
1) Given the relevant Boolean expressions for half-adder and half-subtractor circuits,
design a half adder–subtractor circuit that can be used to perform either addition or
subtraction on two one-bit numbers. The desired arithmetic operation should be
selectable from a control input.
34

2) Write the simplified Boolean expressions for DIFFERENCE and BORROW outputs.
Experiment Name Implementation of parity checker.
Dept. of CSE (S E)
SEM-I(2014-15)

Experiment
Performed
Date -
Experiment
Submitted
Date -
Experiment No. 6
Aim: Implementation of parity checker.
Apparatus: Trainer Kit, patch chords, power supply, IC7486(EX-OR), IC74LS04.
Theory:
The most common error detection code used is the parity bit. A parity bit is an extra bit
included with a binary message to make the total number of 1's either odd or even. In case of
even parity, the parity bit is chosen so that the total number of 1's in the coded message is
even. Alternatively, odd parity can be used in which the total number of 1's in the coded
message is made odd. During transfer of information, the message at the sending-end is
applied to a parity generator where the parity pit is generated. At the receiving-end a parity
checker is used to detect single bit error in the transmitted data word by regenerate the parity
bit in the same fashion as the generator and then compare with the parity bit transmitted.
Circuit diagram of even parity generator and checker:
36

Circuit diagram of odd parity generator and checker:
Procedure:
1. Derive the wiring diagram for the circuit in Figure.
2. Collect all IC chips necessary to build the circuit from the IC drawers.
3. Bring some connection wires with varying lengths.
4. Insure that the power switch of the IC trainer is turned off.
5. Plug the IC chips into the proper sockets.
6. Connect the voltage supply and ground lines to the chips.
7. Starting from left to right connect the outputs of one IC to the input of another ICs
according to your wiring diagram.
8. Once all connections have been done, turn on the power switch of the IC trainer.
9. Produce a single-bit error and verify the correct functioning of the Parity Checker
circuit.
10. After finishing the experiment, turn off the power switch and disconnect the wires
and take out all IC chips from the trainer.
Dept. of CSE (S E)
SEM-I(2014-15)

Conclusion:
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
1)List the applications of parity generator and checker?
2) Add a parity bit next to the LSB of the following hexadecimal codes to form even parity:
0111, 1101, 1010, 1111, 1000, 0000.
Experiment Name
Implementation of flip flops using NAND/NOR gates
S-R Flip flop
D flip flop
J-K Flip flop
T Flip flop
Experiment
Performed
Date -
38

Experiment
Submitted
Date -
Experiment No. 7
Aim: Implementation of flip flops using NAND/NOR gates-S-R Flip flop,D flip flop, J-K
Flip flop, T Flip flop.
Apparatus: Trainer Kit, patch chords, IC 7408, IC 7404, IC 7402, IC 7400.
Theory:
Logic circuits that incorporate memory cells are called sequential logic circuits; their output
depends not only upon the present value of the input but also upon the previous values.
Sequential logic circuits often require a timing generator (a clock) for their operation. The
latch (flip-flop) is a basic bi-stable memory element widely used in sequential logic circuits.
Usually there are two outputs; Q and its complementary value. Some of the most widely used
latches are listed below.
SR LATCH: an S-R latch neither consists of two cross-coupled NOR gates. An S-R flip-flop
can also be design using cross-coupled NAND gates as shown. The truth tables of the
circuits are shown below. A clocked S-R flip-flop has an additional clock input so that the S
and R inputs are active only when the clock is high. When the clock goes low, the state of
flip-flop is latched and cannot change until the clock goes high again. Therefore, the clocked
S-R flip-flop is also called “enabled” S-R flip-flop.
Dept. of CSE (S E)
SEM-I(2014-15)

A D latch combines the S and R inputs of an S-R latch into one input by adding an inverter.
When the clock is high, the output follows the D input, and when the clock goes low, the state
is latched. A S-R flip-flop can be converted to T-flip flop by connecting S input to Q’ and R to
Q.
Flip flop is a bistable, one bit memory element. There are four types of Flip flops:
1. SR flip flop:
By adding gates to the inputs of the basic circuit, the flip-flop can be made to respond to
input levels during the occurrence of a clock pulse. Note that the clock signal is a square
wave signal and the signal prevents the flip-flops from changing the states until the right
time occurs. The clocked RS flip-flop using NAND gates are shown in following Fig.
Circuit diagram and truth table of SR flip-flop:
2. D flip flop:
The D (Delay) flip-flop is used for storing the information. It is basically an RS flip-flop
with an inverter in the R input. Fig. 2 shows a clocked D flip-flop. NAND gates 1 and 2
from a basic RS flip-flop and gates 3 and 4 modify it into a clocked RS flip-flop. The D
input is to the S input and its complement through gate 5 is applied to the R input. The D
flip-flop is often called a ‘delay flip-flop’. The word ‘delay’ describes what happens to the
data or information at input D. In other words, the data, i.e. 0 or 1 at the input D is
delayed by one clock pulse from getting to output Q.
40

Circuit diagram and truth table of D flip-flop:
3. JK flip flop:
The JK flip-flop has the features of all other flip-flops, and hence it can also be
considered as ‘Universal’ flip-flop. This JK flip-flop is a refinement of the RS flip-flop.
The indeterminate state (when R=S=1) of the RS type is defined in the JK type. In that
condition the state of the output is changed; i.e. the complement of the previous state is
available. In other words, if the previous state of the output Q is 0; it becomes 1; and vice
versa. The logic diagram of a clocked JK flip-flop is shown in Fig. 3. Inputs J and K
behave like inputs S and R to set and reset the flip-flop. Note that in a JK flip-flop, the
letter j is for set and the letter K is for reset.
Circuit diagram and truth table of JK flip-flop:
Dept. of CSE (S E)
SEM-I(2014-15)

4. T flip flop:
The single input version of the JK flip-flop is ‘T (toggle) flip-flop’ and it is obtained from
a JK flip-flop if both inputs are tied together. The name T comes from the ability of the
flip-flop to ‘toggle’ or change the state. Generally T flip-flop IC’s are not available. It can
be realized using JK, SR, or D flip-flop. Following figure shows the logic diagram of a
clocked T flip-flop; which has only one input referred to as T-input.
Circuit diagram and truth table of T flip-flop:
PROCEDURE:
1. Make the connection as shown in the figures.
2. Apply the inputs and clock pulse.
3. Verify the output column from the truth table.
CONCLUSION:
___________________________________________________________________________
___________________________________________________________________________
42

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
1) If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in
cascade is______
Ans:
2)Determine the output frequency for a frequency division circuit that contains 12 flip-flops
with an input clock frequency of 20.48 MHz.
Ans:
3) How many flip-flops are required to produce a divide-by-128 device?
Ans:
4) A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is____
Ans:
5)As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must
be_____
Ans:
Dept. of CSE (S E)
SEM-I(2014-15)

Experiment Name Implementation of 3 bit Asynchronous counter.
Experiment
Date -
Performed
Experiment
Submitted
Date -
44

Experiment No. 8
Aim: Implementation of 3 bit Asynchronous counter.
Apparatus: IC 7476, connecting wires, patch chords, Trainer Kit.
Theory:
We will now consider a 3-bit binary up-counter, which belongs to the class asynchronous
counter circuits and is commonly known as a ripple counter. Following figure shows a 3-bit
counter, which has been implemented with three J-Kflip-flops. When clock pulses are applied
to a ripple counter, the counter progresses from state to state and the final output of the flip-flop
in the counter indicates the pulse count. The circuit recycles back to the starting state and
starts counting all over again. The number of states of which this counter is capable is 23 or 8.
This counter is also referred to as a modulo 8 (or divide by 8) counter. Since a flip-flop has
two states, a counter having n flip-flops will have 2n states. You will notice from the diagram
that the normal output, Q of each flip-flop is connected to the clock input of the next flip-flop.
The JK inputs of all the flip-flops, which are held high to enable the flip-flops to toggle
(change their logic state) at every transition of the input pulse from 1 to 0. The circuit is so
arranged that flip-flop B receives its clock pulse from the QA output of flip-flop A and, as a
consequence, the output of flip-flop B will change its logic state when output QA of flip-flop
A changes from binary 1 to 0. This applies to all the other flip-flops in the circuit. It is thus an
asynchronous counter, as all the flip-flops do not change their logic state at the same time.
Let us assume that all the flip-flops have been reset, so that the output of the counter at the
start of the count is 000 as shown in the first row of Table. Also refer to Fig. which shows the
output changes for all the flip-flops at every transition of the input pulse from 1 to 0.
Dept. of CSE (S E)
SEM-I(2014-15)

Circuit diagram of 3-bit asynchronous up counter:
Pin configuration of IC7476
46

Truth table for 3-bit asynchronous up counter:
Timing diagram for 3-bit asynchronous counter:
Dept. of CSE (S E)
SEM-I(2014-15)

Procedure:
1) Make the connection as per circuit diagram.
2) Apply the clock .
3) Connect the outputs to the switches of O/P LEDs and observe conditions of LEDs.
4) Note the readings from QA ,QB,QC, and make the observation table.
Conclusion:
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
1) It is desired to design a binary ripple counter that is capable of counting the number of
items passing on a conveyor belt. Each time an item passes a given point, a pulse is
generated that can be used as a clock input. If the maximum number of items to be
counted is 6000, determine the number of flip-flops required.
Ans:
48

2) A flip‐flops has a 3 ns delay from the time the clock edge occurs to the time the output is
complemented. What is the maximum delay in a 10‐bit binary ripple counter that uses these
flip‐flops? What is the maximum frequency at which the counter can operate reliably?
Ans:
Experiment Name Implementation of
Dept. of CSE (S E)
SEM-I(2014-15)

a. Boolean functions from Assignment No. 2 using
multiplexer ICs.
b. Full adder using 4:1 multiplexers IC.
Experiment
Performed
Date -
Experiment
Submitted
Date -
Experiment No. 9
Aim: - Implementation of a. Boolean functions from using multiplexer ICs.
b. Full adder using 4:1 multiplexers IC.
Apparatus: IC 74153, IC 74151 connecting wires, patch chords, Trainer Kit.
Theory:
Multiplexers are very useful components in digital systems. They transfer a large number of
information units over a smaller number of channels, (usually one channel) under the control
of selection signals. Multiplexer means many to one. A multiplexer is a circuit with many
inputs but only one output. By using control signals (select lines) we can select any input to
the output. Multiplexer is also called as data selector because the output bit depends on the
input data bit that is selected. The general multiplexer circuit has 2n input signals, n
control/select signals and 1 output signal.
50

Block diagram of multiplexer:
Pin configuration of IC 74151
IC 74151 MUX (8:1 MULTIPLEXER)
a. Implementation of logic function
F(A,B,C,D)=Σm(2,4,6,7,9,10,11,12,15) using only one 8:1 MUX (IC 74151)
Truth table:
I0 I1 I2 I3 I4 I5 I6 I7
A
Output
Circuit Diagram for Given function:
Dept. of CSE (S E)
SEM-I(2014-15)

b)To design & implement Full Adder Using 4 : 1 MUX – IC 74153:
Truth table of FULL ADDER :
INPUTS OUTPUTS
A B Cin S C
Sum = Σm ( )
Carry = Σm ( )
Circuit Diagram of Full Adder using 4 : 1 MUX - IC 74153
52

For Sum:
For carry:
Procedure :
PART A: Implementation of logic function
1) Connect I0 to I7 data inputs to the input switches of trainer kit.
Dept. of CSE (S E)
SEM-I(2014-15)

2) Connect enable pin no.7 to ground which is active low.
3) Connect select inputs to the input switches of trainer kit.
4) Connect output Y (pin no.5) to the output LED to observe the output.
5) Connect supply of + 5V to trainer kit.
PART B: Implementation of full adder
1) To implementing SUM of full adder connect I0, I1,I2 and I7 to +vcc and remaining
data i/p lines are connected to GND.
2) Connect pin no.7 to GND (Active low).
3) Connect logic variable X, Y,Z to select input S2, S1, S0 respectively.
4) Take SUM output from Y (pin no 5) for all combination of logic variable X,Y,Z.
5) Similarly, for Implementation of CARRY of full adder I3, I5,I6 and I7 to +vcc and
remaining data i/p lines are connected to GND.
6) And observe the output at Y (pin no.5).
7) For implementation of four variable ( A,B,C ,D) logic function using 8:1 MUX
prepare truth table which indicate connection of 4th variable as uncomplement or
complement combination of variable A .
8) Remaining three variables acts as select lines.
9) Observe the output at Y (pin no.5).
Conclusion:
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
1) Name the circuit for parallel to serial and serial to parallel conversion?
54

Ans:
2) What are the applications of multiplxer and demultiplexer?
Ans:
3) Design, construct, and test a circuit which uses an 74151 to implement a
sum-of-products expression:
Y = f (A,B,C) = A’B’C’ + A’BC + ABC’ + ABC
4)Design, construct a circuit which uses an 74151 to implement the
logic function specified in the truth table
Dept. of CSE (S E)
SEM-I(2014-15)

Experiment Name Implementation of Mod 10 (Decade) Counter using IC
7490.
Experiment
Performed
Date -
Experiment
Submitted
Date -
56

Experiment No. 10
Aim: Implementation of Mod 10 (Decade) Counter using IC 7490.
Apparatus: IC 7490, IC 7400 , patch chords, power supply, connecting wires etc.
Theory :
7490 Decade counter:
All asynchronous counter ICs are falling edge triggered.
It has MOD-2 and MOD-5 counter sections.
The 7490, like the 7493, is another 4-bit ripple counter. However, its flip-flops are internally
connected to provide MOD-2 (count-to-2) and MOD-5 (count-to-5) counter sections. Again,
each section uses a separate clock: input A (clk0) for MOD-2 and input B (clk1) for MOD-5.
By connecting QA to Input B and using input ‘A’ as the single clock input, a MOD-10 counter
(decade or BCD counter) can be created. When RESET inputs R0(1) and R0(2) are set high,
the counter’s outputs are reset to “0000”—provided that SET inputs Rg(1) and Rg(2) both
are not high (the SET inputs override the RESET inputs).
Pin configuration of IC 7490
Dept. of CSE (S E)
SEM-I(2014-15)

Logic diagram for IC7490 with MOD-2 and MOD -5 counter
Function table for IC7490:
Reset/Set inputs Outputs
R0(1)
Rg(1)
R0(2)
Rg(2)
QD QC QB QA
H H L L L L L L
H H X L L L L L
X X H H H L L H
L X L X COUNTING
X L X L COUNTING
L X X L COUNTING
X L L X COUNTING
When Rg(1) and Rg(2) are high, the outputs are set to QA = 1, QB = 0, QC = 0, and QD = 1. In
the MOD-10 configuration, this means that the counter is set to 9 (binary 1001). This master
set feature comes in handy if you wish to start a count at 0000 after the first clock transition
occurs (with master reset, the count starts out at 0001).
Truth table
Clock QD QC QB QA
01
58

23456789
10
7490 as decade counter :
Procedure: Method 1
1) Connect input frequency to be divided at input A(14).
2) Connect output of MOD-2 (i.e. QApin 12) to input B(1).
3) Take output at QD (11).
Note: Output frequency is input frequency divided by 10, but is rectangular in shape.
Procedure: Method 2
1) Connect input frequency to be divided at input B(1).
2) Connect output of MOD-5 (i.e. QD pin 11) to input A(14).
3) Take output at QA (12).
Note: Output frequency is input frequency divided by 10, but is a square wave.
MOD 10 Counter
Dept. of CSE (S E)
SEM-I(2014-15)

Design of MOD 5
Procedure:
1. Connect the trainer to the mains and switch on the power supply, measure the output of
the regulated power supply, that is, + 5V.
2. Connect R0(1), R0(2), Rg(1) and Rg(2) as per the mod counter which we have to design.
3. For MOD-10 counter connect R0(1), R0(2), Rg(1) and Rg(2) tologic zero.
4. For MOD-7 counter connect QC, QB and QA to the R0(1), R0(2) via AND gate or using
two NAND gate because RESET pins are active high , and Rg(1) and Rg(2) to logic ‘0’.
5. Similarly for MOD-5 counter connect QC and QA directly to the R0(1), R0(2) or via
AND gate.
6. Connect pulse output to A input and short B input and QA output.
7. Verify the counter outputs as per truth tables.
Conclusion:
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
_______________
1) A 4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns each.
The maximum possible time required for change of state will be
Ans:
60

2) How many flip‐flop will be complemented in a 10‐bit binary ripple counter to reach the
next count after the following counts?
a)1001100111 (b) 1111000111 (c) 0000001111
Ans:
3) In a 7490 IC, if QD output is connected to A input and the pulses are applied at B input,
find the count sequence of the Q outputs.
Experiment Name Implementation of 7 segment display using
decoder/driver7447 & 7448.
Experiment
Performed
Date -
Experiment
Submitted Date -
Dept. of CSE (S E)
SEM-I(2014-15)

Experiment No. 11
AIM: Implementation of 7 segment display using decoder/driver IC 7447 & IC 7448.
Apparatus: IC7447, IC 7448, Patch chords, Trainer Kit
Theory:
The Light Emitting Diode (LED) finds its place in many applications in these modern
electronic fields. One of them is the Seven Segment Display. Seven-segment displays
contains the arrangement of the LEDs in “Eight” (8) passion, and a Dot (.) with a common
electrode, lead (Anode or Cathode). The purpose of arranging it in that passion is that we can
make any number out of that by switching ON and OFF the particular LED's. Here is the
block diagram of the Seven Segment LED arrangement.
The Light Emitting Diode (LED), finds its place in many applications in this modern
electronic fields. One of them is the Seven Segment Display. Seven-segment displays
contains the arrangement of the LEDs in “Eight” (8) passion, and a Dot (.) with a common
electrode, lead (Anode or Cathode). The purpose of arranging it in that passion is that we can
make any number out of that by switching ON and OFF the particular LED's. Here is the
block diagram of the Seven Segment LED arrangement.
62

Note that inputs ABCD = 1010 to ABCD = 1111 corresponds to illegal inputs. The designer
may wish to treat these inputs as “don’t care” or perhaps generate a blank display or special
unique symbols. If the illegal inputs are treated as “don’t care”, the truth table would look as
follows.
Pin Configuration of IC 7447 & IC 7448:
Truth Table for IC7448:
Inputs Outputs
A B C D a b C d e f G
Dept. of CSE (S E)
SEM-I(2014-15)

Truth Table for IC7447:
Inputs Outputs
A B C D A b C d e f G
Circuit for driving single seven segment display using IC 7447 & IC 7448:
64

Note that the common-cathode display has all cathodes common (tied together) to ground.
Thus, a HIGH input “forward biases” the diode and it emits light. (A diode is forward biased
when a positive voltage is placed across it from anode to cathode.) The common-anode
display, on the other hand, has all anodes common (tied together) to the supply voltage. Thus,
a LOW input forward biases the diode and it emits light.
PROCEDURE:
1) Check all the components for their working.
2) Insert the appropriate IC into the IC base.
3) Make connections as shown in the circuit diagram.
4) Verify the Truth Table and observe the outputs.
Conclusion:
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
Dept. of CSE (S E)
SEM-I(2014-15)

Cse

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Viewers also liked

Viewers also liked (8)

Similar to Cse

Similar to Cse (20)

Recently uploaded

Recently uploaded (20)

Cse