A hardware description language enables a precise, formal description of an electronic circuit that allows for the automated analysis and simulation of an electronic circuit. It also allows for the synthesis of an HDL description into a netlist (a specification of physical electronic components and how they are connected together), which can then be placed and routed to produce the set of masks used to create an integrated circuit.

1. Content of the Course
• Overview of VHDL
• Entity and architecture description
• Signal and Process assignments
• Design of Combinational digital circuits
• Example digital circuits Programming
12/29/2023 VAC VEC

2. Overview of VHDL
• VHSIC Hardware Description Language
• VHSIC:
Very High Speed Integrated Circuits
• VHDL
USA Department of Defense
IEEE Std 1076-1993
• Verilog
IEEE Std 1364-1995
• Super Verilog
• SystemC
• SpecC
12/29/2023 VAC VEC
HW & SW

3. The Y-Diagram Design Paradigm
12/29/2023 VAC VEC
Design is
structured around
a hierarchy of
representations
HDLs can
describe
distinct aspects
of a design at
multiple levels
of abstraction

4. 4
Design Abstraction Levels

5. 5
Role of HDLs
• System description and documentation
• System simulation
• System synthesis
V Very High Speed Integrated Circuit
H Hardware
D Description
L Language

6. 6
Role of HDLs
• Design Specification
– unambiguous definition of components, functionality
and interfaces
• Design Simulation
– verify system/subsystem performance and functional
correctness prior to design implementation
• Design Synthesis
– automated generation of a hardware design

7. 7
HDL Benefits
• Technology independence
– portability
– Reuse
• Interoperability between multiple levels of abstractions
• Cost reduction
• Higher Level of Abstraction (hiding details)
– The design task become simpler
– The design is less error prone
– Productivity is increased

8. 8
Levels of Abstraction
Behavioral
RTL
Structural
High
Intermediate
Low

9. 9
HDL style vs. application
• High Level Modeling (Behavioral style)
• Design Entry (Structural & RTL styles)
• Simulation (Behavioral style)
– validation by mean of a test bench
generate
stimuli
observe
responses
instantiate
design to
test
dut.vhd
TESTBENCH
dut_tb.vhd

10. 10
Modeling Digital Systems
 What aspects do we need to consider to describe a
digital system ?
 Interface
 Function
 Performance (delay/area/costs/…)
abstraction Levels

11. 11
Modeling Digital Systems
• What are the attributes necessary to describe a
digital systems ?
– events, propagation delays, concurrency
– waveforms and timing
– signal values
– shared signals

12. 12
Modeling Digital Systems
• Hardware description languages must provide
constructs for describing the attributes of a specific
design, and …
• Simulators use such descriptions for “mimicking”
the physical system behavior
• Synthesis compilers use such descriptions for
synthesizing manufacturable hardware that
conform to a given specification

13. 13
HDLs vs. Software Languages
Concurrent (parallel) Statements
vs.
Sequential Statements

14. 14
VHDL Design Organization
• Entity
the “symbol” (input/output ports)
• Architecture
one of the several possible implementation of the
design
• Configuration
binding between the symbol and one of the many
possible implementation.
Can be used to express hierarchy.

15. 15
VHDL Design Organization
• Libraries
logical units that are mapped to physical directories. The units of a library are called packages.
• Packages
repositories for type definitions, procedures, and functions
• Libraries and packages can be system defined or user defined
package
package
package body
specification of the
code blocks
declaration
package contents

16. 16
Design Units
• Primary design units (not dependent on other design units)
– Entity
– Configuration
– Package Declaration
• Secondary design units
– Package body
– Architecture
• Design units are arranged in files
• Now you know the layout of a VHDL program!

17. 17
Design Units
• Primary design units (not dependent on other design units)
– Entity
– Configuration
– Package Declaration
• Secondary design units
– Package body
– Architecture
• Design units are arranged in files
• Now you know the layout of a VHDL program!

18. 12/29/2023 VAC VEC
-- This is my first VHDL program
library IEEE;
use IEEE.std_logic_1164.all;
entity my_exor is
port (ip1 : in std_logic;
ip2 : in std_logic;
op1 : out std_logic
);
end my_exor;
entity declaration - describes the
boundaries of the object.
It defines the names of the ports, their
mode and their type.
my EXOR gate

19. 12/29/2023 VAC VEC
library IEEE;
use IEEE.std_logic_1164.all;
entity my_exor is
port (ip1 : in std_logic;
ip2 : in std_logic;
op1 : out std_logic
);
end my_exor;
Library : Collection of design
elements, type declarations, sub
programs, etc.
my EXOR gate

20. 12/29/2023 VAC VEC
library IEEE;
use IEEE.std_logic_1164.all;
entity my_exor is
port (ip1 : in std_logic;
ip2 : in std_logic;
op1 : out std_logic
);
end my_exor;
architecture my_exor_beh of my_exor is
begin
op1 <= (ip1 and (not ip2)) or
(ip2 and (not ip1));
end my_exor_beh;
Library : Collection of design
elements, type declarations,sub
programs, etc.
entity - defines the
interface.
Mode of the port :
It can be
in, out or inout
std_logic is the type of the port
It is defined in the IEEE library.
Any node of type std_logic can take
9 different values.
‘0’ , ’1’ , ’H’ , ’L’ , ’Z’ , ’U’ , ’X’ , ’W’ , ’-’
The architecture describes the
behaviour (function),
interconnections and the
relationship between different
inputs and outputs of the entity.
my EXOR gate

21. 12/29/2023 VAC VEC
architecture my_exor_beh of my_exor is
signal temp1 : std_logic;
signal temp2 : std_logic;
begin
......
end my_exor_beh;
Internal connections are made using signals.
Signals are defined inside the architecture.

22. 12/29/2023 VAC VEC
library IEEE;
use IEEE.std_logic_1164.all;
entity my_exor is
port (ip1 : in std_logic;
ip2 : in std_logic;
op1 : out std_logic
);
end my_exor;
architecture exor_w_sig of my_exor is
signal temp1, temp2 : std_logic;
begin
temp1 <= ip1 and (not ip2);
temp2 <= ip2 and (not ip1);
op1 <= temp1 or temp2;
end exor_w_sig;
configuration my_exor_C of my_exor is
for exor_w_sig
end for;
end my_exor_C;
my EXOR with internal signals

23. 12/29/2023 VAC VEC
• SUMMARY
• Introduction to:
• VHDL flow
• Comments
• Library declaration
• Entity declaration (ports, modes, std_logic type)
• Architecture
• Signal declarations
• Signal assignments
• Component declaration and instantiation
• Configuration statement