2. VHDL
• VHDL is Hardware Language
• Describes the behavior of an electronic circuit or system
• Full form VHDL is VHSIC HDL
or
Very High Speed Integrated Circuit Hardware Description
Language
• VHDL is only for Digital IC and not for Analog IC
• VHDL uses gate level design abstraction
3. History of VHDL
• VHDL was developed by Department of Defense – US
1980
• 1980-87= Department of Defense
• 1987 DOD permitted for commercial purpose and got
IEEE Std (1076)
• 1993 Revised Edition (not synthesizable in this period)
• 1996 Revised Further( It is synthesized language and
simulation tools were added)
4. VHDL vs. ‘C’ language
• VHDL is Concurrent Language while as ‘C’ is
sequential language.
• VHDL is synthesizable while as ‘C’ is not.
5. VHDL Capabilities
• It is case insensitive Language
• It is vendor independent (Xilinx, Altera, Modelsim.etc)
• It supports synthesis (VHDL to Netlist)
• It supports simulation i.e. in the absence of real system we
simulate the function by taking a model of the function
• It supports 9 value logic system
6. Program structure in VHDL
• Library
--- list of libraries
• Entity
---I/O pins of the circuit
• Architecture
--- VHDL code
7. Library Declarations
• Two lines of code are needed
– name of library and use clause
• Syntax
• Three different libraries
• ieee
• standard
• work
LIBRARY library_name;
USE library_name.package_name.package_part;
8. Library
• Library ieee;
Use ieee.std_logic_1164.all;
• Use ieee library
• Use Std_logic_1164 package of library
• Use above package completely
9. Entity
Specification of all input-output pins (ports)
interface to outside world
Syntax
Signal mode: IN, OUT, INOUT, BUFFER
IN- unidirectional (only read the signal)
OUT- unidirectional (only write to the signal)
ENTITY entity_name IS
PORT (
Port_name: signal_mode signal_type;
Port_name: signal_mode signal_type;
……….)
END entity_name;
Inputs and Outputs
Chip
A
B
C
D
E
10. Entity
• Entity is the building block of VHDL program. It is used
to declare input and output ports.
• Example :-
entity ABCD is
port ( a : in std_logic;
b : in std_logic;
c : out std_logic);
end ABCD;
11. Architecture
Description of how the circuit should behave
Syntax
Two parts:
Declarative part (optional): signals and
constants are declared here
Code part
ARCHITECTURE architecture_name OF entity_name IS
[declaration]
BEGIN
(code)
END architecture_name;
ChipA
B
C
D
EX
Y
12. Architecture
• It is the last and the third part of VHDL program. In this
part we are writing logic of program.
• Example
architecture myDEF of ABCD is
begin
output <= input1 and input2;
end myDEF;
13. Types of modeling style in VHDL
• Data flow modeling (Design Equations)
• Behavioral modeling (Explains Behavior)
• Structural modeling (Connection of sub modules)
• Hybrid modeling
15. Final code
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TEST IS
PORT (A,B,C,D : IN STD_LOGIC;
E : OUT STD_LOGIC);
END TEST;
ARCHITECTURE BEHAVIOR OF TEST IS
SIGNAL X,Y : STD_LOGIC;
BEGIN
X <= AAND B;
Y <= C AND D;
E <= X OR Y;
END BEHAVIOR;
