8085 interfacing with memory chips

Memory Interfacing.....T.Srikrishna, Asst Prof, GVP PG, Visakhapatnam
Memory
Memory is an essential element of a computer. Memory plays an important role in
saving and retrieving data. The performance of the computer system depends upon
the size of the memory. Memory is of following types:
1. Primary Memory / Volatile Memory.
2. Secondary Memory / Non Volatile Memory
1. Primary Memory / Volatile Memory: Primary Memory is internal memory of the
computer. RAM AND ROM both form part of primary memory. The primary memory
provides main working space to the computer.
Random Access Memory (RAM): The primary storage is referred to as random
access memory (RAM) because it is possible to randomly select and use any
location of the memory directly store and retrieve data
It is also called read/write memory. The storage of data and instructions inside the
primary storage is temporary. It disappears from RAM as soon as the power to the
computer is switched off.
The memories, which lose their content on failure of power supply, are known as
volatile memories .So now we can say that RAM is volatile memory.
Read Only Memory (ROM): There is another memory in computer, which is called
Read Only Memory (ROM). The storage of program and data in the ROM is

permanent. The ROM stores some standard processing programs supplied by the
manufacturers to operate the personal computer.
. The memories, which do not lose their content on failure of power supply, are
known as non-volatile memories. ROM is non-volatile memory.
PROM: There is another type of primary memory in computer, which is called
Programmable Read Only Memory (PROM). We know that it is not possible to
modify or erase programs stored in ROM, but it is possible for you to store your
program in PROM chip. Once the programmers’ are written it cannot be changed
and remain intact even if power is switched off. Therefore programs or instructions
written in PROM or ROM cannot be erased or changed.
EPROM: This stands for Erasable Programmable Read Only Memory, which
overcome the problem of PROM & ROM. EPROM chip can be programmed time and
again by erasing the information stored earlier in it. Information stored in EPROM
exposing the chip for some time ultraviolet light and it erases chip is reprogrammed
using a special programming facility. When the EPROM is in use information can
only be read.
Cache Memory: The speed of CPU is extremely high compared to the access time
of main memory. Therefore the performance of CPU decreases due to the slow
speed of main memory. To decrease the mismatch in operating speed, a small
memory chip is attached between CPU and Main memory whose access time is very
close to the processing speed of CPU. It is called CACHE memory. CACHE
memories are accessed much faster than conventional RAM. It is used to store
programs or data currently being executed or temporary data frequently used by the
CPU. It is also very expensive to have bigger size of cache memory and its size is
normally kept small.

Registers: The CPU processes data and instructions with high speed; there is also
movement of data between various units of computer. It is necessary to transfer the
processed data with high speed. So the computer uses a number of special memory
units called registers. They are not part of the main memory but they store data or
information temporarily and pass it on as directed by the control unit.
2. Secondary Memory / Non-Volatile Memory: Secondary memory is external and
permanent in nature. The secondary memory is concerned with magnetic memory.
Secondary memory can be stored on storage media like floppy disks, magnetic
disks, magnetic tapes, This memory can also be stored optically on Optical disks -
CD-ROM. The following terms comes under secondary memory of a computer are
discussed below:
Magnetic Tape: Magnetic tapes are used for large computers like mainframe
computers where large volume of data is stored for a longer time. In PC also you can
use tapes in the form of cassettes. The cost of storing data in tapes is inexpensive..
Magnetic Disk: We might have seen the gramophone record, which is circular like a
disk and coated with magnetic material. Magnetic disks used in computer are made
on the same principle. It rotates with very high speed inside the computer drive. Data
is stored on both the surface of the disk. Magnetic disks are most popular for direct
access storage device. Information is recorded on tracks of a disk surface in the form
of tiny magnetic spots. The presence of a magnetic spot represents one bit and its
absence represents zero bit. For Example-Floppy Disk.
Optical Disk: With every new application and software there is greater demand for
memory capacity. It is the necessity to store large volume of data that has led to the
development of optical disk storage medium.
Interfacing:

A microprocessor has to be interfaced with various peripherals to perform various
functions. Let's discuss about the Interfacing techniques in detail.
 We know that a microprocessor is the CPU of a computer.
 A microprocessor can perform some operation on a data and give the output.
But to perform the operation we need an input to enter the data and an output
to display the results of the operation.
Interfacing Types
There are two types of interfacing in context of the 8085 processor.
(a) Memory Interfacing.
(b) I/O Interfacing.
Memory Interfacing:
While executing an instruction, there is a necessity for the microprocessor to access
memory frequently for reading various instruction codes and data stored in the
memory. The interfacing circuit aids in accessing the memory.
Memory requires some signals to read from and write to registers. Similarly the
microprocessor transmits some signals for reading or writing a data.
But what is the purpose of interfacing circuit here?
The interfacing process involves matching the memory requirements with the
microprocessor signals. The interfacing circuit therefore should be designed in such
a way that it matches the memory signal requirements with the signals of the
microprocessor.
I/O Interfacing:
We know that keyboard and Displays are used as communication channel with
outside world. So it is necessary that we interface keyboard and displays with the
microprocessor. This is called I/O interfacing. In this type of interfacing we use
latches and buffers for interfacing the keyboards and displays with the
microprocessor.
Basic concepts of Memory Interfacing:
The programs and data that are executed by the microprocessor have to be stored in
ROM/EPROM and RAM, which are basically semiconductor memory chips.
Microprocessor need to access memory quite frequently to read instructions and
data stored in memory; the interface circuit enables that access.

Fig: 8085 interfacing with memory Chips
The interface process involves designing a circuit that will match the memory
requirements with the microprocessor signal.
Memory has certain signal requirements to read from and write into memory.
Similarly Microprocessor initiates the set of signals when it wants to read from and
write into memory.
 8085 has 16 address lines (A0 - A15), hence a maximum of 64 KB (= 216
bytes) of memory locations can be interfaced with it.
 The memory address space of the 8085 takes values from 0000H to FFFFH.
 The 8085 initiates set of signals such as IO/M, RD’ and WR’ when it wants to
read from and write into memory.
 Similarly, each memory chip has signals such as CE or CS (chip enable or
chip select), OE or RD’ (output enable or read) and WE or WR’ (write enable
or write) associated with it.
Generation of Control Signals for Memory: When the 8085 wants to read from
and write into memory, it activates IO/M, RD and WR signals as shown. Status of
IO/M, RD’ and WR’ signals during memory read and write operations
IO/M’ RD’ WR’ Operation
0 0 1 8085 reads data from memory
0 1 0 8085 writes data into memory
Using IO/M , RD and WR signals, two control signals MEMR (memory read) and MEMW
(memory write) are generated. Fig. 16 shows the circuit used to generate these signals.

 8085 places 16-bit address on address bus and with this address only one
register should be selected (only 11 low order address lines are required).
 Remaining 8085 address lines (A15-A11) should be decoded to generate chip
select.
 8085 provides two signal-IO/M’ and RD’– to indicate that is memory read
operation MEMR’. (Similarly signal-IO/M’ and WR’– indicates memory write
operation MEMW’).
Primary Function of memory interfacing is that the microprocessor should be able to
read from and write into a given register of a memory chip:
 Select the Chip
 Identify the register
 Enable the appropriate buffer.
.
MEMORY STRUCTURE AND ITS REQUIREMENTS
Structure of R/W Memory (RAM)
Figure Shows:
 2048 registers
 Register store 8-bits
 8 input, 8-output lines
 11 address lines (AD10-AD0), 1 chip select, 2 control lines to enable input
and output buffer.
 Internal decoder to decode address lines

Structure of ROM:
 EPROM: Chip must be programmed before it can be used as ROM.
 4096 (4K) registers.
 Register store 8-bits
 8 input lines
 Internal decoder to decode address lines.
 12 address lines (A11-A0), 1 chip select, 1 Read control Signal lines to enable
output buffer.
8085 Interfacing with Memory.

The following are the steps involved in interfacing memory with 8085 processor.
 First decide the size of memory requires to be interfaced. Depending on this
we can say how many address lines are required for it.
For example if you want to interface 4KB memory it requires 12 address
lines. Remaining 4 address lines can be used in address decoding.
 Depending on the size of memory required and given address range,
construct address decoding circuitry. This address decoding circuitry can be
implemented with NAND gates or decoders.
 Connect data bus of memory to processor data bus.
 Generate the control signals required for memory using IO/M’, WR’, RD’
signals of 8085 processor.
Example:
 Interface 4KB memory to 8085 with starting address A000H.
 4KB memory requires 12 address lines for addressing and 4 address lines are
used for address decoding
 Given that starting address for memory is A000H. So for 4KB memory ending
address becomes A000H+0FFFH (4KB) = AFFFH.
A0-A11 address lines are directly connected to address bus of memory chip.
A12-A15 are used for generating chip select signal for memory chip.
Address decoding circuit using 3X8 decoder:
A15 line is use for enabling 74x138 decoder chip. A12, A13, A14 lines are connected
to 74X138 chip as inputs. When theses lines are 010 output should be ‘0’. This is
provided at O2 pin of 74X138 chip.
Address decoding circuit using only NAND gates:

A15, A14, A13, A12 inputs should be 1010, for enabling the chip. So the circuit for
this is as shown above.
8085 Interfacing Circuit to interface EPROM:(using 3x8 Decoder)
 The 8085 address lines A11-A0 are connected to the pins A11-A0 of the
memory chip.
 Decoder decode A15-A12 and output O0 is connected to CE’ which is
asserted only when A15-A12 is 0000
 One control signal MEMR’ is connected to OE’ to enable output buffer
An address bus: this determines the location in memory that the processor will
read data from or write data to.
A data bus: this contains the contents that have been read from the memory
location or are to be written into the memory location.

A control bus: this manages the information flow between components
indicating whether the operation is a read or a write and ensuring that the operation
happens at the right time.
Example: Interfacing 64Kb EPROM with 8085:
Consider a system in which the full memory space 64kb is utilized for EPROM
memory. Interface the EPROM with 8085 processor.
 The memory capacity is 64 Kbytes. i.e
 2^n = 64 x 1000 bytes where n = address lines.
 So, n = 16.
 In this system the entire 16 address lines of the processor are connected to
address input pins of memory IC in order to address the internal locations of
memory.
 The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied
to ground).
 Since the processor is connected to EPROM, the active low RD pin is
connected to active low output enable pin of EPROM.
 The range of address for EPROM is 0000H to FFFFH.
8085 Interfacing RAM Memory Chip :
 11 Address lines A10-A0 to decode 2048K registers.
 Address lines A15-A11 are connected to decoder (which is enabled by IO/M’
signal in addition to the address lines A15 and A14).

 RD’ and WR’ signals are directly connected to memory chip.
 MEMR’ and MEMW’ need not to be generated separately (this technique save
two gates).
 Memory Address Ranges from 8800H to 8FFFH.
 A13-A11 (001) activate output O1 of decoder which is connected to CE’ of
memory chip and it is asserted only when IO/M’ is low.
Fig: Interfacing RAM Memory
Ex: Interfacing 32Kb EPROM and 32Kb RAM with 8085
 Consider a system in which the available 64kb memory space is equally
divided between EPROM and RAM. Interface the EPROM and RAM with
8085 processor.
 Implement 32kb memory capacity of EPROM using single IC 27256.
 32kb RAM capacity is implemented using single IC 62256.
 The 32kb memory requires 15 address lines and so the address lines A0 -
A14 of the processor are connected to 15 address pins of both EPROM and
RAM.
 The unused address line A15 is used as to chip select. If A15 is 1, it select
RAM and If A15 is 0, it select EPROM.
 Inverter is used for selecting the memory.
 The memory used is both Ram and EPROM, so the low RD and WR pins of
processor are connected to low WE and OE pins of memory respectively.
 The address range of EPROM will be 0000H to 7FFFH and that of RAM will
be 7FFFH to FFFFH.

Other Examples (Only for Reference purpose):
 Consider a system in which 32kb memory space is implemented using four
numbers of 8kb memory. Interface the EPROM and RAM with 8085 processor
 The total memory capacity is 32Kb. So, let two numbers of 8kb n memory be
EPROM and the remaining two numbers be RAM.
 Each 8kb memory requires 13 address lines and so the address lines A0- A12
of the processor are connected to 13 address pins of all the memory.
 The address lines and A13 - A14 can be decoded using a 2-to-4 decoder to
generate four chip select signals.
 These four chip select signals can be used to select one of the four memory
IC at any one time.
 The address line A15 is used as enable for decoder.
 The simplified schematic memory organization is shown.
Fig - Interfacing 16Kb EPROM and 16Kb RAM with 8085

 Consider a system in which the 64kb memory space is implemented using
eight numbers of 8kb memory. Interface the EPROM and RAM with 8085
processor.
 The total memory capacity is 64Kb. So, let 4 numbers of 8Kb EPROM and 4
numbers of 8Kb RAM.
 Each 8kb memory requires 13 address lines. So the address line A0 - A12 of
the processor are connected to 13address pins of all the memory lCs.
 The address lines A13, A14 and A]5 are decoded using a 3-to-8 coder to
generate eight chip select signals. These eight chip select signals can be
used to select one of the eight memories at any one time.
 The memory interfacing is shown in following figure
Address space partitioning in 8085
There are two techniques through which devices can be interfaced to
microprocessor.
1. Memory mapped I/O
2. Peripheral mapped I/O or I/O mapped I/O
Memory mapped I/O:
In memory mapped I/O scheme we can use only one address space. This
particular one address space is allocated to both memory and I/O devices.
In total memory addresses, some addresses are assigned to memories and
some to I/O devices. But we have to assign the address for I/O devices are
different from the addresses which have been assigned to memories.

In this scheme remember that I/O device is also treated as a memory location.
Now take a very good example, MOV C, M instruction would transfer one byte of
data from a memory location or it can also transfer an input device to the register
C, depending on whether the address in the H-L register pair is assigned to a
memory location or to an input device.
If H-L contains address of a memory location, data will be transferred from that
memory location to register C, while if H-L pair contains the address of an input
device, data will be transferred from that input device to register C.
I/O mapped I/O:
In this method separate address space is given to I/O devices. Each I/O
device is given an 8-bit address. Hence maximum 256 devices can be interfaced to
the processor. The address range for the I/O devices is 00H-FFH. I/O control signals
are used to perform read, write operations.
For reading data from I/O device or writing data to IO device IN, OUT
instructions needs to be used.
We know that Some CPUs provide one or more control lines like IO/ M line for
8085, which indicates the status of operation, is memory or I/O operation.
If we get the status of IO/ M’ line is high, it indicates I/O operation and when we
get low, it points to memory operation. in this case the same address may be
assigned to both memory and an I/O device depending on the status of IO/M
line.
The above scheme is referred as I/O mapped I/O scheme. Look in this scheme
two separate address spaces exist. One space is meant exclusively for memory
operations and the other for I/O operations.
The following figure shows, pictorially, both the schemes. Here it is assumed that
the system has a 64 KB of memory and 256 I/O space.

Memory Mapped I/O I/O Mapped I/O
In Memory Mapped I/O Address width is 1 6-bit. A0
to A15 are usedtogenerate address of thedevice.
MEMR and MEMW control signals are used to control
read and write I/O operationsrespectively.
Instructions available areSTA addr,LDA addr,LDAX rp,
STAX rp, ADD M, CMPM, MOV r, M, etc.
Data transfer takes place between any register and I/O
dev ice
In I/O Mapped I/O Address width is 8-bit. A0 to A15
lines are used togenerate address of the device.
IORand IOWcontrol signals are used tocontrol read and
write I/O operations respectively.
IN and OUT are the only availableinstructions.
Data transfer takes place between accumulator and I/O
dev ice.
dev ice.
Maximum number of I/O dev ices that can be addressed is
65536 (theoretically).
It requires more hardware circuitry because it decodes 16-
bit address.
Maximum number of I/O dev ices that can be addressed is
256.
It requires less hardwarecircuitry because it decodes 8-bit
address.
STACK.ORGANIZATION
Stack is a storage structure that stores information in such a way that the last item
stored is the first item retrieved. It is based on the principle of LIFO (Last-in-first-out).
The stack in digital computers is a group of memory locations with a register that
holds the address of top of element. This register that holds the address of top of
element of the stack is called Stack Pointer.
Stack.Operations:
The two operations of a stack are:
1. Push: Inserts an item on top of stack.
2. Pop: Deletes an item from top of stack.
In digital computers, stack can be implemented in two ways:
1. Register Stack
2. Memory Stack
Register Stack
A stack can be organized as a collection of finite number of registers that are used to
store temporary information during the execution of a program. The stack pointer
(SP) is a register that holds the address of top of element of the stack.
Memory Stack
A stack can be implemented in a random access memory (RAM) attached to a CPU.
The implementation of a stack in the CPU is done by assigning a portion of memory
to a stack operation and using a processor register as a stack pointer. The starting
memory location of the stack is specified by the processor register as stack pointer.

8085 interfacing with memory chips

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