56666

1. Prepared and presented by Dr. A. Islam
1
EC4205/EC203
Dr. A. Islam
Dept. of ECE
BIT, Mesra, Ranchi
Microprocessor and Microcontroller/DSD
Webcast link:
https://sites.google.com/a/bitmesra.ac.in/aminulislam/home
All announcement made through webpage: check back often
Students are welcome outside the class (right after class)

2. Prepared and presented by Dr. A. Islam
2
EC4205/EC203
Lecture notes based on material
• From me, Prof. (Dr.) R. Sukesh Kumar and following
text books:
1. Digital Computer Electronics, 2/e, by A. P. Malvino.
2. Microprocessor Architecture, Programming and Applications with 8085, by
R. S. Gaonkar.
3. Microprocessor and Interfacing, Programming of Hardware, by D. Hall.
4. Microprocessor and Peripherals, by S. P. Chowdhury and S. Chowdhury.
5. INTEL 8086/8088 Microprocessor, Architecture, Programming, Design
and Interfacing, 3/e, by B. S. Chhabra.
6. Microprocessor, Microcomputer and their Applications, 2/e, by A, K.
Mukhopadhyay.
7. The Intel Microprocessors 8086/888, 80186/80188, 80286, 80386, 80486,
Pentium and Pentium Pro processor – architecture, programming and
interfacing, 4/e, by B. B. Brey.
8. Microprocessors with applications in process control, by SI Ahson.
9. Microprocessors – theory and applications: Intel and Motorola, by M.
Rafiquzzaman.
Use the material without violating copyright act involved with original books.

3. Prepared and presented by Dr. A. Islam
3
Module-I: Outline
1. Revision of logic circuits with emphasis on control lines
2. SAP concepts with stress on timing diagrams
3. Microinstructions
4. Microprogramming
5. Variable machine cycle
6. Architecture of 8085 Processor
7. Functions of all signals
8. Bus concepts
9. Multiplexed and De-multiplexed Bus
10.Minimum system
Module – 5 (for EC203 DSD):
Design of simple computing machines: SAP-I concepts with stress on timing
diagrams, Microinstructions, Fetch and Execution cycle variable machine cycle,
Hardware control Matrix, Macroinstructions, Microprogramming, Bus concepts,
Multiplexed Minimum system. Pipelining concepts.

4. Prepared and presented by Dr. A. Islam
4
SAP concepts with stress on timing diagrams
• Program counter: On
reset it contains 0000.
It places the address
(onto the W bus during
T1 or address state) of
the instruction to be
fetched and executed.
• Input and MAR: It
includes address & data
switch registers. These
s/w registers allow to
send 4 address bits and
8 data bits to RAM.
MAR is part of SAP-1
memory. Address from
PC and IR gets latched
into MAR. A bit latter,
MAR applies this 4-bit
address to the RAM,
where a read operation
is performed.

5. Prepared and presented by Dr. A. Islam
5
SAP concepts with stress on timing diagrams
• RAM: In SAP-1
RAM is 16×8 bit
TTL 74189 static
RAM which is
programmed with
address and data
s/w registers
before a computer
run.

6. Prepared and presented by Dr. A. Islam
6
SAP concepts with stress on timing diagrams
• Instruction register:
When memory read
operation is
performed content of
addressed memory
location is loaded
into instruction
register on next +ve
clock edge.
• Its content is split
into two nibbles.
Upper nibble is a
two-state o/p that
goes to
controller/sequencer.
• The lower nibble is a
three-state o/p that is
placed onto W bus for
further reading and
placing onto MAR.

7. Prepared and presented by Dr. A. Islam
7
SAP concepts with stress on timing diagrams

8. Prepared and presented by Dr. A. Islam
8
SAP concepts with stress on timing diagrams
• Controller-
sequencer: When
CLEAR/START push-
button of debouncer
ckt is pressed a low
CLR_bar goes to PC,
(C29) start-the-clock-
flip-flop) and ring
counter. A high CLR
goes to instruction
register.
• This resets the PC to
0000 and wipes out
the previous content
of instruction
register. The
controller-sequencer
generates a 12 bit
control word of the
format shown on its
o/p

9. Prepared and presented by Dr. A. Islam
9
SAP concepts with stress on timing diagrams
• Accumulator: is a
buffer register that
stores intermediate
result during program
run. It has two o/ps.
The two-state o/p goes
to adder/subtracter.
This o/p continuously
drives the
adder/subtracter. The
three-state o/p goes to
W bus and appears on
W bus when EA
(Enable accumulator) is
high.

10. Prepared and presented by Dr. A. Islam
10
SAP concepts with stress on timing diagrams
• B register: is another
buffer register used for
arithmetic operation. A
low on LB bar and +ve
clock edge loads the
word on W bus into B
register.
• Output register
(output port): When
EA (Enable
Accumulator) is high
and LO bar is low, the
next +ve clock edge
loads the accumulator
content into output
register for further LED
display.
• Binary display: is a
row of 8 LEDs
connected to Q output
of each FF of
74LS173.

11. Prepared and presented by Dr. A. Islam
11
SAP concepts with stress on timing diagrams
INSTRUCTION SET OF SAP-1: There are 5 instructions in SAP-1. They are:
LDA, ADD, SUB, OUT and HLT which are upward compatible with 8080/8085.
Every instruction should have machine language code, called opcode. Opcode
of SAP-1 instructions are assumed to be:
Mnemonic Op code
LDA 0000
ADD 0001
SUB 0010
OUT 1110
HLT 1111
Example program:
Address: Mnemonics
0H LDA 9H
1H ADD AH
2H ADD BH
3H SUB CH
4H OUT
5H HLT
The content of A after execution of the program will be 02H.
Address data
6H 00H
7H 00H
8H 00H
9H 01H
AH 02H
BH 03H
CH 04H
DH 00H
EH 00H
FH 00H

12. Prepared and presented by Dr. A. Islam
12
SAP concepts with stress on timing diagrams
The machine language version of the same
program is
Address contents
0000 0000 1001
0001 0001 1010
0010 0001 1011
0011 0010 1100
0100 1110 XXXX
0101 1111 XXXX
0110 XXXX XXXX
0111 XXXX XXXX
1000 XXXX XXXX
1001 0000 0001
1010 0000 0010
1011 0000 0011
1100 0000 0100
As can be seen, the four MSBs of a SAP-1
machine instruction specify the operation, and the
four LSBs give the address. Hence the MSBs is
called instruction field and LSBs as the address
field.
Instructions = XXXX XXXX
Instruction field
Address field

13. Prepared and presented by Dr. A. Islam
13
SAP concepts with stress on timing diagrams

14. Prepared and presented by Dr. A. Islam
14
SAP concepts with stress on timing diagrams
• As can be seen ring counter generates six timing states called
T states (T1 through T6), period during which registers
contents change. Initially when ring counter is cleared with
CLR the ring word is
T1 = 000001
• The successive clock pulses produce following rings words:
T2 = 000010
T3 = 000100
T4 = 001000
T5 = 010000
T6 = 100000
• As can be seen that a positive CLK edge occurs midway
through each T states, where loading of registers take place.

15. Prepared and presented by Dr. A. Islam
15
SAP concepts with stress on timing diagrams
• Fetch cycle consists of three states: Address state, Increment state, and
memory state. These states taken together is called fetch cycle.
Various operations that take place during these states are tabulated as
given below:
T states State
name
Active
control
signals
Active
parts of
SAP-1
Operation takes place
T1 Address
state
EP
LM bar
PC
MAR
CON
As high EP enables tristated o/p
buffer of PC, its content is outputted
onto W bus. Low LM bar makes MAR
enabled to be loaded. when +ve CLK
edge hits in the middle of T1 state
MAR gets loaded with the address
available on the W bus.
T2 Incremen
t state
CP PC
CON
In T2 state CP (J & K i/p of PC) goes
high. On +ve CLK edge, PC
increments.
T3 Memory
state
CE bar
LI bar
MAR
RAM
IR
CON
CE bar enables tristated o/p of RAM
making addressed RAM content
available onto W bus. LI bar enables
Instruction register to be loaded with
present content of W bus on +ve
CLK edge.

16. Prepared and presented by Dr. A. Islam
16
SAP concepts with stress on timing diagrams
Fig. 10.3 (Malvino) Fetch Cycle (a) T1 state; (b) T2 state (c) T3 state