1. Memory cache.it U
Memory Size Hierarchy
Top Registers
32 32 bit r.c.ge
32 4 Total n
of 12813 and access time is few ns
On chip cache memory
8 32 KB ofcacheMein
Access time is about 10ns
Second level ofchip cache which can havefew hundreds
of KB and access time is few tenths ofnseconds
Cache memory is a representation ofmain
memory
where
it will copy and keep it for quick access execution
Main Memory
NTegabytesof Dynamic 12AMCORAM access time is
about 100200ns
Backupstorage secondaryStorage Few GB and
large of ns
Registers have control over compiler assembler and the
remaining layers are usually controlled
by H W
2. CacheMemories data
Harvard Split
InstI
Von Neumann unified Data instruction
memory
FF f
prove
ward Hinze
i
ae
cache
r
instr
00 0
On chip cache memory less power fast copies
recently used memory values
Harvard Mem
FF F
instr Tott Him
am P
we
I'T
Damone
3. I
if the cache is located b w processor 4 MMU then
it is known as virtual cache
if the cache is located b w MMU main memory
then it is known as Physical cache
virtual cache saves the data in virtual space
Notes Book digram Pic
generally ARM7 to ARM10 works with logical cache
and ARM it with physical cache
CACHE MEMORY ARCHITECTURE
3Iparts
f
Di
info
1 Address issued
by the processor set index
Data index
2 cache control
3 Cache memory cache lines lb bytes
D Data portions 16bigoted
Status bits
3 cache
tug
write the schematic of 8KB cachemef.rs showingall
3 parts i
p T 0
4. 31
tag fdw3µYw two
tag hit
f FH
34
Data
index
tag Hd
w3f4wtwo
cache
Adder issued
by controller
vg.fi
dtfirty
processor bit
cache controller is Hln supported
by Sjw copies data
It interrupts Rfw memory
ref before passing them
controller uses set index to
availability of cache
line that might hold request
controller checks whether the line is active or not
by verifying the valid bit value
if dirty bitis set
then cache line contains the data which is different
from the main memory
then the controller compares The tag in the adder
with cache
tag of the
memory If it isfalse then
cache miss them the entire data is taken from
the main memory and given to the processor
5. If cache hit then the controller supplies the data
from cache to processor
Chapter 1213 7 Cache Mem Andrew Sloss
