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Special Devices


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This class notes is useful for M.Sc Electronics students of SKU & RU and other ECE students

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Special Devices

  1. 1. 1 Dr.Y.Narasimha Murthy Ph.D SPECIAL DEVICES Universal Active Filter : The rapid developments in integrated circuit technology , paved the way to designing filter circuits on a single chip which can simultaneously give Low-pass , High-pass, Band-pass output responses . These filter circuits are known as Universal filters. Using the Universal filters , Notch and all-pass filter response can also be obtained .The chip has the features of easy control gain and Q-factor .This universal filter is also commonly known as state variable filter. Commercially the universal filter is available as a 16-pin DIP IC (FLT-U2) from Datel company. The important characteristics are : The filter has a frequency range of 0.001 Hz to 200KHz. The figure of Merit is (Q):0.1 to 100. Frequency stability is 0.001% per 0C Voltage gain is : 0.1 to 1000 Input impedance is 5Mohms. Unity gain bandwidth is 3M.Hz and the Slew rate is 1V/uS.
  2. 2. 2 Dr.Y.Narasimha Murthy Ph.D Working: The Datel’s FLT-U2 is the best example of a universal filter that uses the state state variable active filter principle to implement second order low-pass, high-pass and band – pass functions. The filter consists of four op-amps in which three are connected for filter action and the fourth unconnected op-amp is used as a gain stage or buffer amplifier or used to raise the order of the filter. Two–pole (second order) low-pass ,high-pass and band-pass filter functions are obtained simultaneously from three different outputs ,and notch and all-pass functions are available by combining these outputs in the uncommitted operational amplifier.To realize higher order filters several FLT-U2s can be cascaded. Frequency tuning is done by using two external resistors and the Q-tuning is done by a third resistor. By using suitable components externally any of the filter types like Butterworth, Chebyshev or Bessel may also be implemented using this universal filter.
  3. 3. 3 Dr.Y.Narasimha Murthy Ph.D TIMER IC 555 : Due to the inherent limitations of mechanical and electro mechanical timers, solid state timers in IC form gained momentum. The most popular integrated circuit timer is 555 , first introduced by Signetics corporation in the year 1971 and later National Semiconductor corporation as SE555/555NE. It is a low cost, easy to use versatile IC which can operate from supply voltages of +5V to +18V.The 555 timer is available in two packages. T0-99 circular metal Can and DIP. This DIP is available as 8 pin and 14 pins also. Description of Functional Diagram: The 555 timer consists of two op-amp comparators, one flip- flop and two transistors. The o/p of the comparators set and reset the flip-flop. The F/F in turn controls the o/p level and the conduction of two control transistors T1 and T2. A voltage divider network between VCC and Ground provides 2/3 VCC to the inverting terminal of threshold comparator and 1/3 Vcc to the non-inverting input of Trigger comparator. When the voltage at threshold terminal greater than or equal to 2/3VCC, the O/P of threshold comparator goes HI and Flip-Flop is reset. Q¯= 1 . This turns T1 on and drives the o/p to low.
  4. 4. 4 Dr.Y.Narasimha Murthy Ph.D When the voltage at the trigger input is less than 1/3 VCC , its O/P goes high. Which makes Q¯= 0 .AS a result T1 is cutoff and the output goes high. Once the circuit is triggered, it remains in that state until the set time is elapsed (i.e. voltage at the threshold terminals reaches 2/3VCC) .The circuit do not change for further triggering during this period. However application of varying DC voltage to the pin 5 (Control voltage) alters the timing cycle. The output can be pulse width modulated by applying a sinusoidal voltage to this terminal. The 555 timer has two basic operational modes : (i) one shot and (ii) Astable . In the one-shot mode, the 555 acts like a mono-stable multivibrator. A monostable has a single stable state--that is the off state. Whenever it is triggered by an input pulse, the monostable switches to its temporary state. It remains in that state for a period of time determined by an RC network. It then returns to its stable state. In other words, the mono-stable circuit generates a single pulse of a fixed time duration each time it receives an input trigger pulse. Hence the name one-shot. One-shot multivibrators are used for turning some circuit or external component on or off for a specific length of time. It is also used to generate delays. When multiple one-shots are cascaded,
  5. 5. 5 Dr.Y.Narasimha Murthy Ph.D a variety of sequential timing pulses can be generated. Those pulses will allow you to time and sequence a number of related operations. The other operational mode of 555 is an astable multivibrator. An astable multivibrator is simplly an oscillator. The astable multivibrator generates a continuous stream of rectangular off-on pulses that switch between two voltage levels. The frequency of the pulses and their duty cycles depend on the values of RC network . The XR-2240 Programmable Timer/Counter : The XR-2240, programmable timer/counter is a monolithic controller capable of producing ultra long time delays without the loss of accuracy. It can generate accurate time delays from seconds to days. Two such timing circuits can be cascaded to generate time delays of up to three years. The XR-2240 consists of one modified 555 timer(Time base circuit), one 8-bit programmable binary counter and control circuit (Flip-Flop). All these contained in a single 16-pin DIP chip. The time delay is set by an external R-C network and can be programmed to any value from IRC to 255RC. In astable operation ,the circuit can generate 256 separate frequencies from a single RC setting and can be synchronized with external clock signals.Both the control inputs and outputs are compatible with TTL and DTL logic levels.The time base works as an astable multivibrator with a period equal to RC .The eight bit binary counter can divide the time base output by any integer value from 1 to 255.The counter may operate independently of the time base. Features:  Generate time delays from microseconds to days  Programmable delays: 1 RC to 255 RC  Voltage Supply Range: 4V to 15V.  TTL and DTL compatible outputs.  Accuracy : 0.5%
  6. 6. 6 Dr.Y.Narasimha Murthy Ph.D Working of XR-2240 : The timing cycle for the XR-2240 is initiated by applying a positive going trigger pulse to the input (pin 11).So, it starts the 555 time base oscillator and enables the counter section and sets all the counter outputs to low state.The time base oscillator generates timing pulses with a period of RC .These clock pulses are counted by the binary counter. A positive going pulse on reset pin (10) stops the 555 timer base oscillator. The threshold voltage for both trigger and reset terminals is about 1.4V. The Time base period T for one Cycle of 555 oscillators is set by an external RC network connected to the timing pin 13. Therefore T=RC ; R: Range from 1KΩ to 10MΩ; C; Ranges from 0.05 to 1000 μF The binary counter outputs are open collector outputs .So, they are shorted together to a common pull-up resistor to form a wired-or connection.The combined output will be low as long as any
  7. 7. 7 Dr.Y.Narasimha Murthy Ph.D one of the outputs is low. So,the delays associated with each counter output can be summed by simply shorting them together to a common output bus as shown in the figure. Suppose ,the pin 6 alone is connected to the output and rest are left open,the total time delay would be equal to 32T.In the same way if pins 1,4 and 8 are shorted to the output bus ,the total time delay would be (1+ 8+128) RC= 137RC .So,by proper choice of counter terminals connected to the output bus ,we can achieve the required timing cycle defined by 1T≤ Delay time ≤ 255 T. In the above circuit when the switch S is closed the circuit operates in monostable mode of operation and when it is open it works in astable mode of operation. Applications: XR-2240 has many applications and widely used in generating accurate delays and frequency synthesis circuits. Some of the applications include (i). Precision Timing (ii). Long delay generation (iii). Digital sample and hold (iv).Pulse counting/summing (v). Frequency synthesis .
  8. 8. 8 Dr.Y.Narasimha Murthy Ph.D Function Generator IC 8038: The ICL8038 is a monolithic precision waveform generator IC manufactured by Intersil and capable of producing sine, square and triangular output waveforms, simultaneously with a minimum number of external components or adjustments. Its operating frequency range is from 0.001Hz to 300kHz. There is an option to control the parameters like frequency,duty cycle and distortion of these functions.It is highly stable over a wide range of temperatures and supply voltages .It can be operated using either a single power supply (10-30V) or a dual supply also. The 8038 IC is available as a14 pin DIP chip as shown in the diagram. Pin 1 and Pin12: Sine wave adjusts. The external resistor connections to these pins decide the accuracy of sine waves. For distortion less than 1% we have to connect 100KΩ potentiometer between pin 12 and ground or –VEE. To get a distortion less than 0.5%, we have to connect two 100KΩ potentiometers between VCC and ground. With one of the wipers to pin 1 and other to pin 12. Pin 2 Sine wave output: The sine wave output of amplitude 0.22 Vi is available at this pin. Pin 3: Triangular wave O/P: A Triangular wave of 0.33 Vi is available at this pin. Pin 4 and 5: Duty cycle/Frequency adjust :The frequency of the o/p signal is promotional to the charging and discharging currents and duty cycle can be adjusted by selecting proper values of R1 and R2 between pins 4 and 5 and a capacitor connected at pin 10. The range of the values varies from 1KΩ to 1MΩ.
  9. 9. 9 Dr.Y.Narasimha Murthy Ph.D Principle: The working principle of 8038 can be understood from the block diagram. The operation is based on the charging and discharging a grounded capacitor(C) whose charging and discharging rates are controlled by programmable current sources I1 and I2. When the switch is at the position 1 the capacitor charges at rate determined by current sources I1. Once the capacitor voltage reaches Vu, the upper comparator (comp1) triggers and reset the FF o/p. This causes the switch position to change from position 1 to 2. Now, the capacitor starts discharging at the rates determined by the current source I2. Once the capacitor reaches VL , the lower comparator (comp2) triggers and sets the FF o/p. This changes the switch position from to position 1. This process repeats. So, we get a square wave at the output of the flip-flop and triangular wave across the capacitor. The triangular wave is then passed through an on chip wave shaper (sine converter) , which generates a sine wave. To allow automatic frequency control currents I1 and I2 are made programmable by an external control voltage Vi. For equal magnitudes of I1 and I2, the output wave forms are symmetrical; conversely when two currents are unequal, output wave forms are asymmetrical. By making one of the currents much larger than the other we can get saw tooth waveforms across the capacitor and rectangular wave at the o/p of the flip-flop. XR-2206- Function generator: The XR-2206 is a monolithic function generator capable of producing high quality sine , Sqare, triangular, ramp and pulse wave forms of high stability
  10. 10. 10 Dr.Y.Narasimha Murthy Ph.D and frequency modulated by an external voltage. Frequency of operation can be selected over a range of 0.01Hz to more than 1 MHz. The circuit is ideally suited for communications, instrumentation, and function generator applications requiring sinusoidal tone, AM, FM, or FSK generation. It has a typical drift specification of 20ppm/°C. The oscillator frequency can be linearly swept over a 2000:1 frequency range with an external control voltage, while maintaining low distortion. Functional Block Diagram: The XR-2206 monolithic circuit consists of four major blocks. They are Voltage Controlled Oscillator(VCO) 1. An analog multiplier and sine shaper. 2. A unit gain buffer amplifier and 3. A set of current switches as shown below. The VCO produces an output frequency proportional to an input current, which is set by a resistor from the timing terminals to ground. With two timing pins, two discrete output frequencies can be independently produced for FSK generation applications by using the FSK
  11. 11. 11 Dr.Y.Narasimha Murthy Ph.D input control pin. This input controls the current switches which select one of the timing resistor currents, and routes it to the VCO. The XR-2206 can be operated with two separate timing resistors, R1 and R2, connected to the timing Pin 7 and 8, respectively, Depending on the polarity of the logic signal at Pin 9, either one or the other of these timing resistors is activated. If Pin 9 is open-circuited or connected to a bias voltage 2V, only R1 is activated. Similarly, if the voltage level at Pin 9 is 1V, only R2 is activated. Thus, the output frequency canbe keyed between two levels. f1 and f2, as : f1 = 1/R1C and f2 = 1/R2C For split-supply operation, the keying voltage at Pin 9 is referenced to V-. Frequency of Operation The frequency of oscillation, fo, is determined by the external timing capacitor, C, across Pin 5 and 6, and by the timing resistor, R, connected to either Pin 7 or 8. The frequency is given as: f0 = 1 / RC Hz and can be adjusted by varying either R or C. The recommended values of R, for a given frequency range Sine wave generation: XR-2206 can be used as a sine wave generator. The necessary circuit diagram is shown below. The Potentiometer R1 at pin 7 provides the required frequency tuning. The pin 3 is biased such that output DC level is approximately V+/2. For sine wave generation, the switch S1 is closed. The pins 15 and 16 are used for additional adjustments to get low sine wave distortion. The Resistance R1 and R2 can be used to reduce the distortion to about the resistance R2 provides the fine adjustment for the wave form symmetry. The frequency of the sine wave is f = 1/RC
  12. 12. 12 Dr.Y.Narasimha Murthy Ph.D Triangular wave generation: The same circuit used for sine wave can be used for triangular wave by opening the switch S1. The amplitude of the triangular wave is twice to that of sine wave output obtained with switch S1 closed.The amplitude is controlled by resistance R3. Aapplications of XR-2206 :  Wave form generation.  Sweep generator.  FSK generator.  Phase locked loop.  Voltage to Frequency conversion.  Tone generation.
  13. 13. 13 Dr.Y.Narasimha Murthy Ph.D Phase Locked Loop (565): A phase locked loop is basically a closed loop system designed to lock the O/P frequency and phase to the frequency and phase of an input signal. The PLL can be used as a modulator, demodulators, oscillator, synthesizer, clock signal recovery circuit and so on. It was introduced by a French Scientist de Bellescize in 1832 as a technique for stabilizing an oscillator frequency .The first PLLs were analog but, since the 70’s integrated circuits have been available to perform the same function on an IC . These are called digital PLLs. The Phase Locked Loop acts similar to op-amp in the frequency domain. The op amp has two voltage inputs inverting and non-inverting. The inverting input is normally used for feed back from the output. Similarly, the PLL has two inputs. One is the input signal and the other is the feed back signal from VCO. The op amp changes its output voltage depending on the difference in voltage between the two input voltages. Similarly, the PLL changes its output phase and frequency depending on the frequency difference between two input signals. There are basically there types of PLLs. (i) The linear(Analog) PLL (LPPL) (ii)The Digital PLL (DPLL) (iii). All-digital PLL (ADPLL) Block Diagram-Operation: The PLL consists of four important blocks. They are 1. Phase detector , 2. Low pass filter 3. Error Amplifier and 4. Voltage Controlled Oscillator(VCO) . All these parts are connected to form a closed-loop frequency feedback system.
  14. 14. 14 Dr.Y.Narasimha Murthy Ph.D Working:.When no input signal is applied to the PLL, the error voltage at the output of the phase detector is zero. The voltage Vd(t) from the LPF is also zero, which causes the VCO to operate at a set frequency(fo) called the center frequency. Now, If an input signal is applied to the PLL, The phase detector compares the phase and frequency of the input signal with the VCO frequency and generates an error voltage proportional to the phase and frequency difference of the input signal and VCO. The error voltage Ve(t) is filtered . It will remove high frequency signal (fi+f0) and allows only (fi-f0).The error voltage is Ve(t) filtered and applied to the control input of the VCO. Vd(t) varies in a direction that reduces the frequency difference between the VCO and input-signal frequency. When the input frequency is sufficiently close to the VCO frequency, the closed loop nature of the PLL forces the VCO to lock in frequency with signal input . i.e when the PLL is in lock , the VCO frequency is identical to the input signal frequency, except for a finite phase difference . The range of frequencies over which the PLL can maintain this locked condition is known as the lock range of the system. Once locked, PLL goes through three stages (i). Free running (ii) Capture and (iii). Locked or tracking. IC PLL 565: The IC 565 is a very widely used PLL and Its operating frequency range is 0.001 Hz to 500 K Hz. PLL is available as a 14-pin DIP package and as 10-pin metal can package.
  15. 15. 15 Dr.Y.Narasimha Murthy Ph.D The input signals are fed to the phase detector through pins 2 and 3 in differential mode. The input signals can be direct-coupled provided that the dc level at these two pins is made same and dc resistances seen from pins 2 and 3 are equal. By shorting pins 4 and 5 output of VCO is supplied back to the phase detector (PD) . The output of PD is internally connected to amplifier, the output of which is available at pins 6 and 7 through a resistor of 3.6 k ( connected internally). A capacitor C connected between pins 7 and 10 forms a low-pass filter with 3.6 k. resistor. The filter capacitor C should be large enough so as to eliminate the variations in demodulated output and stabilize the VCO frequency. Voltage available at pin 7 is connected internally to VCO as a control signal. At pin 6 a reference voltage nominally equal to voltage at pin 7 is available allowing both the differential stages to be biased. Pins 1 and 10 are supply pins. The output frequency of the VCO is given by f0= 0.25/ RTCT Where RT and CT are external resistor and capacitors connected to pin 8 and 9. A value between 2KΩ and 20KΩ is recommended for RT . The VCO free running frequency is adjusted with RT and CT to be at the center of the input frequency range. A short circuit between pins 4 and 5 connects the VCO o/p to the phase comparator so as to compare fo with input signal fs. The centre frequency of the PLL is determined by the free-running frequency of the VCO.
  16. 16. 16 Dr.Y.Narasimha Murthy Ph.D CD 4046-PLL : This is a CMOS micro power Phase Locked Loop. It consists of a low power, linear voltage controlled oscillator(VCO) and two different phase comparators having a common signal input amplifier and a common comparator input. If , necessary a 5.2V Zener diode is provided for supply regulation. The VCO is connected either directly or through frequency dividers to the comparator input of the phase comparators. The LPF is implemented through external parts as some components cannot be integrated and also the configuration changes from application to application. The CD4046 is available as 16 pin IC in different packages. Features: Its power consumption is very low(~70 μw)  Operating frequency range upto 1.4 MHz.  Very low frequency drift 0,04% /0 C.  Choices of two comparators  High VCO Linearity.  Zener diode provision for supply regulation.  Standardized symmetrical output characteristics Block Diagram: The PLL 4046 consists of a linear voltage controlled oscillator and two different phase comparators. The VCO requires one external capacitor C1 and one or two external resistors (R1 or R1 &R2). The resistor R1 and capacitor C1 decides the frequency range of VCO and resistor R2 enables the VCO to have a frequency offset if required. The high input impedance of the VCO simplifies the design of LPF by permitting the designer a wide choice of resistor to capacitor ratios.
  17. 17. 17 Dr.Y.Narasimha Murthy Ph.D In order not to load the LPF, a source follower O/P voltage is provided at pin 10. If this terminal is used, a load resistor RS of 10KΩ or more should be connected from this terminal to Vss, Otherwise it must be left open. The VCO can be connected either directly or through frequency dividers to the comparator input of the phase comparators. Logic 0 on the Inhibit input enables the VCO and the source follower while a logic 1 turns off both to minimize standby power consumption. Phase comparator 1 is an exclusive-OR network to maximize the lock range, the signal and the comparator input frequencies must have 50% duty cycle. With no signal or noise on the signal input, this phase comparator has an average output voltage equal to VDD /2. The low pass filter connected to the output of phase comparator1 supplies the average voltage to the VCO input and causes the VCO to oscillate at the corner frequency f0.
  18. 18. 18 Dr.Y.Narasimha Murthy Ph.D Important feature of this type of phase comparator is that it may lock onto input frequencies that are close to harmonic of the VCO center frequency.Phase comparator II is an edge controlled digital memory network. It consists of four Flip Flop stages, control gating and a three state output circuit comprising p and n type drivers having a common output node.This type of phase comparator acts only on the positive edge of the signal and comparator inputs. Applications: 1. FM modulator and demodulator 2. Frequency synthesis and multiplication 3. Frequency discriminator 4. Voltage to frequency converter 5. Tone Decoding 6. FSK modulation 7. Signal Conditionings.
  19. 19. 19 Dr.Y.Narasimha Murthy Ph.D LM 380 Audio Power Amplifier: It is an audio power amplifier widely used for consumer applications. The output is short circuit proof with internal thermal limiting. In order to hold system cost to a minimum, gain is internally fixed at 34 dB . It is a 40 PIN, DIP chip with the following features Features:  Wide supply voltage range  Low quiescent power drain  Voltage gain fixed at 50.  High peak current capabilities.  Input reference to ground  High input impedance  Low distortion  Quiescent output voltage at one half of the supply voltage  Standard dual in line package. Circuit Description: The input stage of LM380 is PNP emitter follower driving a PNP differential pair with a slave current source load. The second stage is a common emitter voltage gain amplifier with a current-source load. Internal compensation is provided by the polar-splitting capacitor . This pole splitting compensation is used to preserve the wide power band width.(100KHz at 2W,8Ω). The amplifier gain is internally fixed to 50 or 34dB. This is achieved by the internal feedback network. The
  20. 20. 20 Dr.Y.Narasimha Murthy Ph.D LM 380 is internally biased with the 150 KΩ resistance to ground. This enables input transducers to be direct coupled to either inverting or non-inverting inputs of the amplifier. In most applications where the non-inverting input is used , The inverting input is left floating. Audio Power Amplifier : The circuit shows simple audio amplifier built using the IC LM380. This amplifier requires very few external components. Although the gain of the LM380 is internally fixed at 50, it can be changed with the use of external components. In the above circuit , the gain is varied up to 50 with the use of the potentiometer across the two input terminals. The wattage of IC LM380 is around 2.5 W. Applications of LM380 : It is used in intercoms, line drivers, alarms, ultrasonic drivers, TV sound system, AM/FM radio, power converters, small servo drivers etc… Data Converters : The unprecedented growth and development in digital technology has revolutionized the computational and processing techniques. Now a days computers are inseparable components in data-acquisition systems. So, the microprocessors (micro computers) are used not only for computations but also for measurement and processing of physical quantities like temperature, pressure, displacement etc. But the microprocessor which is a logic device can process only digital signals. The physical quantities like temperature, pressure etc., are analog quantities. So,
  21. 21. 21 Dr.Y.Narasimha Murthy Ph.D to process the quantities using microprocessors, it is necessary to convert analog signals into equivalent digital signals using certain circuitry. The electronic circuit which converts an analog signal into equivalent digital signal (both in magnitude and sign) is called analog to digital converter. This is popularly known as ADC. The output of a microprocessor will be in digital form, which is not easy for the users to understand. So, the digital data must be again converted into analog data. The electronic circuit which converts the binary data into equivalent analog data is known as digital to analog converter. More popularly known as DAC. Digital to Analog Converter : Based on the principle of working there are two types of DACs. (i) Binary weighted Resistor DAC (ii) R-2R ladder DAC (i).Weighted Resister D/A Converter : This technique is also called variable resister divider network because the resistor used for MSB is R/2N and the resistor used for LSB is R/20 in an N-bit DAC. So, it can be easily understood that for an 8-bit DAC, resister for MSB is R/27 =R/128 and the resister for LSB is R/20 =R. This means that the resister used for MSB handles a high current as compared to the LSB resister. As the resistors are chosen according to the weightage of the binary bits, this technique is called binary weighted resister technique. The circuit diagram for weighted resistor N-bit DAC is shown below.
  22. 22. 22 Dr.Y.Narasimha Murthy Ph.D Here digitally controlled electronic switches are used. These switches can produce a current I corresponding to logic 1 at the MSB, I/2 corresponding to the logic 1 at the next lower bit and I/22 for logic 1 at the next lower bit and so on… and I/2N-1 for logic 1 at the LSB. The total current thus produced will be propositional to the digital input. The output current is converted into corresponding voltage by using an op-amp circuit. This will give us voltage output propositional to the digital input. Suppose V(0) and V(1) are the voltages applied to the resistor network for 0 and 1 respectively, the output voltage of DAC is given by Here RF is the feedback resistance. As the output changes in only one direction, this DAC is a unipolar DAC. Limitations : 1.In this method , each resistor required in the network is of different value, like R/128, R/64. R/32, R/16………R .So ,we have to choose from a wide range of values, which is practically and economically not feasible many times. This will also affect the accuracy and stability of the circuit. 2. When the number of input bits is large, the resistor used for LSB will be very high value, which may sometimes be nearly equal to input resistance of the amplifier. This will affect the result. 3.If each higher bit resistor is not exactly half of the previous resistor value, the next step size will be change. So, to overcome all these limitations, we use R-2R binary ladder network technique which uses resistors having only two values R & 2R . (ii).R-2R Ladder Network D/A Converter : This is a better type of D/A converter which eliminates the drawbacks suffered by weighted resister D/A converter. It is also a resistive network, whose output voltage is properly weighted sum of digital inputs. The salient features of this converter are
  23. 23. 23 Dr.Y.Narasimha Murthy Ph.D  It is constructed using the resistors of two values (R and 2R) only.  These binary ladder networks are available on monolithic integrated chips thus giving a high degree of precision.  The only disadvantage is that one additional resistor is required for each bit as compared to the weighted resistor network, where only one resistor is needed for each bit. Functioning: The circuit diagram of a 4-bit D/A converter using R-2R ladder network is shown in fig1. below. The binary inputs are applied by switches b0 through b3 and the output is proportional to the binary inputs. The binary inputs can be either high (+5V) or low(0V). Let us assume that the MSB switch b3 is connected to +5V and other switches are connected to ground. Let R=RL=10KΩ and RF =2R. Applying Thevenin’s theorem to the left side of the switch b3, the equivalent Thevenin’s resistance is RTh =[ [ {[(2R║2R+R) ║2R] ║2R]+R}║2R]+R RTh = 2R The resultant circuit is as shown in fig.2 below. In the circuit, the non-inverting input is at virtual ground .So V2 = 0 , and the current through RTh is zero. However current through the resistor 2R connected to +5V is I = 5V/20 KΩ = 0.25mA.
  24. 24. 24 Dr.Y.Narasimha Murthy Ph.D The same current flows through the feedback resistor RF. So, the output voltage V0= RF .I V0 = - (20KΩ) (0.25mA) = - 5V Using the same theory the output voltage corresponding to all the possible combinations of binary input can be determined. The maximum or full scale output of -9.375 V is obtained when all the binary inputs are high. The output voltage equation can be written as V0= - RF (b3/2R + b2/4R+ b1/8R+b0 /16R) where each of the bits b3 , b2 ,b1 and b0 may be either +5V or 0 V. The only drawback of this R-2R ladder circuit is, as the number of binary inputs increases beyond 4, the circuit becomes complex and accuracy decreases. Analog to Digital Converter: The Analog to Digital conversion is a quantizing process, in which an analog signal is converted in to its equivalent binary (digital) value. This process is opposite to D/A conversion process. Based on the conversion technique the ADCs are classified into two categories. The first technique involves comparing a given analog signal with the internally generated equivalent signal. This category includes,  Successive approximation  Counter type and  Flash type ADCs
  25. 25. 25 Dr.Y.Narasimha Murthy Ph.D The second type involves changing an analog signal into time or frequency and comparing these new parameters to known values. This group includes (a) Dual slope ADCs. and (ii) Voltage to frequency converters. The successive approximation and Flash ADCs are faster but less accurate than the integrator and voltage to frequency type converters. Also, the flash type are expensive and also difficult to design, for high accuracy. Principle of Successive Approximation : It is the most popular method of A/D conversion. It has also excellent compromise between accuracy and speed. Here, the principle is ,an unknown voltage Vin is compared with the fraction of the reference voltage (Vr). For n-bit digital output, comparison is made for n times with different fractions of Vr. The value of the particular bit is set to 1, if Vin is greater than the set fraction of Vr. The value of the particular bit is set to 0 , if Vin is less than the set fraction of Vr. Successive Approximation A/D Converter: The heart of the circuit is a successive approximation register(SAR). If the output of ADC is to be 8-bit, we use an 8-bit successive Approximation Register . The output of SAR is applied to an 8-bit D/A converter. The analog output of the D/A converter is given to the inverting terminal of the comparator. A reference voltage is applied to the non-inverting terminal. An 8-bit latch is used to store the digital output after complete conversion. As shown in fig.below.
  26. 26. 26 Dr.Y.Narasimha Murthy Ph.D The operation of the circuit is as follows : At the start of conversion cycle, the SAR is reset by holding the start signal(S) high. On the first clock pulse Low-to-High transition, the most significant bit Q7 of the SAR is Set(HIGH). The D/A converter give out an analog equivalent to Q7 bit, which is compared with the analog input Vi . If the DAC o/p V0 is greater than Vi, the comparator output is low and the SAR will clear (Reset) its MSB Q7. On other hand, if the D/A output is less than Vin, the SAR will keep the MSB Q7 set. On the next clock pulse, Low to High transition, the SAR will set the next MSB Q6. Depending on the output of the comparator, the SAR will either set or reset the bit Q6. This process is continued until the SAR completes all the 8-bits. At the end of the LSB Q0, the SAR sends out a conversion complete signal (High) to indicate that the parallel output lines contain valid digital data. This conversion complete signal enables an 8-bit latch and the digital data appear at the output of the latch. The entire process is completed only in 8-clock pulses. To repeat this process continuously the conversion complete signal is connected to the start of conversion input. The advantage of successive approximation A/D converter is its high speed and good resolution. Dual slope ADC : Dual slope conversion is an indirect method for A/D conversion where an analog voltage and reference voltage are converted into time periods by an integrator and then measured by a counter. The speed of conversion is slow,but the accuracy is high.The block diagram of the Dual slope ADC is shown below. A dual slope converter consists of an integrator (Ramp generator), comparator, binary counter, reference voltage. and a control Flip-Flop. The ramp generator input is switched between the analog input voltages Vi and negative reference voltage, -VREF . The analog switch is controlled by the MSB of the counter. When MSB is logic 0, the voltage being measured is connected to the ramp generator input. Similarly when MSB is logic 1, the negative reference voltage is connected to the ramp generator. At time t=0, analog switch ’S’ is connected to the analog input voltage Vi , So that the analog input voltage is integrated by the op-amp integrator. The output voltage of the integrator is given by Voi = -1/RC ∫ Vi dt. = - [Vi / RC].t
  27. 27. 27 Dr.Y.Narasimha Murthy Ph.D Here RC is the integrator time constant and Vi is assumed constant over the integration time period. This makes the output of the comparator Vc ,to go High.Under these conditions ,the AND gate is enabled and the clock pulses are counted by the counter. Since the circuit uses an n-stage ripple counter, it resets to zero after counting 2N pulses. The analog voltage is integrated for a fixed number of 2N clock pulses after which the counter resets to zero. If the clock period is Tc , the integration occurs for a time T1 = 2NTc and the output is a ramp going downwards. At the end of the time interval T1 ,the counter resets and the reference voltage –Vref is connected to the integrator input. The integrator produces a ramp voltage in the positive going direction .The counter continuous to count as long as Vo<
  28. 28. 28 Dr.Y.Narasimha Murthy Ph.D 0.When Vo goes positive at t=T2 ,then the comparator outputgoes low and disables the AND gate. Then the counter stops counting. The time interval T1 = 2NxTime period of the clock pulse. = 2N.Tc When the integrator is fed with negative reference voltage(-Vref) Vo = -(Vi/RC) T1 +Vref/RC (t-T1) Since the voltage Vo= 0 at t=T2 0 = -(Vi/RC) +Vref/RC (T2-T1) therefore (T2 –T1) = (Vi/Vref )T1 = Vi/Vref.2N.Tc If n is the count recorded by the counter at t=T2, (T2-T1) = nTc = Vi/Vref.2N.Tc or n = (Vi /Vref).2N So,the output of the counter is proportional to Vi. If Vref is constant, Vi α n The advantages of dual slope ADC are 1. It is low cost technique 2. it is a highly accurate 3. It is immune to variations In R and C due to temperature the only disadvantage is it is relatively slow.
  29. 29. 29 Dr.Y.Narasimha Murthy Ph.D FLASH CONVERTER : It is the fastest ADC when compared to the other techniques. These are also known as parallel ADCs . Flash ADCs are suitable for very large bandwidth applications. Typical examples include data acquisition, satellite communication, radar processing, sampling oscilloscopes, and high-density disk drives. But the disadvantages are , these converters consume considerable power, have relatively low resolution, and can be quite expensive. Flash ADCs are made by cascading high-speed comparators. For an N-bit converter, the circuit employs 2N-1 comparators. A resistive-divider with 2N resistors provides the reference voltage. Each comparator produces a 1 when its analog input voltage is higher than the reference voltage applied to it. Otherwise, the comparator output is 0. The analog input and the corresponding digital outputs are given in the table. S.No Analog input(Volts) Digital output D2 D1 D0 1 0—0.5 0 0 0 2 0.5—1.5 0 0 1 3 1.5—2.5 0 1 0 4 2.5—3.5 0 1 1 5 3.5—4.5 1 0 0 6 4.5—5.5 1 0 1 7 5.5—6.5 1 1 0 8 >6.5 1 1 1 Let us consider a 3-bit flash converter. It require 23-1= 7 comparators as shown in the diagram. The analog input Vi is applied to all the non-inverting inputs of the comparators as shown in the diagram. The other input to each comparator is a Dc from a regulated supply.The comparators are op-amp circuits without feedback. For a given analog input voltage ,all the comparators below a certain voltage in the ladder, will have one particular state and those above that point will have the opposite state. This pattern of states is applied to a decoder circuit which produces a digital output. For example when input voltage is 5V, the outputs of comparators 1 to 5 would go high and 6 and 7 go low. So, the corresponding digital output would be 101.
  30. 30. 30 Dr.Y.Narasimha Murthy Ph.D The conversion time of the flash converter is limited only by the response times of comparators and logic gates. The cost of the Flash converters increases as the resolution is increased. Sample and Hold circuits - LF 398 : Need of sampling and Hold circuit: The signal that is applied to an A/D Converter should be maintained constant during the conversion period. The sampled signal must be maintained at constant level, until the earlier sample is converted into digital quantity. Otherwise the final result will be erroneous. So, we need a circuit which samples the input analog signal and holds a sample at the sample level till the earlier sample is completely converted. This type of circuit is known as sample and hold circuit. Principle of working : In S/H circuits, a JFET is used as a switch. During the sampling time the JFET is switched ON and the holding capacitor charges upto the level of the analog input voltage. At the end of this short sampling period the JFET is switched off. This isolates the holding capacitor CH and hence output voltage will remain constant at the value of the input voltage at the end of sampling time. However due to leakage in the capacitor there will be a small voltage drop. To avoid this voltage follower circuits are used.
  31. 31. 31 Dr.Y.Narasimha Murthy Ph.D Sampled output voltage = Input voltage x(1+ RF/Ri ) LF 398 IC : The LF398 is a monolithic sample-and-hold circuit which utilizes high-voltage ion-implant JFET technology to obtain ultra-high DC accuracy with fast acquisition of signal and low droop rate. Operating as a unity gain follower, DC gain accuracy is 0.002% typical and acquisition time is as low as 6 ms to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide band width. Input offset adjust is accomplished with a single pin and does not degrade input offset drift. The wide bandwidth allows theLF398 to be included inside the feedback loop of 1 MHz op amps without having stability problems. Input impedance of 1010 Ω allows high source impedances to be used without degrading accuracy. The salient features of this IC are given below. Features: (a) Can operate from ±5V to ±18V (b) Acquisition time is less than 10μs. (c) It has TTL, PMOS, and CMOS compatibility logic input. (d) Low input offset (e) Wide band width (f) Input chrematistics do not change during hold mode (g) Low output noise in hold mode. (h) High supply rejection ratio in sample or hold. Circuit Details: A bipolar input stage is used to achieve low offset voltage and wide band width. In the output amplifier P- channel junction FET s are combined with bipolar devices to give very
  32. 32. 32 Dr.Y.Narasimha Murthy Ph.D low droop rate. The droop rate is the rate at which the output of the S/H circuit decreases. An external capacitor, known as hold capacitor is used with LF 398 to hold the voltage applied to it . A 1μF capacitor can give a droop rate of 5mv/min. JFETs have much lower noise than MOS devices. The schematic of LF 398 is shown below. CH is a hold capacitor connected externally at the pin6. A logic pulse of 5V is applied at the pin 8 The width of the pulse should be equal to acquisition time which depends on hold capacitor. When the logic becomes high, the input voltage is applied to the hold capacitor. This capacitor is charged to the instantaneous value of the input voltage. The input voltage is switched off when the logic goes low. The hold capacitor is isolated from any load through an op amp included in S/H circuit for this purpose. So, the hold capacitor holds the instantaneous value of the input voltage applied it. NOTE: The hold capacitor should be made of dielectrics having low hysteresis such as polystyrene , polypropylene and Teflon etc…The acquisition time mainly depends on the value of hold capacitor. ……………….xxxxxxxxxxxxx…………………