Digital Electronics

1. Digital Electronics-
Logic families and characteristics

2. Types
• TTL – transistor-transistor logic based on bipolar transistors.
• CMOS – complementary metal-oxide semiconductor logic based on
metal-oxide-semiconductor field effect transistors (MOSFETs).
• ECL – emitter coupled logic based on bipolar transistors.

3. General Characteristics of Basic Logic Families
• CMOS consumes very little power, has excellent noise immunity, and
is used with a wide range of voltages.
• TTL can drive more current and uses more power than CMOS.
• ECL is fast, with poor noise immunity and high power consumption.

4. Transistor-transistor logic (TTL)
• based on bipolar transistors
• one of the most widely used families for small- and medium-scale devices –
rarely used for VLSI
• typically operated from 5V supply
• typical noise immunity about 1 – 1.6 V
• many forms, some optimised for speed, power, etc.
• high speed versions comparable to CMOS (~ 1.5 ns)
• low-power versions down to about 1 mW/gate

5. Emitter-coupled logic (ECL)
• based on bipolar transistors, but removes problems of storage time by
preventing the transistors from saturating
• very fast operation - propagation delays of 1ns or less
• high power consumption, perhaps 60 mW/gate
• low noise immunity of about 0.2-0.25 V
• used in some high speed specialist applications, but now largely replaced by
high speed CMOS

6. Complementary metal oxide semiconductor
(CMOS)
• most widely used family for large-scale devices
• combines high speed with low power consumption
• usually operates from a single supply of 5 – 15 V
• excellent noise immunity of about 30% of supply voltage
• can be connected to a large number of gates (about 50)
• many forms – some with tPD down to 1 ns
• power consumption depends on speed (perhaps 1 mW

7. A Comparison of Logic Families

8. Fan-In and Fan-Out
• The fan-out denotes the number of load gates N that are connected to the
output of the driving gate (Figure). Increasing the fan-out of a gate can
affect its logic output levels.
• When the fan-out is large, the added load can deteriorate the dynamic
performance of the driving gate. For these reasons, many generic and
library components define a maximum fan-out to guarantee that the static
and dynamic performance of the element meet specification

9. • The fan-in of a gate is defined as the number of inputs to the gate
(Figure b) Gates with large fan-in tend to be more complex, which
often results in inferior static and dynamic properties.
Fan-In and Fan-Out

10. Propagation delay
• The propagation delay tp of a gate defines how quickly it responds to
a change at its input(s). It expresses the delay experienced by a signal
when passing through a gate.
• It is measured between the 50% transition points of the input and
output waveforms, as shown in Figure for an inverting gate.

11. Propagation delay
• The tpLH defines the response time of the gate for a low to high (or
positive) output transition,
• while tpHL refers to a high to low (or negative) transition. The
propagation delay tp is defined as the average of the two.
The rise/fall time of a signal is largely determined by the strength of the
driving gate, and the load presented by the node itself, which sums the
contributions of the connecting gates (fan-out) and the wiring
parasitics.

12. Observations:
• TTL series best at high frequency is 74 AS
• TTL series best for battery operated circuits is 74 ALS
• ECL is the fastest logic family (unsaturated)
• Best speed - power product (or FOM ) is 74 ACT (for battery operated circuits)

13. Timing Metrics for Sequential Circuits
• There are three important timing parameters associated with a
register as illustrated in Figure.
• The set-up time (tsu) is the time that the data inputs (D input) must
be valid before the clock transition (this is, the 0 to 1 transition for a
positive edge-triggered register).
• The hold time (thold) is the time the data input must remain valid
after the clock edge.

14. Timing Metrics for Sequential Circuits

15. • Assuming that the set-up and hold-times are met, the data at the D
input is copied to the Q output after a worst-case propagation delay
(with reference to the clock edge) denoted by tc-q.
• Given the timing information for the registers and the combination
logic, some system-level timing constraints can be derived. Assume
that the worst-case propagation delay of the logic equals tplogic,
while its minimum delay (also called the contamination delay) is tcd.
The minimum clock period T, required for proper operation of the
sequential circuit is given by
Timing Metrics for Sequential Circuits
T tc-q + tplogic + tsu

16. The hold time of the register imposes an extra constraint for proper
operation,
where tcdregister is the minimum propagation delay (or
contamination delay) of the register

23. Programmable Logic
Device (PLD)

24. Combinational PLDs
(a) Programmable read-only memory
(PROM)
(b) Programmable array logic (PAL)
(c) Programmable logic array (PLA)
Sequential programmable devices include both gates and flip‐flops.
1. Sequential (or simple) programmable logic device (SPLD)
2. Complex programmable logic device (CPLD)
3. Field‐programmable gate array (FPGA)

25. Combinational PLDs

26. PROM

29. Design a Combinational circuit using PROM. The circuit accepts 3 bit binary
number and generates equivalent Excess-3 code

32. PAL

40. PLA