SlideShare a Scribd company logo
NAND and NOR
As a universal gates
Prepared by: Kaushal Shah
Branch – 3rd Semester, Bio-medical engineering
What are a Universal Gate
And why NAND and NOR are
known as universal gates?
 A gate which can be use to create any Logic
gate is called Universal Gate
 NAND and NOR are called Universal Gates
because all the other gates can be created by
using these gates
Proof for NAND gates
 Any Boolean function
can be implemented using AND, OR and NOT
gates
 In the same way AND, OR and NOT gates can
be implemented using NAND gates only,
Implementation of NOT using
NAND
A NOT gate is made by joining the inputs of a NAND
gate together.
Input Output
0 1
1 0
Desired NOT Gate NAND Construction
Implementation of AND using
NAND
 A NAND gate is an inverted AND gate.
 An AND gate is made by following a NAND gate with
a NOT gate
NAND Construction
Input A Input B Output Q
0 0 0
0 1 0
1 0 0
1 1 1
Implementation of OR gate using
NAND
• If the truth table for a NAND gate is examined or by
applying De Morgan's Laws, it can be seen that if any of
the inputs are 0, then the output will be 1. To be an OR
gate,
Input A Input B Output Q
0 0 0
0 1 1
1 0 1
1 1 1NAND Construction
Implementation of NOR gate using
NAND
 A NOR gate is simply an inverted OR gate. Output is
high when neither input A nor input B is high:
Input A Input B Output Q
0 0 1
0 1 0
1 0 0
1 1 0
NAND Construction
Implementation of XOR gate using
NAND
 An XOR gate is constructed similarly to an OR
gate, except with an additional NAND
gate inserted such that if both inputs are high,
the inputs to the final NAND gate will also be
high,
Input A Input B Output Q
0 0 0
0 1 1
1 0 1
1 1 0NAND Construction
Implementation of XNOR gate using
NAND
• An XNOR gate is simply an XOR gate with an inverted
output:
Input A Input B Output Q
0 0 1
0 1 0
1 0 0
1 1 1
NAND Construction
Proof for NOR gates
 Like NAND gates, NOR gates are so-called "universal
gates" that can be combined to form any other kind
of logic gate. A NOR gate is logically an inverted OR
gate
Implementation of NOT gate
using NOR
 NOT made by joining the inputs
of a NOR gate.
Input Output
0 1
1 0
Implementation of OR gate using NOR
Input A Input B Output Q
0 0 0
0 1 1
1 0 1
1 1 1
• The OR gate is simply a NOR gate followed by another
NOR gate
Desired Gate
Implementation of AND gate
using NOR
Input A Input B Output Q
0 0 0
0 1 0
1 0 0
1 1 1
• an AND gate is made by inverting the inputs to a
NOR gate.
NOR Construction
Implementation of NAND gate
using NOR
NOR Construction
Implementation of XOR gate using
NOR
 An XOR gate is made by connecting the output of 3
NOR gates (connected as an AND gate) and the output
of a NOR gate to the respective inputs of a NOR gate.
Input A Input B Output Q
0 0 0
0 1 1
1 0 1
1 1 0NOR Construction
Implementation of XNOR gate using
NOR
 An XNOR gate can be constructed from four NOR gates
implementing the expression "(A NOR N) NOR (B NOR
N) where N = A NOR B". This construction has a
propagation delay three times that of a single NOR gate,
and uses more gates.
Input A Input B Output Q
0 0 1
0 1 0
1 0 0
1 1 1NOR Construction
The End!!
Thank you

More Related Content

What's hot

Universal gates electronic
Universal gates electronic Universal gates electronic
Universal gates electronic
Sooraj Maurya
 
Combinational circuits
Combinational circuits Combinational circuits
Combinational circuits
DrSonali Vyas
 
Universal logic gate
Universal logic gateUniversal logic gate
Universal logic gate
sana younas
 
Logic gates
Logic gatesLogic gates
Logic gates
prasanna chitra
 
Sequential circuits in Digital Electronics
Sequential circuits in Digital ElectronicsSequential circuits in Digital Electronics
Sequential circuits in Digital Electronics
Vinoth Loganathan
 
decoder and encoder
 decoder and encoder decoder and encoder
decoder and encoder
Unsa Shakir
 
Boolean Algebra
Boolean AlgebraBoolean Algebra
Boolean Algebra
blaircomp2003
 
Decoder Full Presentation
Decoder Full Presentation Decoder Full Presentation
Decoder Full Presentation
Adeel Rasheed
 
Encoder & Decoder
Encoder & DecoderEncoder & Decoder
Encoder & Decoder
Syed Saeed
 
Presentation on Flip Flop
Presentation  on Flip FlopPresentation  on Flip Flop
Presentation on Flip Flop
Nahian Ahmed
 
DIGITAL ELECTRONICS- Logic Gates
DIGITAL ELECTRONICS- Logic GatesDIGITAL ELECTRONICS- Logic Gates
DIGITAL ELECTRONICS- Logic Gates
Trinity Dwarka
 
Flip-Flop || Digital Electronics
Flip-Flop || Digital ElectronicsFlip-Flop || Digital Electronics
Flip-Flop || Digital Electronics
Md Sadequl Islam
 
Introduction to Counters
Introduction to CountersIntroduction to Counters
Introduction to Counters
ISMT College
 
K - Map
  K - Map    K - Map
K - Map
Abhishek Choksi
 
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Satya P. Joshi
 
Half adder & full adder
Half adder & full adderHalf adder & full adder
Half adder & full adder
Gaditek
 
13 Boolean Algebra
13 Boolean Algebra13 Boolean Algebra
13 Boolean Algebra
Praveen M Jigajinni
 
Flipflop
FlipflopFlipflop
Flipflop
sohamdodia27
 
adder and subtractor
 adder and subtractor adder and subtractor
adder and subtractor
Unsa Shakir
 
Digital Logic circuit
Digital Logic circuitDigital Logic circuit
Digital Logic circuit
kavitha muneeshwaran
 

What's hot (20)

Universal gates electronic
Universal gates electronic Universal gates electronic
Universal gates electronic
 
Combinational circuits
Combinational circuits Combinational circuits
Combinational circuits
 
Universal logic gate
Universal logic gateUniversal logic gate
Universal logic gate
 
Logic gates
Logic gatesLogic gates
Logic gates
 
Sequential circuits in Digital Electronics
Sequential circuits in Digital ElectronicsSequential circuits in Digital Electronics
Sequential circuits in Digital Electronics
 
decoder and encoder
 decoder and encoder decoder and encoder
decoder and encoder
 
Boolean Algebra
Boolean AlgebraBoolean Algebra
Boolean Algebra
 
Decoder Full Presentation
Decoder Full Presentation Decoder Full Presentation
Decoder Full Presentation
 
Encoder & Decoder
Encoder & DecoderEncoder & Decoder
Encoder & Decoder
 
Presentation on Flip Flop
Presentation  on Flip FlopPresentation  on Flip Flop
Presentation on Flip Flop
 
DIGITAL ELECTRONICS- Logic Gates
DIGITAL ELECTRONICS- Logic GatesDIGITAL ELECTRONICS- Logic Gates
DIGITAL ELECTRONICS- Logic Gates
 
Flip-Flop || Digital Electronics
Flip-Flop || Digital ElectronicsFlip-Flop || Digital Electronics
Flip-Flop || Digital Electronics
 
Introduction to Counters
Introduction to CountersIntroduction to Counters
Introduction to Counters
 
K - Map
  K - Map    K - Map
K - Map
 
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
 
Half adder & full adder
Half adder & full adderHalf adder & full adder
Half adder & full adder
 
13 Boolean Algebra
13 Boolean Algebra13 Boolean Algebra
13 Boolean Algebra
 
Flipflop
FlipflopFlipflop
Flipflop
 
adder and subtractor
 adder and subtractor adder and subtractor
adder and subtractor
 
Digital Logic circuit
Digital Logic circuitDigital Logic circuit
Digital Logic circuit
 

Similar to Nand and nor as a universal gates

Nand and nor
Nand and norNand and nor
Nand and nor
Zahida Pervaiz
 
Universal Gates - Aneesa N Ali
Universal Gates - Aneesa N AliUniversal Gates - Aneesa N Ali
Universal Gates - Aneesa N Ali
Dipayan Sarkar
 
Universal logic Gate ppt for digital logic design
Universal logic Gate ppt for digital logic designUniversal logic Gate ppt for digital logic design
Universal logic Gate ppt for digital logic design
HODECEDSIET
 
Universal Gate ppt to design digital logic circuit
Universal Gate ppt to design digital logic circuitUniversal Gate ppt to design digital logic circuit
Universal Gate ppt to design digital logic circuit
HODECEDSIET
 
NAND and NOR implementation and Other two level implementation
NAND and NOR implementation and  Other two level implementationNAND and NOR implementation and  Other two level implementation
NAND and NOR implementation and Other two level implementation
Muhammad Akhtar
 
Dsd lab internal q.paper
Dsd lab internal q.paperDsd lab internal q.paper
Dsd lab internal q.paper
Arun Dasa
 
Logic gates
Logic gatesLogic gates
LOGICAL_GATES_priyansh_singhal.pdf
LOGICAL_GATES_priyansh_singhal.pdfLOGICAL_GATES_priyansh_singhal.pdf
LOGICAL_GATES_priyansh_singhal.pdf
MeghaChauhan75
 
Nand gate
Nand gateNand gate
Nand gate
hepzijustin
 
NAND AND NOR IMPLEMENTATION.pptx
NAND AND NOR IMPLEMENTATION.pptxNAND AND NOR IMPLEMENTATION.pptx
NAND AND NOR IMPLEMENTATION.pptx
recoveraccount1
 
Chap 3
Chap 3Chap 3
Chap 3
Abid Mahmood
 
introduction of logic gates
introduction of logic gates introduction of logic gates
introduction of logic gates
HASNAINNAZIR1
 
UNIVERSAL PROPERTY.pptx
UNIVERSAL PROPERTY.pptxUNIVERSAL PROPERTY.pptx
UNIVERSAL PROPERTY.pptx
GaganaP13
 
New microsoft office power point presentation
New microsoft office power point presentationNew microsoft office power point presentation
New microsoft office power point presentation
arushi bhatnagar
 
LOGICAL GATES mayank chauhan.pdf
LOGICAL GATES mayank chauhan.pdfLOGICAL GATES mayank chauhan.pdf
LOGICAL GATES mayank chauhan.pdf
MeghaChauhan75
 
Chapter 3_Logic Gates (EEEg4302).pdf
Chapter 3_Logic Gates (EEEg4302).pdfChapter 3_Logic Gates (EEEg4302).pdf
Chapter 3_Logic Gates (EEEg4302).pdf
TamiratDejene1
 
ECAD lab manual
ECAD lab manualECAD lab manual
ECAD lab manual
Dr. Swaminathan Kathirvel
 
Electronics: Logic Gates
Electronics: Logic GatesElectronics: Logic Gates
Electronics: Logic Gates
Marc Owen Rentap anak Dineal Gumis
 
Physics investigatory project { LOGIC GATES} CLASS XII
Physics investigatory project  { LOGIC GATES} CLASS XIIPhysics investigatory project  { LOGIC GATES} CLASS XII
Physics investigatory project { LOGIC GATES} CLASS XII
avneesh1234
 
Deld lab manual
Deld lab manualDeld lab manual
Deld lab manual
Vivek Kumar Sinha
 

Similar to Nand and nor as a universal gates (20)

Nand and nor
Nand and norNand and nor
Nand and nor
 
Universal Gates - Aneesa N Ali
Universal Gates - Aneesa N AliUniversal Gates - Aneesa N Ali
Universal Gates - Aneesa N Ali
 
Universal logic Gate ppt for digital logic design
Universal logic Gate ppt for digital logic designUniversal logic Gate ppt for digital logic design
Universal logic Gate ppt for digital logic design
 
Universal Gate ppt to design digital logic circuit
Universal Gate ppt to design digital logic circuitUniversal Gate ppt to design digital logic circuit
Universal Gate ppt to design digital logic circuit
 
NAND and NOR implementation and Other two level implementation
NAND and NOR implementation and  Other two level implementationNAND and NOR implementation and  Other two level implementation
NAND and NOR implementation and Other two level implementation
 
Dsd lab internal q.paper
Dsd lab internal q.paperDsd lab internal q.paper
Dsd lab internal q.paper
 
Logic gates
Logic gatesLogic gates
Logic gates
 
LOGICAL_GATES_priyansh_singhal.pdf
LOGICAL_GATES_priyansh_singhal.pdfLOGICAL_GATES_priyansh_singhal.pdf
LOGICAL_GATES_priyansh_singhal.pdf
 
Nand gate
Nand gateNand gate
Nand gate
 
NAND AND NOR IMPLEMENTATION.pptx
NAND AND NOR IMPLEMENTATION.pptxNAND AND NOR IMPLEMENTATION.pptx
NAND AND NOR IMPLEMENTATION.pptx
 
Chap 3
Chap 3Chap 3
Chap 3
 
introduction of logic gates
introduction of logic gates introduction of logic gates
introduction of logic gates
 
UNIVERSAL PROPERTY.pptx
UNIVERSAL PROPERTY.pptxUNIVERSAL PROPERTY.pptx
UNIVERSAL PROPERTY.pptx
 
New microsoft office power point presentation
New microsoft office power point presentationNew microsoft office power point presentation
New microsoft office power point presentation
 
LOGICAL GATES mayank chauhan.pdf
LOGICAL GATES mayank chauhan.pdfLOGICAL GATES mayank chauhan.pdf
LOGICAL GATES mayank chauhan.pdf
 
Chapter 3_Logic Gates (EEEg4302).pdf
Chapter 3_Logic Gates (EEEg4302).pdfChapter 3_Logic Gates (EEEg4302).pdf
Chapter 3_Logic Gates (EEEg4302).pdf
 
ECAD lab manual
ECAD lab manualECAD lab manual
ECAD lab manual
 
Electronics: Logic Gates
Electronics: Logic GatesElectronics: Logic Gates
Electronics: Logic Gates
 
Physics investigatory project { LOGIC GATES} CLASS XII
Physics investigatory project  { LOGIC GATES} CLASS XIIPhysics investigatory project  { LOGIC GATES} CLASS XII
Physics investigatory project { LOGIC GATES} CLASS XII
 
Deld lab manual
Deld lab manualDeld lab manual
Deld lab manual
 

Recently uploaded

DESIGN AND MANUFACTURE OF CEILING BOARD USING SAWDUST AND WASTE CARTON MATERI...
DESIGN AND MANUFACTURE OF CEILING BOARD USING SAWDUST AND WASTE CARTON MATERI...DESIGN AND MANUFACTURE OF CEILING BOARD USING SAWDUST AND WASTE CARTON MATERI...
DESIGN AND MANUFACTURE OF CEILING BOARD USING SAWDUST AND WASTE CARTON MATERI...
OKORIE1
 
Butterfly Valves Manufacturer (LBF Series).pdf
Butterfly Valves Manufacturer (LBF Series).pdfButterfly Valves Manufacturer (LBF Series).pdf
Butterfly Valves Manufacturer (LBF Series).pdf
Lubi Valves
 
Prediction of Electrical Energy Efficiency Using Information on Consumer's Ac...
Prediction of Electrical Energy Efficiency Using Information on Consumer's Ac...Prediction of Electrical Energy Efficiency Using Information on Consumer's Ac...
Prediction of Electrical Energy Efficiency Using Information on Consumer's Ac...
PriyankaKilaniya
 
Asymmetrical Repulsion Magnet Motor Ratio 6-7.pdf
Asymmetrical Repulsion Magnet Motor Ratio 6-7.pdfAsymmetrical Repulsion Magnet Motor Ratio 6-7.pdf
Asymmetrical Repulsion Magnet Motor Ratio 6-7.pdf
felixwold
 
Object Oriented Analysis and Design - OOAD
Object Oriented Analysis and Design - OOADObject Oriented Analysis and Design - OOAD
Object Oriented Analysis and Design - OOAD
PreethaV16
 
Ericsson LTE Throughput Troubleshooting Techniques.ppt
Ericsson LTE Throughput Troubleshooting Techniques.pptEricsson LTE Throughput Troubleshooting Techniques.ppt
Ericsson LTE Throughput Troubleshooting Techniques.ppt
wafawafa52
 
EV BMS WITH CHARGE MONITOR AND FIRE DETECTION.pptx
EV BMS WITH CHARGE MONITOR AND FIRE DETECTION.pptxEV BMS WITH CHARGE MONITOR AND FIRE DETECTION.pptx
EV BMS WITH CHARGE MONITOR AND FIRE DETECTION.pptx
nikshimanasa
 
Sri Guru Hargobind Ji - Bandi Chor Guru.pdf
Sri Guru Hargobind Ji - Bandi Chor Guru.pdfSri Guru Hargobind Ji - Bandi Chor Guru.pdf
Sri Guru Hargobind Ji - Bandi Chor Guru.pdf
Balvir Singh
 
ITSM Integration with MuleSoft.pptx
ITSM  Integration with MuleSoft.pptxITSM  Integration with MuleSoft.pptx
ITSM Integration with MuleSoft.pptx
VANDANAMOHANGOUDA
 
Blood finder application project report (1).pdf
Blood finder application project report (1).pdfBlood finder application project report (1).pdf
Blood finder application project report (1).pdf
Kamal Acharya
 
Presentation on Food Delivery Systems
Presentation on Food Delivery SystemsPresentation on Food Delivery Systems
Presentation on Food Delivery Systems
Abdullah Al Noman
 
Open Channel Flow: fluid flow with a free surface
Open Channel Flow: fluid flow with a free surfaceOpen Channel Flow: fluid flow with a free surface
Open Channel Flow: fluid flow with a free surface
Indrajeet sahu
 
AI in customer support Use cases solutions development and implementation.pdf
AI in customer support Use cases solutions development and implementation.pdfAI in customer support Use cases solutions development and implementation.pdf
AI in customer support Use cases solutions development and implementation.pdf
mahaffeycheryld
 
Assistant Engineer (Chemical) Interview Questions.pdf
Assistant Engineer (Chemical) Interview Questions.pdfAssistant Engineer (Chemical) Interview Questions.pdf
Assistant Engineer (Chemical) Interview Questions.pdf
Seetal Daas
 
Null Bangalore | Pentesters Approach to AWS IAM
Null Bangalore | Pentesters Approach to AWS IAMNull Bangalore | Pentesters Approach to AWS IAM
Null Bangalore | Pentesters Approach to AWS IAM
Divyanshu
 
一比一原版(osu毕业证书)美国俄勒冈州立大学毕业证如何办理
一比一原版(osu毕业证书)美国俄勒冈州立大学毕业证如何办理一比一原版(osu毕业证书)美国俄勒冈州立大学毕业证如何办理
一比一原版(osu毕业证书)美国俄勒冈州立大学毕业证如何办理
upoux
 
A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...
A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...
A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...
DharmaBanothu
 
1FIDIC-CONSTRUCTION-CONTRACT-2ND-ED-2017-RED-BOOK.pdf
1FIDIC-CONSTRUCTION-CONTRACT-2ND-ED-2017-RED-BOOK.pdf1FIDIC-CONSTRUCTION-CONTRACT-2ND-ED-2017-RED-BOOK.pdf
1FIDIC-CONSTRUCTION-CONTRACT-2ND-ED-2017-RED-BOOK.pdf
MadhavJungKarki
 
Height and depth gauge linear metrology.pdf
Height and depth gauge linear metrology.pdfHeight and depth gauge linear metrology.pdf
Height and depth gauge linear metrology.pdf
q30122000
 
Call For Paper -3rd International Conference on Artificial Intelligence Advan...
Call For Paper -3rd International Conference on Artificial Intelligence Advan...Call For Paper -3rd International Conference on Artificial Intelligence Advan...
Call For Paper -3rd International Conference on Artificial Intelligence Advan...
ijseajournal
 

Recently uploaded (20)

DESIGN AND MANUFACTURE OF CEILING BOARD USING SAWDUST AND WASTE CARTON MATERI...
DESIGN AND MANUFACTURE OF CEILING BOARD USING SAWDUST AND WASTE CARTON MATERI...DESIGN AND MANUFACTURE OF CEILING BOARD USING SAWDUST AND WASTE CARTON MATERI...
DESIGN AND MANUFACTURE OF CEILING BOARD USING SAWDUST AND WASTE CARTON MATERI...
 
Butterfly Valves Manufacturer (LBF Series).pdf
Butterfly Valves Manufacturer (LBF Series).pdfButterfly Valves Manufacturer (LBF Series).pdf
Butterfly Valves Manufacturer (LBF Series).pdf
 
Prediction of Electrical Energy Efficiency Using Information on Consumer's Ac...
Prediction of Electrical Energy Efficiency Using Information on Consumer's Ac...Prediction of Electrical Energy Efficiency Using Information on Consumer's Ac...
Prediction of Electrical Energy Efficiency Using Information on Consumer's Ac...
 
Asymmetrical Repulsion Magnet Motor Ratio 6-7.pdf
Asymmetrical Repulsion Magnet Motor Ratio 6-7.pdfAsymmetrical Repulsion Magnet Motor Ratio 6-7.pdf
Asymmetrical Repulsion Magnet Motor Ratio 6-7.pdf
 
Object Oriented Analysis and Design - OOAD
Object Oriented Analysis and Design - OOADObject Oriented Analysis and Design - OOAD
Object Oriented Analysis and Design - OOAD
 
Ericsson LTE Throughput Troubleshooting Techniques.ppt
Ericsson LTE Throughput Troubleshooting Techniques.pptEricsson LTE Throughput Troubleshooting Techniques.ppt
Ericsson LTE Throughput Troubleshooting Techniques.ppt
 
EV BMS WITH CHARGE MONITOR AND FIRE DETECTION.pptx
EV BMS WITH CHARGE MONITOR AND FIRE DETECTION.pptxEV BMS WITH CHARGE MONITOR AND FIRE DETECTION.pptx
EV BMS WITH CHARGE MONITOR AND FIRE DETECTION.pptx
 
Sri Guru Hargobind Ji - Bandi Chor Guru.pdf
Sri Guru Hargobind Ji - Bandi Chor Guru.pdfSri Guru Hargobind Ji - Bandi Chor Guru.pdf
Sri Guru Hargobind Ji - Bandi Chor Guru.pdf
 
ITSM Integration with MuleSoft.pptx
ITSM  Integration with MuleSoft.pptxITSM  Integration with MuleSoft.pptx
ITSM Integration with MuleSoft.pptx
 
Blood finder application project report (1).pdf
Blood finder application project report (1).pdfBlood finder application project report (1).pdf
Blood finder application project report (1).pdf
 
Presentation on Food Delivery Systems
Presentation on Food Delivery SystemsPresentation on Food Delivery Systems
Presentation on Food Delivery Systems
 
Open Channel Flow: fluid flow with a free surface
Open Channel Flow: fluid flow with a free surfaceOpen Channel Flow: fluid flow with a free surface
Open Channel Flow: fluid flow with a free surface
 
AI in customer support Use cases solutions development and implementation.pdf
AI in customer support Use cases solutions development and implementation.pdfAI in customer support Use cases solutions development and implementation.pdf
AI in customer support Use cases solutions development and implementation.pdf
 
Assistant Engineer (Chemical) Interview Questions.pdf
Assistant Engineer (Chemical) Interview Questions.pdfAssistant Engineer (Chemical) Interview Questions.pdf
Assistant Engineer (Chemical) Interview Questions.pdf
 
Null Bangalore | Pentesters Approach to AWS IAM
Null Bangalore | Pentesters Approach to AWS IAMNull Bangalore | Pentesters Approach to AWS IAM
Null Bangalore | Pentesters Approach to AWS IAM
 
一比一原版(osu毕业证书)美国俄勒冈州立大学毕业证如何办理
一比一原版(osu毕业证书)美国俄勒冈州立大学毕业证如何办理一比一原版(osu毕业证书)美国俄勒冈州立大学毕业证如何办理
一比一原版(osu毕业证书)美国俄勒冈州立大学毕业证如何办理
 
A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...
A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...
A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...
 
1FIDIC-CONSTRUCTION-CONTRACT-2ND-ED-2017-RED-BOOK.pdf
1FIDIC-CONSTRUCTION-CONTRACT-2ND-ED-2017-RED-BOOK.pdf1FIDIC-CONSTRUCTION-CONTRACT-2ND-ED-2017-RED-BOOK.pdf
1FIDIC-CONSTRUCTION-CONTRACT-2ND-ED-2017-RED-BOOK.pdf
 
Height and depth gauge linear metrology.pdf
Height and depth gauge linear metrology.pdfHeight and depth gauge linear metrology.pdf
Height and depth gauge linear metrology.pdf
 
Call For Paper -3rd International Conference on Artificial Intelligence Advan...
Call For Paper -3rd International Conference on Artificial Intelligence Advan...Call For Paper -3rd International Conference on Artificial Intelligence Advan...
Call For Paper -3rd International Conference on Artificial Intelligence Advan...
 

Nand and nor as a universal gates

  • 1. NAND and NOR As a universal gates Prepared by: Kaushal Shah Branch – 3rd Semester, Bio-medical engineering
  • 2. What are a Universal Gate And why NAND and NOR are known as universal gates?  A gate which can be use to create any Logic gate is called Universal Gate  NAND and NOR are called Universal Gates because all the other gates can be created by using these gates
  • 3. Proof for NAND gates  Any Boolean function can be implemented using AND, OR and NOT gates  In the same way AND, OR and NOT gates can be implemented using NAND gates only,
  • 4. Implementation of NOT using NAND A NOT gate is made by joining the inputs of a NAND gate together. Input Output 0 1 1 0 Desired NOT Gate NAND Construction
  • 5. Implementation of AND using NAND  A NAND gate is an inverted AND gate.  An AND gate is made by following a NAND gate with a NOT gate NAND Construction Input A Input B Output Q 0 0 0 0 1 0 1 0 0 1 1 1
  • 6. Implementation of OR gate using NAND • If the truth table for a NAND gate is examined or by applying De Morgan's Laws, it can be seen that if any of the inputs are 0, then the output will be 1. To be an OR gate, Input A Input B Output Q 0 0 0 0 1 1 1 0 1 1 1 1NAND Construction
  • 7. Implementation of NOR gate using NAND  A NOR gate is simply an inverted OR gate. Output is high when neither input A nor input B is high: Input A Input B Output Q 0 0 1 0 1 0 1 0 0 1 1 0 NAND Construction
  • 8. Implementation of XOR gate using NAND  An XOR gate is constructed similarly to an OR gate, except with an additional NAND gate inserted such that if both inputs are high, the inputs to the final NAND gate will also be high, Input A Input B Output Q 0 0 0 0 1 1 1 0 1 1 1 0NAND Construction
  • 9. Implementation of XNOR gate using NAND • An XNOR gate is simply an XOR gate with an inverted output: Input A Input B Output Q 0 0 1 0 1 0 1 0 0 1 1 1 NAND Construction
  • 10. Proof for NOR gates  Like NAND gates, NOR gates are so-called "universal gates" that can be combined to form any other kind of logic gate. A NOR gate is logically an inverted OR gate Implementation of NOT gate using NOR  NOT made by joining the inputs of a NOR gate. Input Output 0 1 1 0
  • 11. Implementation of OR gate using NOR Input A Input B Output Q 0 0 0 0 1 1 1 0 1 1 1 1 • The OR gate is simply a NOR gate followed by another NOR gate Desired Gate
  • 12. Implementation of AND gate using NOR Input A Input B Output Q 0 0 0 0 1 0 1 0 0 1 1 1 • an AND gate is made by inverting the inputs to a NOR gate. NOR Construction
  • 13. Implementation of NAND gate using NOR NOR Construction
  • 14. Implementation of XOR gate using NOR  An XOR gate is made by connecting the output of 3 NOR gates (connected as an AND gate) and the output of a NOR gate to the respective inputs of a NOR gate. Input A Input B Output Q 0 0 0 0 1 1 1 0 1 1 1 0NOR Construction
  • 15. Implementation of XNOR gate using NOR  An XNOR gate can be constructed from four NOR gates implementing the expression "(A NOR N) NOR (B NOR N) where N = A NOR B". This construction has a propagation delay three times that of a single NOR gate, and uses more gates. Input A Input B Output Q 0 0 1 0 1 0 1 0 0 1 1 1NOR Construction