Boolean algebra simplification and combination circuits

UNIT II
Boolean Algebra Simplification
and Combinational Circuits
By Dr. Dhobale J V
Associate Professor
School of Engineering & Technology
RNB Global University, Bikaner
RNB Global University, Bikaner. 1Course Code - 19004000

Objectives
 Simplification of Boolean function by K-Map.
 Simplification of Boolean function by Q. M.
 Adder – Half, Full, BCD, High Speed.
 Subtractor, Multiplier, dividers.
 ALU, Code Conversion – Encoder, Decoder.
 Comparators, Multiplexers, Demultiplexers.
 Implementation using ICs.
2RNB Global University, Bikaner.Course Code - 19004000

Boolean Algebra – Simplification
 A simplified Boolean expression uses the
fewest gates possible to implement a given
expression.
 Ex. Simplify - AB + A(B + C) + B(B + C)

 Solution - AB + AB + AC + BB + BC
AB + AB + AC + B + BC
AB + AC + B + BC
AB + AC + B
B+AC

 Ex. Simplify – 1. C + BC
2. AB (A + B) (B + B)
3. (A + C) (AD + AD) + AC + C
4. A (A+B)+(B+AA)(A+B)

 Ex. Simplify – 1. C + BC
 Solution - C + BC
= C + (B + C)
= ( C + C) + B
= 1 + B
= 1

 Ex. Simplify –
2. AB (A + B) (B + B)
Solution – AB ( A + B) (B + B)
= AB ( A + B)
= ( A + B) (A + B)
= AA + AB + AB + BB
= A + A( B + B )
= A + A
= A

 Ex. Simplify –
3. (A + C) (AD + AD) + AC + C
Solution - (A + C) (AD + AD) + AC + C
= (A + C) A (D + D) + AC + C
= ( A + C ) A + C
= AA + AC + C
= A + C

 Ex. Simplify – 4. A (A+B)+(B+AA)(A+B)
Solution - A (A+B)+(B+AA)(A+B)
= AA + AB + (B+A) (A+B)
= 0 + AB + AB + BB + AA + AB
= AB + AB + 0 + A + AB
= AB + A (B+1+B)
= AB + A (1 + 1)
= AB + A
= (A+A)(A+B)
= A+B

 Standard form of Boolean expression
(Canonical Form): All Boolean expressions,
regardless of their form, can be converted into
either of two standard forms: the sum-of-
products form or the product-of sums form.
 Standardization makes the evaluation,
simplification, and implementation of Boolean
expressions much more systematic and
easier.

 Standard form of Boolean expression:
 The Sum-of-Products (SOP) Form.
 When two or more product terms are summed
by Boolean addition, the resulting expression
is a sum-of-products (SOP).
 Ex. AB + ABC
ABC + CDE + BCD
AB + BCD + AC
 Also, an SOP expression can contain a single-
variable term, as in A + ABC + BCD.

 The Sum-of-Products (SOP) Form.
 In an SOP expression a single overbar
cannot extend over more than one variable.

 Converting Product Terms to Standard SOP :
 Each product term in an SOP expression that
does not contain all the variables in the
domain can be expanded to standard SOP to
include all variables in the domain and their
complements.
 a nonstandard SOP expression is converted
into standard form using Boolean algebra rule
6 (A + A = 1).

 Example - Convert the following Boolean
expression into standard SOP form:
ABC + AB + ABCD
 Solution - The domain of this SOP expression
A, B, C, D.
 Take one term at a time. The first term, ABC,
is missing variable D or D, so multiply the first
term by (D + D) as follows:

ABC = ABC(D + D) = ABCD + ABCD
 In this case, two standard product terms are
the result.
 The second term, AB, is missing variables C
or C and D or D, so first multiply the second
term by C + C as follows:
 AB = AB(C + C) = ABC + ABC

ABC = ABC(D + D) = ABCD + ABCD
 AB = AB(C + C) = ABC + ABC
 The two resulting terms are missing variable D
or D, so multiply both terms by (D + D) as
follows:
 ABC(D + D) + ABC(D + D)
 = ABCD + ABCD + ABCD + ABCD

 In this case, four standard product terms are
the result. The third term, ABCD, is already in
standard form. The complete standard SOP
form of the original expression is as follows:
 ABC + AB + ABCD = ABCD + ABCD + ABCD
+ ABCD + ABCD + ABCD + ABCD

 The Product-of-Sums (POS) Form : A sum
term was defined before as a term consisting
of the sum (Boolean addition) of literals
(variables or their complements). When two or
more sum terms are multiplied, the resulting
expression is a product-of-sums (POS).
 Examples - (A + B)(A + B + C)
(A + B + C)( C + D + E)(B + C + D)
(A + B)(A + B + C)(A + C)

 The Product-of-Sums (POS) Form : A POS
expression can contain a single-variable term,
as in A(A + B + C)(B + C + D).
 In a POS expression, a single overbar cannot
extend over more than one variable; however,
more than one variable in a term can have an
overbar.
 For example, a POS expression can have the
term A + B + C but not A + B + C.

 The Product-of-Sums (POS) Form :
Implementation of a POS Expression simply
requires ANDing the outputs of two or more
OR gates. A sum term is produced by an OR
operation and the product of two or more sum
terms is produced by an AND operation.
 Following figure shows for the expression (A +
B)(B + C + D)(A + C).

 The Product-of-Sums (POS) Form : The
Standard POS Form - So far, we have seen
POS expressions in which some of the sum
terms do not contain all of the variables in the
domain of the expression.
 For example, the expression
(A + B + C) (A + B + D) (A + B + C + D)

 The Product-of-Sums (POS) Form : has a
domain made up of the variables A, B, C, and
D.
 Notice that the complete set of variables in the
domain is not represented in first two terms of
the expression; that is, D or D is missing from
the first term and C or C is missing from the
second term.
 Standard Exp. is –
(A + B + C + D)(A + B + C + D)(A + B + C + D)

Converting a Sum Term to Standard POS-
Rules –
1. Add to each nonstandard product term a term
made up of the product of the missing
variable and its complement. This results in
two sum terms. As you know, you can add 0
to anything without changing its value.

Rules –
2. Apply Boolean Rule No. 12 A + BC = (A +
B)(A + C).
3. Repeat Step 1 until all resulting sum terms
contain all variables in the domain in either
complemented or non complemented form.

Example - Convert the following Boolean
expression into standard POS form:
(A + B + C)(B + C + D)(A + B + C + D)
 Solution - The domain of this POS expression
is A, B, C, D. Take one term at a time. The first
term, A + B + C, is missing variable D or D, so
add DD and apply rule 12 as follows:

A + B + C = A + B + C + DD = (A + B + C +
D)(A + B + C + D)
 The second term, B + C + D, is missing
variable A or A
B + C + D = B + C + D + AA = (A + B + C +
D)(A + B + C + D)
 The third term, A + B + C + D, is already in
standard form.

(A + B + C)(B + C + D)(A + B + C + D) = (A +
B + C + D)(A + B + C +D) (A + B + C + D)(A +
B + C + D) (A + B + C + D)

 Express the Boolean function F = A + BC in a
sum of minterms (SOP).
Solution - The term A is missing two variables
because the domain of F is (A, B, C)
A = A(B + B) = AB + AB
The term BC is missing A vaiable
BC (A + A) = BCA + BCA
The term AB + AB is missing C
AB(C + C) + AB(C + C)
= ABC+ABC+ABC+ABC

 Final solution is
= ABC+ABC+ABC+ABC+ABC+ABC
= ABC+ABC+ABC+ABC+ABC
F= m7+m6+m5+m4+m1
 In short notation
F(A, B, C) = Ʃ(1, 4, 5, 6, 7)
F(A, B, C) = Ʃ(0, 2, 3)

 The complement of a function expressed as
the sum of minterms equal to the sum of
minterms missing from the original function.
 Truth Table for F = A+BC

 Express F = xy + xz in a product of maxterms
form.

form.
Solution – F = xy + xz
= (xy + x) (xy + z)
= (x + x)(y + x)(x + z)(y + z)
= (y + x) (x + z)(y + z)
F= (x + y + zz)(x + yy + z)(xx + y + z)
= (x + y + z) (x + y + z) (x + y + z) (x + y + z)
(x + y + z) (x + y + z)

form.
Solution –
F = (x + y + z) (x + y + z) (x + y + z) (x + y + z)
F = M4 M5 M0 M2
F(x, y, z) = Π(0, 2, 4, 5)
F(x, y, z) = Π(1, 3, 6, 7)
 The complement of a function expressed as
the product of maxterms equal to the product
of maxterms missing from the original function.

 Example - Develop a truth table for the
standard SOP expression ABC + ABC + ABC.

 Example - Determine the truth table for the
following standard POS expression:
(A+B+C) (A+B+C) (A+B+C) (A+B+C) (A+B+C)

KARNAUGH MAP MINIMIZATION
 A Karnaugh map provides a systematic
method for simplifying Boolean expressions
and, if properly used, will produce the simplest
SOP or POS expression possible, known as
the minimum expression.
 As you have seen, the effectiveness of
algebraic simplification depends on your
familiarity with all the laws, rules, and
theorems of Boolean algebra and on your
ability to apply them.

 A Karnaugh map is similar to a truth table
because it presents all of the possible values
of input variables and the resulting output for
each value.
 Instead of being organized into columns and
rows like a truth table, the Karnaugh map is an
array of cells in which each cell represents a
binary value of the input variables.

 The cells are arranged in a way so that
simplification of a given expression is simply a
matter of properly grouping the cells.
 Karnaugh maps can be used for expressions
with two, three, four and five variables.
Another method, called the Quine-McClusky
method can be used for higher numbers of
variables.

 The number of cells in a Karnaugh map is
equal to the total number of possible input
variable combinations as is the number of
rows in a truth table.
 For three variables, the number of cells is 23 =
8.

 Three Variable Karnaugh Map: The 3-variable
Karnaugh map is an array of eight cells, as
shown in fig below.

 Three Variable Karnaugh Map: In this case, A,
B, and C are used for the variables although
other letters could be used.
 Binary values of A and B are along the left
side (notice the sequence) and the values of C
are across the top.
 The value of a given cell is the binary values of
A and B at the left in the same row combined
with the value of C at the top in the same
column.

 Three Variable Karnaugh Map: For example,
the cell in the upper left corner has a binary
value of 000 and the cell in the lower right
corner has a binary value of 101.

 Four Variable Karnaugh Map: The 4-variable
Karnaugh map is an array of sixteen cells, as
shown in fig below.

 Four Variable Karnaugh Map: Binary values of
A and B are along the left side and the values
of C and D are across the top.
 The value of a given cell is the binary values of
A and B at the left in the same row combined
with the binary values of C and D at the top in
the same column.
 For example, the cell in the upper right corner
has a binary value of 0010 and the cell in the
lower right corner has a binary value of 1010.

 Four Variable Karnaugh Map: below shown
the standard product terms that are
represented by each cell in the 4-variable
Karnaugh map.

 Cell Adjacency : The cells in a Karnaugh map
are arranged so that there is only a single
variable change between adjacent cells.
 Adjacency is defined by a single variable
change.
 In the 3-variable map the 010 cell is adjacent
to the 000 cell, the 011 cell, and the 110 cell.
The 010 cell is not adjacent to the 001 cell, the
111 cell, the 100 cell, or the 101 cell.

 Cell Adjacency : below fig shows Adjacent
cells on a Karnaugh map are those that differ
by only one variable. Arrows point between
adjacent cells.

 KARNAUGH MAP SOP MINIMIZATION: For
an SOP expression in standard form, a 1 is
placed on the Karnaugh map for each product
term in the expression.
 Each 1 is placed in a cell corresponding to the
value of a product term.

 KARNAUGH MAP SOP MINIMIZATION:
Example- Map the following standard SOP
expression on a Karnaugh map.
ABC+ABC+ABC+ABC
Solution -

Example- Map the following standard SOP
expression on a Karnaugh map
ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+
ABCD
Solution -

Example- Map the following SOP
expression on a Karnaugh map: A+AB+ABC
Solution - The SOP expression is obviously
not in standard form because each product
term does not have three variables.
 First expand the terms numerically as follows:

Solution -

expression on a Karnaugh map:
BC+AB+ABC+ABCD+ABCD+ABCD
Solution - The SOP expression is obviously
not in standard form because each product
term does not have four variables.

Solution –

Grouping the 1s, you can group 1s on the
Karnaugh map according to the following
rules by enclosing those adjacent cells
containing 1s.
 The goal is to maximize the size of the groups
and to minimize the number of groups.

1. A group must contain either 1, 2, 4, 8, or 16
cells, which are all powers of two. In the case
of a 3-variable map, 23 = 8 cells is the
maximum group.
2. Each cell in a group must be adjacent to one
or more cells in that same group.
3. Always include the largest possible number
of 1s in a group in accordance with rule 1.

4. Each 1 on the map must be included in at
least one group. The 1s already in a group
can be included in another group as long as
the overlapping groups include non common
1s.

 Examples -

 Solution – The grouping are shown below

 Solution – Determine the minimum product
term for each group.
a. For a 3-variable map:
1. A 1-cell group yields a 3-variable product term
3. A 4-cell group yields a 1-variable term
4. An 8-cell group yields a value of 1 for the
expression

 Solution – b. For a 4-variable map:
4. An 8-cell group yields a 1-variable term
5. A 16-cell group yields a value of 1 for the
expression

 Example –

 Solution – The resulting minimum product term
for each group is shown in fig above The
minimum SOP expressions for each of the
Karnaugh maps in the figure are:
(a)AB+BC+ABC (C) AB + AC + ABD
(b) B + A C + AC (d) D + ABC + BC

 Simplify z=f(A,B)=AB+AB using algebraic
equation and Karnaug hMap (K-Map).

 Simplify z=f(A,B)=AB+AB using algebraic
equation and Karnaug hMap (K-Map).
 Solution- z = AB+AB
= A(B+B)
= A

 Using Karnaugh Map.
z= AB+AB
 No of Variables 2 there for we required 4 cell
map. B A 0 1
0
1
1
1

 Using Karnaugh Map.
z= AB+AB
map. B A 0 1
0 A
1
1
1

 Solve
z= f(A,B) = AB+AB+AB

 Solve
map. B A 0 1
0
1
1 1
1

Karnaugh Map (K-Map)

 Simplify – using Karnaugh Map
ABC+ABC+ABC+ABC

ABC+ABC+ABC+ABC
A BC 00 01 11 10
0
1
1
1 1 1

ABC+ABC+ABC+ABC BC
A BC 00 01 11 10
0
1 AB
AC = AC+BC+AB
1
1 1 1

 Simplify using Karnaugh Map
f(A,B,C,D) = ABCD+ ABCD+ ABCD+ ABCD+
ABCD + ABCD + ABCD

ABCD + ABCD + ABCD
AB CD00 01 11 10
00
01
11
10
1
1
1 1 1 1
1

ABCD + ABCD + ABCD
AB CD00 01 11 10
00
01
11 AB
10
BC = AB+BC
1
1
1 1 1 1
1

 Don’t Care Condition: Sometimes input
combinations are of no concern
 Because they may not exist
• Example: BCD uses only 10 of possible 16
input combinations
 Since we “don’t care” what the output, we can
use these “don’t care” conditions for logic
minimization
• The output for a don’t care condition can be
either 0 or 1
 WE DON’T CARE!!!

 Don’t Care conditions denoted by:
 X, -, d, 2
• X is probably the most often used
• Can also be used to denote inputs
 Example: ABC = 1X1 = AC
• B can be a 0 or a 1

 Don’t Care conditions denoted by:

Adders – Half & Full Adder
 Adder is a circuit which adds two binary bits.
 In order to understand the functioning of either
of these circuits, we must speak of arithmetic
in terms
 “plus tables”, specifically the sum of adding
any two one–digit numbers: 2 + 2 = 4, 2 + 3 =
5, etc.
 add numbers that had more than one digit
each: 23 + 34 = 57, but 23 + 38 = 61.
 This adaptation of addition to multiple digit
numbers gives rise to the full adder.

 We begin with two simple sums, each
involving only single digits. 2 + 2 = 4, and 5 + 5
= 10.
 If these are so, why do we write the following
sum 25 + 25 as 25 + 25 = 50, and not as 25 +
25 = 4 10? What digit is written in the unit’s
column of the sum?
 The reason that we do not do this is the idea
of a carry from the unit’s column to the ten’s
column.

 The addition as follows: 1. 5 + 5 is 0, with a
carry–out of 1, which goes into the ten’s
column. 2. 2 + 2 is 4, but we have a carry–in of
1 from the unit’s column, so we say 2 + 2 + 1 =
5. The sum digit in this column is a 5.
 We have just noted that the decimal number 2
is represented in binary as 10.
 It must be the case that, in binary addition, we
have the sum as 1 + 1 = 10 This reads as “the
addition 1 + 1 results in a sum of 0 and a
carry–out of 1”.

 Recall the decimal sum 25 + 25.
1
2 5
2 5
5 0
 The 1 written above the numbers in the ten’s
column shows the carry–out from the unit’s
column as a carry–in to the ten’s column.

 The Half Adder: The half adder takes two
single bit binary numbers and produces a sum
and a carry–out, called “carry”.
 Here is the truth table description of a half
adder. We denote the sum A + B.
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

 Written as a standard sum, the last row
represents the following:
01
+01
1o
 The sum column indicates the number to be
written in the unit’s column, immediately below
the two 1’s. We write a 0 and carry a 1

 An adder is a digital logic circuit in electronics
that implements addition of numbers.
 In many computers and other types of
processors, adders are used to calculate
addresses, similar operations and table
indices in the ALU and also in other parts of
the processors.
 Adders are classified into two types: half adder
and full adder.
 The half adder circuit has two inputs: A and B,
which add two input digits and generate a
carry and sum.

 The full adder circuit has three inputs: A and
C, which add the three input numbers and
generate a carry and sum.

 An adder is a digital circuit that performs
addition of numbers.
 The half adder adds two binary digits called as
augend and addend and produces two outputs
as sum and carry; XOR is applied to both
inputs to produce sum and AND gate is
applied to both inputs to produce carry.
 The full adder adds 3 one bit numbers, where
two can be referred to as operands and one
can be referred to as bit carried in. And
produces 2-bit output, and these can be
referred to as output carry and sum.

 Half-adder Truth Table:

 Full Adder
 This adder is difficult to implement than a half-
adder.
 The difference between a half-adder and a full-
adder is that the full-adder has three inputs
and two outputs, whereas half adder has only
two inputs and two outputs.
 The first two inputs are A and B and the third
input is an input carry as C-IN.

 When a full-adder logic is designed, you string
eight of them together to create a byte-wide
adder and cascade the carry bit from one
adder to the next.
 The output carry is designated as C-OUT and
the normal output is designated as S.

 Full-adder Truth Table:

 With the truth-table, the full adder logic can be
implemented. You can see that the output S is
an XOR between the input A and the half-
adder, SUM output with B and C-IN inputs.
 We take C-OUT will only be true if any of the
two inputs out of the three are HIGH.
 So, we can implement a full adder circuit with
the help of two half adder circuits. At first, half
adder will be used to add A and B to produce
a partial Sum and a second half adder logic
can be used to add C-IN to the Sum produced
by the first half adder to get the final S output. 117RNB Global University, Bikaner.Course Code - 19004000

 If any of the half adder logic produces a carry,
there will be an output carry. So, COUT will be
an OR function of the half-adder Carry
outputs. Take a look at the implementation of
the full adder circuit shown below.

Adders – BCD Adder
 A BCD adder is a combinational circuit which
adds two bcd numbers.
 WHAT ARE BCD NUMBERS ?
 BCD is a class of encoding in which each
decimal digit is represented by some fixed
number of bits .Usually 4 or 8 bits are used.

 Up to 9 the bcd representation is same as the
decimal representation and after the 9.
 The first 4 digits in BCD representation is used
to show the first digit in decimal and next four
digits in BCD are used to represent next digit
in decimal.

 Truth Table:

 WHY only 4 BIT ADDER CAN NOT BE USED
?:
 when we provide two 4 bits BCD number to
the 4 bit adders, the output exceeds the BCD
range , or called BCD representation.
 WE WANT TO OUTPUT ALSO IN BCD . but
when we directly take the output of the 4 bit
adder then it will be a invalid representation .
 Therefore we need some mechanism through
which we can change the output of the 4 bit
adder into a valid BCD representation.

 For the numbers which does not satisfy the
condition of BCD , 6 is added . see in the
table, when the sum is 01010 the bcd
representation is obtained by adding 6, so
the representation in BCD is 1 0000.

Subtractor
 Subtractor : Subtractor is the one which used
to subtract two binary number(digit) and
provides Difference and Borrow as a output. In
digital electronics we have two types of
subtractor.
1. Half Subtractor
2. Full Subtractor

Subtractor – Half & Full
 Half Subtractor :Half Subtractor is used for
subtracting one single bit binary digit from
another single bit binary digit.The truth table of
Half Subtractor is shown below.

 Half Subtractor :Half Subtractor is used for
subtracting one single bit binary digit from
another single bit binary digit. The truth table
of Half Subtractor is shown below.

 Full Subtractor : A logic Circuit Which is used
for Subtracting Three Single bit Binary digit is
known as Full Subtractor. The Truth Table of
Full Subtractor is Shown Below.

Multiplexer & De-multiplexer
 A multiplexer (MUX) is a circuit that accept
many input but give only one output.
 A demultiplexer function exactly in the reverse
of a multiplexer, that is a demultiplexer
accepts only one input and gives many
outputs.
 Generally multiplexer and demultiplexer are
used together, because of the communication
systems are bi directional.

 Multiplexer: Multiplexer means many into one.
A multiplexer is a circuit used to select and
route any one of the several input signals to a
signal output.
 An simple example of an non electronic circuit
of a multiplexer is a single pole multiposition
switch.

 Multiplexer:
 However circuits that operate at high speed
require the multiplexer to be automatically
selected.
 A mechanical switch cannot perform this task
satisfactorily. Therefore, multiplexer used to
perform high speed switching are constructed
of electronic components.

 Multiplexer:
 Multiplexer handle two type of data that is
analog and digital. For analog application,
multiplexer are built of relays and transistor
switches. For digital application, they are built
from standard logic gates.
 The multiplexer used for digital applications,
also called digital multiplexer, is a circuit with
many input but only one output.

 Multiplexer:
 By applying control signals, we can steer any
input to the output. Few types of multiplexer
are 2-to-1, 4-to-1, 8-to-1, 16-to-1 multiplexer.
 Following figure shows the general idea of a
multiplexer with n input signal, m control
signals and one output signal.

 Multiplexer:

 Multiplexer: Understanding 4-to-1 Multiplexer:
The 4-to-1 multiplexer has 4 input bit, 2 control
bits, and 1 output bit.
 The four input bits are D0,D1,D2 and D3. only
one of this is transmitted to the output y.
 The output depends on the value of AB which
is the control input.
 The control input determines which of the input
data bit is transmitted to the output.

 For instance, as shown in fig. when AB = 00,
the upper AND gate is enabled while all other
AND gates are disabled. Therefore, data bit
D0 is transmitted to the output, giving Y = Do.
 If the control input is changed to AB =11, all
gates are disabled except the bottom AND
gate. In this case, D3 is transmitted to the
output and Y = D3.

 Multiplexer: Examples:
1. An example of 4-to-1 multiplexer is IC 74153
in which the output is same as the input.
2. Another example of 4-to-1 multiplexer is
45352 in which the output is the compliment
of the input.
3. Example of 16-to-1 line multiplexer is
IC74150.

 Multiplexer: Applications: Multiplexer are used
in various fields where multiple data need to
be transmitted using a single line. Following
are some of the applications of multiplexers
1. Communication system – Multiple data
2. Telephone network – Multiple Audio signals
3. Computer memory – Bus to storage
4. Transmission from the computer system of a
satellite - GPS

 De-Multiplexer (DEMUX): Demultiplexer
means one to many.
 A demultiplexer is a circuit with one input and
many output.
 By applying control signal, we can steer any
input to the output. Few types of demultiplexer
are 1-to 2, 1-to-4, 1-to-8 and 1-to 16
demultiplexer.

 De-Multiplexer:

 De-Multiplexer: The 1-to-4 demultiplexer has 1
input bit, 2 control bit, and 4 output bits.
 An example of 1-to-4 demultiplexer is IC
74155. The 1-to-4 demultiplexer is shown in
figure below-

 De-Multiplexer:

 De-Multiplexer: The input bit is labelled as
Data D. This data bit is transmitted to the data
bit of the output lines. This depends on the
value of AB, the control input.
 When AB = 01, the upper second AND gate is
enabled while other AND gates are disabled.
Therefore, only data bit D is transmitted to the
output, giving Y1 = Data.
 If D is low, Y1 is low. IF D is high,Y1 is high.
The value of Y1 depends upon the value of D.
All other outputs are in low state.

 De-Multiplexer: If the control input is changed
to AB = 10, all the gates are disabled except
the third AND gate from the top. Then, D is
transmitted only to the Y2 output, and Y2 =
Data.
 Example of 1-to-16 demultiplexer is IC 74154
it has 1 input bit, 4 control bits and 16 output
bit.

 De-Multiplexer: Applications of Demultiplexers
are:
1. Demultiplexer are also used for
reconstruction of parallel data and ALU
circuits.
2. Communication System - The multiplexer and
demultiplexer work together to carry out the
process of transmission and reception of data
in communication system.

 De-Multiplexer: Applications of Demultiplexers
are:
3. Demultiplexer is used to connect a single
source to multiple destinations.
4. Serial to parallel converter - A serial to
parallel converter is used for reconstructing
parallel data from incoming serial data
stream.

 De-Multiplexer:

Multiplier & Dividers
 Multiplication of binary numbers is performed
in the same way as in decimal numbers –
partial product: the multiplicand is multiplied by
each bit of the multiplier starting from the least
significant bit.

 Multiplication of two bits = A * B (AND) 0 * 0 =
0 0 * 1 = 0 1 * 0 = 0 1 * 1 = 1.

 To design a 4-bit binary number divider which
divides four bits by 5 (101 in binary).
 It can be easily solved using its truth table and
K-map.
 We needs to consider the quotient. So in order
to write the truth table you need only two
output variables. This is because the
maximum number that can be represented
using 4 bits is 15 (1111), which when divided
by 5 yields quotient 3 (0011).

 A3 to A0 represent the input in binary.F1 and
F0 represents the output in binary.
 This table is easily obtained since numbers 0
to 4 upon division with 5 gives 0 quotient. 5 to
9 yields 1. 10 to 14 yields 2 and so on.
 Now you can draw K-maps for F1 and F0.

Decoder - Encoder
 Encoders: An encoder is a combinational
circuit that performs the inverse operation of a
decoder.
 If a device output code has fewer bits than the
input code has, the device is usually called an
encoder. e.g. 2n-to-n, priority encoders.
 The simplest encoder is a 2n-to-n binary
encoder, where it has only one of 2n inputs = 1
and the output is the n-bit binary number
corresponding to the active input.
 It can be built from OR gates.

Decoder - Encoder
 Encoders: 4 to 2 Encoder

Decoder - Encoder
 Encoders: Octal to Binary Encoder
 Octal-to-Binary take 8 inputs and provides 3
outputs, thus doing the opposite of what the 3-
to-8 decoder does.
 At any one time, only one input line has a
value of 1.
 The figure below shows the truth table of an
Octal-to-binary encoder:

Decoder - Encoder
Io I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

Decoder - Encoder
 For an 8-to-3 binary encoder with inputs I0-I7
the logic expressions of the outputs Y0-Y2 are:
Y0 = I1 + I3 + I5 + I7
Y1= I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 +I7

Decoder - Encoder
 Based on the above equations, we can draw
the circuit as shown below

Decoder - Encoder
 Decoder: A combinational circuit that converts
binary information from n input lines to a
maximum of 2n unique output lines.
 n-to-m-line decoders: generate m (=2n or
fewer) minterms of n input variables A n-to-2n
decoder takes an n-bit input and produces 2n
outputs. The n inputs represent a binary
number that determines which of the 2n
outputs is uniquely true.

Decoder - Encoder
 Decoder:
 A 2-to-4 decoder operates according to the
following truth table. – The 2-bit input is called
S1S0, and the four outputs are Q0-Q3. – If the
input is the binary number i, then output Qi is
uniquely true.
 For instance, if the input S1 S0 = 10 (decimal
2), then output Q2 is true, and Q0, Q1, Q3 are
all false.

Decoder - Encoder
 Decoder:
 This circuit “decodes” a binary number into a
“one-of-four” code.
 Follow the design procedures from last time!
We have a truth table, so we can write
equations for each of the four outputs (Q0-
Q3), based on the two inputs (S0-S1).

Decoder - Encoder
 Decoder:
 In this case there’s not much to be simplified.
Here are the equations:
Q0 = S1’ S0’
Q1 = S1’ S0
Q2 = S1 S0’
Q3 = S1 S0

Decoder - Encoder
 Decoder:

Decoder - Encoder
 Decoder: Many devices have an additional
enable input, which is used to “activate” or
“deactivate” the device. • For a decoder,
 – EN=1 activates the decoder, so it behaves
as specified earlier. Exactly one of the outputs
will be 1.
 – EN=0 “deactivates” the decoder. By
convention, that means all of the decoder’s
outputs are 0.
 We can include this additional input in the
decoder’s truth table:

Decoder - Encoder
 Decoder:

Decoder - Encoder
 Decoder: 3 to 8 decoder

Decoder - Encoder
 COMPARATOR: Comparator compares
binary numbers.
 Logic comparing 2 bits: a and b

Decoder - Encoder
 COMPARATOR: Digital or Binary
Comparators are made up from
standard AND, NOR and NOT gates that
compare the digital signals present at their
input terminals and produce an output
depending upon the condition of those inputs.
 For example, along with being able to add and
subtract binary numbers we need to be able to
compare them and determine whether the
value of input A is greater than, smaller than or
equal to the value at input B etc.

Decoder - Encoder
 COMPARATOR: The digital comparator
accomplishes this using several logic gates
that operate on the principles of Boolean
Algebra.
 There are two main types of Digital
Comparator available and these are.
1. Identity Comparator – an Identity
Comparator is a digital comparator with only
one output terminal for when A = B, either A =
B = 1 (HIGH) or A = B = 0 (LOW).

Decoder - Encoder
 COMPARATOR: 2. Magnitude
Comparator – a Magnitude Comparator is a
digital comparator which has three output
terminals, one each for equality, A = B greater
than, A > B and less than A < B
 The purpose of a Digital Comparator is to
compare a set of variables or unknown
numbers, for example A (A1, A2, A3, …. An,
etc) against that of a constant or unknown
value such as B (B1, B2, B3, …. Bn, etc) and
produce an output condition or flag depending
upon the result of the comparison. 176RNB Global University, Bikaner.Course Code - 19004000

Decoder - Encoder
 COMPARATOR: For example, a magnitude
comparator of two 1-bits, (A and B) inputs
would produce the following three output
conditions when compared to each other.
A > B, A = B, A < B
 Which means: A is greater than B, A is equal
to B, or A is less than B
 This is useful if we want to compare two
variables and want to produce an output when
any of the above three conditions are
achieved.

Decoder - Encoder
 COMPARATOR:

Decoder - Encoder
 COMPARATOR: Then the operation of a 1-bit
digital comparator is given in the following
Truth Table.

Decoder - Encoder
 Code Conversion: Binary-to-Gray
 Below table shows natural-binary numbers
(upto 4-bit) and corresponding gray codes.

Decoder - Encoder
 Looking at gray-code (G3G2G1G0), we find
that any two subsequent numbers differ in only
one bit-change.
 The same table is used as truth-table for
designing a logic circuitry that converts a given
4-bit natural binary number into gray number.
For this circuit, B3 B2 B1 B0 are inputs while
G3 G2 G1 G0 are outputs.

Decoder - Encoder

Decoder - Encoder
 So that’s a simple three EX-OR gate circuit
that converts a 4-bit input binary number into
its equivalent 4-bit gray code. It can be
extended to convert more than 4-bit binary
numbers.

Decoder - Encoder
 Code Conversion: Gray - to - binary
 Once the converted code (now in Gray form) is
processed, we want the processed data back
in binary representation. So we need a
converter that would perform reverse
operation to that of earlier converter. This we
call a Gray-to-Binary converter.
 The design again starts from truth-table: .

Decoder - Encoder
 Code Conversion: Gray - to – binary

Decoder - Encoder

ROM & Programmable Logic
 The next three combinational components we
will study are: ROM, PLA, and PAL.
 ROM's PLA's and PAL's are storage
Components.
 A more precise definition is: a combinational
component is a circuit that doesn't have
memory of past inputs. (The outputs of a
combinational component are completely
determined by the current inputs.)

 ROM: A ROM is a combinational component
for storing data. The data might be a truth
table or the data might be the control words for
a microprogrammed CPU. (Control words in a
microprogrammed CPU interpret the macro
instructions understood by the CPU.)
 A ROM can be programmed at the factory or
in the field.
 The following image shows the generic form of
a ROM:

 ROM: (x = log2 n <=> 2x = n )

 ROM: An n x m ROM can store the truth table
for m functions defined on log2n variables:

 ROM: Example: Implement the following
functions in a ROM:
F0 = A
F1 = A'B' + AB
 Since a ROM stores the complete truth table
of a function (or you could say that a ROM
decodes every minterm of a function)
 The first step is to express each function as a
truth table.

 ROM:
 For the discussion that follows it may be
helpful to keep in mind the canonical form of
the function also:
F0 = AB' + AB
F1 = A'B' + AB

 ROM:
 We use a special notation to show the ROM
implementation of a function:

 ROM:
 The image above shows how a 4x3 ROM can
be used to implement the two functions F0 and
F1. (Note, there is room in the ROM for 3
functions of two variables. F2 isn't used.

 ROM:
 ROMs programmed at the factory are called
mask ROMS because during fabrication the
circuit patterns are determined by a mask.
There are several different types of field
programmable ROMS:
 PROM (Programmable Read-Only Memory) - This
is the type that was discussed above. Connections
are fused and burned in the field with a PROM
programmer.

 ROM:
 EPROM (Erasable Programmable Read-Only
Memory) - This type of ROM can be re-written by
shining an ultraviolet light through a window on the
IC.
 EEPROM (Electrically Erasable Programmable
Read-Only Memory) - Rather than ultraviolet light
an extra high voltage is used to re-write the
contents of this type of ROM.
 Flash Memory - Instead of requiring extra high
voltages flash memory devices work with regular
device voltages.

 Programmable Logic: A programmable logic
device works like a ROM but is a more efficient
solution for implementing sparse (Matrix in which non
zero elements are less than no of zeros) output
functions (Not all minterms are decoded).
 There are two types of programmable logic devices:
1. PLA (Programmable Logic Array)
2. PAL (Programmable Array Logic)

 Programmable Array Logic (PAL) :
 PAL is a programmable logic device that has
Programmable AND array & fixed OR array.
 The advantage of PAL is that we can generate only
the required product terms of Boolean function instead
of generating all the min terms by using programmable
AND gates.
 The block diagram of PAL is shown in the following
figure.

 Here, the inputs of AND gates are programmable.
That means each AND gate has both normal and
complemented inputs of variables.
 So, based on the requirement, we can program any of
those inputs. So, we can generate only the
required product terms by using these AND gates.
 the inputs of OR gates are not of programmable type.
So, the number of inputs to each OR gate will be of
fixed type. Hence, apply those required product terms
to each OR gate as inputs.
 Therefore, the outputs of PAL will be in the form
of sum of products form.

 Example: Let us implement the following Boolean
functions using PAL.
A=XY+XZ′
A=XY′+YZ′
 The given two functions are in sum of products form.
There are two product terms present in each Boolean
function. So, we require four programmable AND
gates & two fixed OR gates for producing those two
functions.
 The corresponding PAL is shown in the following
figure.

 Example:

 Example:
 The programmable AND gates have the access of
both normal and complemented inputs of variables. In
the above figure, the inputs X, X′ , Y, Y′, Z & Z′, are
available at the inputs of each AND gate.
 So, program only the required literals in order to
generate one product term by each AND gate. The
symbol ‘X’ is used for programmable connections.
 The symbol ‘X’ is used for programmable connections.

 Example:
 Here, the inputs of OR gates are of fixed type. So, the
necessary product terms are connected to inputs of
each OR gate.
 So that the OR gates produce the respective Boolean
functions.
 The symbol ‘.’ is used for fixed connections.

 Programmable Logic Array (PLA) :
 PLA is a programmable logic device that has
both Programmable AND array &
Programmable OR array. Hence, it is the most
flexible PLD.
 The block diagram of PLA is shown in the
following figure.

 Here, the inputs of AND gates are programmable.
That means each AND gate has both normal and
complemented inputs of variables.
 Based on the requirement, we can program any of
those inputs. So, we can generate only the
required product terms by using these AND gates.
 The inputs of OR gates are also programmable. So,
we can program any number of required product
terms, since all the outputs of AND gates are applied
as inputs to each OR gate. Therefore, the outputs of
PAL will be in the form of sum of products form.

 Example-
 Let us implement the following Boolean
functions using PLA.
A=XY+XZ′
B=XY′+YZ+XZ′
 The given two functions are in sum of products form.
The number of product terms present in the given
Boolean functions A & B are two and three
respectively. One product term, Z′XZ′X is common in
each function.

 we require four programmable AND gates & two
programmable OR gates for producing those two
functions. The corresponding PLA is shown in the
following figure.

 The programmable AND gates have the access of
both normal and complemented inputs of variables. In
the above figure, the inputs X, X′, Y, Y′, Z & Z′, are
available at the inputs of each AND gate. So, program
only the required literals in order to generate one
product term by each AND gate.
 All these product terms are available at the inputs of
each programmable OR gate. But, only program the
required product terms in order to produce the
respective Boolean functions by each OR gate. The
symbol ‘X’ is used for programmable connections.

FPGA - Field Programmable Gate
Arrays
 Field Programmable Gate Arrays (FPGAs) are
semiconductor devices that are based around a matrix
of configurable logic blocks (CLBs) connected via
programmable interconnects.
 FPGAs can be reprogrammed to desired application or
functionality requirements after manufacturing.
 This feature distinguishes FPGAs from Application
Specific Integrated Circuits (ASICs), which are custom
manufactured for specific design tasks.

Arrays
 Field-programmable gate arrays (FPGAs) are
reprogrammable silicon chips. Ross Freeman, the
cofounder of Xilinx, invented the first FPGA in 1985.
 FPGA chip adoption across all industries is driven by
the fact that FPGAs combine the best parts of
application-specific integrated circuits (ASICs) and
processor-based systems.
 FPGAs provide hardware-timed speed and reliability,
but they do not require high volumes to justify the
large upfront expense of custom ASIC design.
 Reprogrammable silicon also has the same flexibility
of software running on a processor-based system, but
it is not limited by the number of processing cores
available. 212RNB Global University, Bikaner.Course Code - 19004000

Arrays
 Although one-time programmable (OTP) FPGAs are
available, the dominant types are SRAM based which
can be reprogrammed as the design evolves.
 Applications of FPGAs:
1. Aerospace & Defence - Radiation-tolerant FPGAs
along with intellectual property for image processing,
waveform generation, and partial reconfiguration for
SDRs (Special Drawing Rights).

Arrays
2. ASIC Prototyping - ASIC prototyping with FPGAs
enables fast and accurate SoC (System on Chip)
system modeling and verification of embedded
software
3. Automotive - Automotive silicon and IP solutions for
gateway and driver assistance systems, comfort,
convenience, and in-vehicle infotainment.
4. Consumer Electronics - Cost-effective solutions
enabling next generation, full-featured consumer
applications, such as converged handsets, digital flat
panel displays, information appliances, home
networking, and residential set top boxes.

Arrays
5. Data Center - Designed for high-bandwidth, low-
latency servers, networking, and storage applications
to bring higher value into cloud deployments.
6. High Performance Computing and Data Storage -
Solutions for Network Attached Storage (NAS),
Storage Area Network (SAN), servers, and storage
appliances.
7. Industrial higher degrees of flexibility, faster time-to-
market, and lower overall non-recurring engineering
costs (NRE) for a wide range of applications such as
industrial imaging and surveillance, industrial
automation, and medical imaging equipment.

Arrays
8. Medical - For diagnostic, monitoring, and therapy
applications.
9. Security - offers solutions that meet the evolving
needs of security applications, from access control to
surveillance and safety systems.
10. Wired Communications - End-to-end solutions for the
Reprogrammable Networking Linecard Packet
Processing, Framer/MAC, serial backplanes, and
more.

TTL IC
 Transistor–transistor logic (TTL) is a class of digital
circuits built from bipolar junction transistors (BJTs)
and resistors.
 It is called transistor–transistor logic because
transistors perform both the logic function (e.g., AND)
and the amplifying function (compare with resistor–
transistor logic (RTL) and diode–transistor logic (DTL).
 TTL integrated circuits (ICs) were widely used in
applications such as computers, industrial controls,
test equipment and instrumentation, consumer
electronics, and synthesizers.

Quine McCluskey Tabulation Method
 The Quine McCluskey tabulation method is a very
useful and convenient tool for simplification of Boolean
functions for large numbers of variables.
 As we know that the Karnaugh map method is a very
useful and convenient tool for simplification of Boolean
functions as long as the number of variables does not
exceed four.
 But for case of large number of variables, the
visualization and selection of patterns of adjacent cells
in the Karnaugh map becomes complicated and too
much difficult.
 For those cases Quine McCluskey tabulation method
takes vital role to simplify the Boolean expression.

 The Quine McCluskey tabulation method is a specific
step-by-step procedure to achieve guaranteed,
simplified standard form of expression for a function.
 Now take an example to understand the process. Let
we have a Boolean expression F=
(0,1,2,3,5,7,8,10,14,15) and we have to minimize that
by Quine McCluskey tabulation method.

 To start with we have to make table and kept all the
numbers in same group whose binary numbers
containing equal 1s. Like 1,2,8 (0001,0010,1000) are
in same group because all has equal 1s in their binary
number. See in below table.

 We have to add another column to right side of that
table naming 1stNow between two groups depending
upon number of 1s, we have to find similar number
with only one position change to 0 to 1.
 See the binary number of 1 (0001) from first group and
3 (0011) from second group. Both the number are
similar only second bit position from LSB change 0 to
1. So in new column we should write (1,3) 00-1 (in
place of number change we put “–“ on that). In this
way we have to check entire table and make new
column accordingly.

 Now we have to again add another column to right
side of that table naming 2nd Now between two groups
from 1st column, we have to find similar number with
only one position change to 0 to 1.
 See the binary number of (0,1) (000-) and (2,3) (001-).
Both the numbers are similar only second bit position
from LSB change 0 to 1. So in new column we should
write (0,1,2,3) 00– (in place of number change we put
“–“ on that). In this way we have to check entire table
and make new column accordingly.

 Most of we completed now we have to mark
what are those combination we used in
2nd Like for first one (0,1,2,3), we used 0,1 and
2,3 combination from 1st column.
 Now make the final table for getting the
simplified Boolean expression. Now question
is how it possible? We have to make a table
with all combination of 2nd column and unused
portion of 1st

 We can keep one cross in any one column. So
we have to cut some raw which was most
benefited entirely to make one cross at one
column. But keep mind that we should not cut
those raw which can give as cross at single
column.

 Now we can get the simplified Boolean
expression from above table and it’s
correspond 2nd column value. We have to take
uncut row with its 2nd column value and
convert it with ABCD variable. Like where you
find 0 take complement value, 1 for
uncomplement value and “–“ for no variable.

0,8,2,10 (- 0 – 0) =B^D^
1,3,5,7 (0 – – 1) = A^D
14,15 (1 1 1 -) =ABC
So answer will be F =B^D^+A^D+ABC

 Example - Let us simplify the following
Boolean
Function, f(W,X,Y,Z)=∑m(2,6,8,9,10,11,14,15)
using Quine-McClukey tabular method.

 Example -
Group Minterm W X Y Z
GA1 2 0 0 1 0
8 1 0 0 0
GA2 6 0 1 1 0
9 1 0 0 1
10 1 0 1 0
GA 11 1 0 1 1
14 1 1 1 0
GA4 15 1 1 1 1

 Example -
GB1 2,6 0 - 1 0
2,10 - 0 0 0
8, 9 1 0 0 -
8, 10 1 0 - 1
GB2 6,14 - 1 1 0
9,11 1 0 - 1
10,11 1 0 1 -
10,14 1 - 1 0
GB3 11,15 1 - 1 1
14,15 1 1 1 -

 Example -
GB1 2,6,10,14 - - 1 0
2,10,6,14 - - 1 0
8, 9,10,11 1 0 - -
8,10,9,11 1 0 - -
GB2 10,11,14,15 1 - 1 -
10,14,11,15 1 - 1 -

 Example -
GB1 2,6,10,14 - - 1 0
8, 9,10,11 1 0 - -
GB2 10,11,14,15 1 - 1 -

 Example -
Min
terms
/
Prime
Implic
ants
2 6 8 9 10 11 14 15
YZ’ 1 1 1 1
WX’ 1 1 1 1
WY 1 1 1 1

 Example - Let us simplify the following
Boolean.
 f(W,X,Y,Z) = YZ’ + WX’ + WY.

 Example - Let us simplify the following.
F (a,b,c,d) = Ʃ(0,5,8,9,10,11,14,15)

 Example - Let us simplify the following.
F (a,b,c,d) = Ʃ(0,5,8,9,10,11,14,15)
Ans – AB’+AC+B’C’D’+A’BC’D

Reviews
 Simplification of Boolean function by K-Map.
 Simplification of Boolean function by Q. M.
 Adder – Half, Full, BCD, High Speed.
 Subtractor, Multiplier, dividers.
 ALU, Code Conversion – Encoder, Decoder.
 Comparators, Multiplexers, Demultiplexers.
 Implementation using ICs.

Thank You!
RNB Global University, Bikaner. 243Course Code - 19004000

Boolean algebra simplification and combination circuits

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