Ch4 Boolean Algebra And Logic Simplication1

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Ch4 Boolean Algebra And Logic Simplication1

  1. 1. Ch. 4 Boolean Algebra and Logic Simplification <ul><li>Boolean Operations and Expressions </li></ul><ul><li>Laws and Rules of Boolean Algebra </li></ul><ul><li>Boolean Analysis of Logic Circuits </li></ul><ul><li>Simplification Using Boolean Algebra </li></ul><ul><li>Standard Forms of Boolean Expressions </li></ul><ul><li>Truth Table and Karnaugh Map </li></ul><ul><li>Programmable Logic: PALs and GALs </li></ul><ul><li>Boolean Expressions with VHDL </li></ul>
  2. 2. Introduction <ul><li>Boolean Algebra </li></ul><ul><li>George Boole(English mathematician), 1854 </li></ul><ul><ul><li>“ An Investigation of the Laws of Thought, on Which Are Founded the Mathematical Theories of Logic and Probabilities” </li></ul></ul><ul><ul><li>Boolean Algebra </li></ul></ul><ul><ul><li>{(1,0), Var, (NOT, AND, OR), Thms} </li></ul></ul><ul><li>Mathematical tool to expression and analyze digital (logic) circuits </li></ul><ul><li>Claude Shannon, the first to apply Boole’s work, 1938 </li></ul><ul><ul><li>“ A Symbolic Analysis of Relay and Switching Circuits” at MIT </li></ul></ul><ul><li>This chapter covers Boolean algebra, Boolean expression and its evaluation and simplification, and VHDL program </li></ul>
  3. 3. <ul><li>Boolean functions : NOT, AND, OR, </li></ul><ul><li> exclusive OR(XOR) : odd function </li></ul><ul><li> exclusive NOR(XNOR) : even function(equivalence) </li></ul>Basic Functions
  4. 4. <ul><li>AND </li></ul><ul><ul><li>Z=X  Y or Z=XY </li></ul></ul><ul><ul><li>Z=1 if and only if X=1 and Y=1 , otherwise Z=0 </li></ul></ul><ul><li>OR </li></ul><ul><ul><li>Z=X + Y </li></ul></ul><ul><ul><li>Z=1 if X=1 or if Y=1, or both X=1and Y=1. Z=0 if and only if X=0 and Y=0 </li></ul></ul><ul><li>NOT </li></ul><ul><ul><li>Z=X  or </li></ul></ul><ul><ul><li>Z=1 if X=0, Z=0 if X=1 </li></ul></ul>Basic Functions ( 계속 )
  5. 5. Basic Functions ( 계속 )
  6. 6. Boolean Operations and Expressions <ul><li>Boolean Addition </li></ul><ul><ul><li>Logical OR operation </li></ul></ul><ul><li>Ex 4-1) Determine the values of A, B, C, and D that make the sum term A+B’+C+D’ </li></ul><ul><li>Sol) all literals must be ‘0’ for the sum term to be ‘0’ </li></ul><ul><li> A+B’+C+D’=0+1’+0+1’=0  A=0, B=1, C=0, and D=1 </li></ul><ul><li>Boolean Multiplication </li></ul><ul><ul><li>Logical AND operation </li></ul></ul><ul><li>Ex 4-2) Determine the values of A, B, C, and D for AB’CD’=1 </li></ul><ul><li>Sol) all literals must be ‘1’ for the product term to be ‘1’ </li></ul><ul><li> AB’CD’=10’10’=1  A=1, B=0, C=1, and D=0 </li></ul>
  7. 7. Basic Identities of Boolean Algebra The relationship between a single variable X, its complement X  , and the binary constants 0 and 1
  8. 8. Laws of Boolean Algebra <ul><li>Commutative Law </li></ul><ul><ul><li>the order of literals does not matter </li></ul></ul><ul><ul><li>A + B = B + A </li></ul></ul><ul><ul><li>A B = B A </li></ul></ul>
  9. 9. <ul><li>Associative Law </li></ul><ul><ul><li>the grouping of literals does not matter </li></ul></ul><ul><ul><li>A + (B + C) = (A + B) + C (=A+B+C) </li></ul></ul><ul><ul><li>A(BC) = (AB)C (=ABC) </li></ul></ul>Laws of Boolean Algebra ( 계속 )
  10. 10. <ul><li>Distributive Law : A(B + C) = AB + AC </li></ul>Laws of Boolean Algebra ( 계속 ) A B C X Y X=Y
  11. 11. <ul><li>(A+B)(C+D) = AC + AD + BC + BD </li></ul>Laws of Boolean Algebra ( 계속 ) A B C D X Y X=Y
  12. 12. <ul><li>A+0=A </li></ul><ul><li>In math if you add 0 you have changed nothing in Boolean Algebra ORing with 0 changes nothing </li></ul>A X X=A+0=A Rules of Boolean Algebra
  13. 13. <ul><li>A+1=1 </li></ul><ul><li>ORing with 1 must give a 1 since if any input is 1 an OR gate will give a 1 </li></ul>Rules of Boolean Algebra ( 계속 ) A X X=A+1=1
  14. 14. <ul><li>A•0=0 </li></ul><ul><li>In math if 0 is multiplied with anything you get 0. If you AND anything with 0 you get 0 </li></ul>Rules of Boolean Algebra ( 계속 ) A X X=A0 = 0
  15. 15. <ul><li>A•1 =A </li></ul><ul><li>ANDing anything with 1 will yield the anything </li></ul>Rules of Boolean Algebra ( 계속 ) A X X=A1=A A
  16. 16. <ul><li>A+A = A </li></ul><ul><li>ORing with itself will give the same result </li></ul>Rules of Boolean Algebra ( 계속 ) A A X A=A+A =A
  17. 17. <ul><li>A+A’=1 </li></ul><ul><li>Either A or A’ must be 1 so A + A’ =1 </li></ul>Rules of Boolean Algebra ( 계속 ) A A’ X X=+A’=1
  18. 18. <ul><li>A•A = A </li></ul><ul><li>ANDing with itself will give the same result </li></ul>Rules of Boolean Algebra ( 계속 ) A A X A=AA=A
  19. 19. <ul><li>A•A’ =0 </li></ul><ul><li>In digital Logic 1’ =0 and 0’ =1, so AA’=0 since one of the inputs must be 0. </li></ul>Rules of Boolean Algebra ( 계속 ) A A’ X X=AA’=0
  20. 20. <ul><li>A = (A’)’ </li></ul><ul><li>If you not something twice you are back to the beginning </li></ul>Rules of Boolean Algebra ( 계속 ) A X X=(A’)’=A
  21. 21. Rules of Boolean Algebra ( 계속 ) A B X <ul><li>A + AB = A </li></ul>
  22. 22. <ul><li>A + A’B = A + B </li></ul><ul><li>If A is 1 the output is 1 If A is 0 the output is B </li></ul>Rules of Boolean Algebra ( 계속 ) A B X Y X=Y
  23. 23. Rules of Boolean Algebra ( 계속 ) A B C X Y <ul><li>(A + B)(A + C) = A + BC </li></ul>
  24. 24. <ul><li>DeMorgan’s Theorem </li></ul><ul><ul><li>F  (A,A  ,  , + , 1,0) = F(A  , A, + ,  ,0,1) </li></ul></ul><ul><ul><li>(A • B)’ = A’ + B’ and (A + B)’ = A’ • B’ </li></ul></ul><ul><ul><li>DeMorgan’s theorem will help to simplify digital circuits using NORs and NANDs his theorem states </li></ul></ul>DeMorgan’s Theorems
  25. 26. Look at (A +B +C + D)’ = A’ • B’ • C’ • D’
  26. 27. <ul><li>Ex 4-3) Apply DeMorgan’s theorems to (XYZ)’ and (X+Y+Z)’ </li></ul><ul><li>Sol) (XYZ)’=X’+Y’+Z’ and (X+Y+Z)’=X’Y’Z’ </li></ul><ul><li>Ex 4-5) Apply DeMorgan’s theorems to </li></ul><ul><li>(a) ((A+B+C)D)’ (b) (ABC+DEF)’ (c) (AB’+C’D+EF)’ </li></ul><ul><li>Sol) (a) ((A+B+C)D)’= (A+B+C)’+D’=A’B’C’+D’ </li></ul><ul><li>(b) (ABC+DEF)’=(ABC)’(DEF)’=(A’+B’+C’)(D’+E’+F’) </li></ul><ul><li>(c) (AB’+C’D+EF)’=(AB’)’(C’D)’(EF)’=(A’+B)(C+D’)(E’+F’) </li></ul>
  27. 28. Boolean Analysis of Logic Circuits <ul><li>Boolean Expression for a Logic Circuit </li></ul>Figure 4-16 A logic circuit showing the development of the Boolean expression for the output.
  28. 29. <ul><li>Constructing a Truth Table for a Logic Circuit </li></ul><ul><ul><li>Convert the expression into the min-terms containing all the input literals </li></ul></ul><ul><ul><li>Get the numbers from the min-terms </li></ul></ul><ul><ul><li>Putting ‘1’s in the rows corresponding to the min-terms and ‘0’s in the remains </li></ul></ul><ul><ul><li>Ex) A(B+CD)= AB(C+C’) (D+D’) +A(B+B’)CD = ABC(D+D’) +ABC’(D+D’) +ABCD+AB’CD = ABCD +ABCD’+ABC’D+ABC’D’ + ABCD +AB’CD = ABCD +ABCD’+ABC’D+ABC’D’ +AB’CD =m11+m12+m13+m14+m15=  (11,12,13,14,15) </li></ul></ul>
  29. 30. Truth Table from Logic Circuit A(B+CD)=m11+m12+m13+m14+m15 =  (11,12,13,14,15) Output Input 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 A(B+CD) D C B A
  30. 31. <ul><li>Ex 4-8) Using Boolean algebra, simplify this expression </li></ul><ul><li>AB+A(B+C)+B(B+C) </li></ul><ul><li>Sol) AB+AB+AC+BB+BC =B(1+A+A+C)+AC= B+AC </li></ul>Simplification Using Boolean Algebra
  31. 32. <ul><li>Ex 4-9) Simplify the following Boolean expression </li></ul><ul><li>(AB’(C+BD)+A’B’)C </li></ul><ul><li>Sol) (AB’C+ A B’B D +A’B’)C=A B’CC +A’ B’C =(A+A’)B’C=B’C </li></ul><ul><li>Ex 4-10) Simplify the following Boolean expression </li></ul><ul><li>A’ BC +A B’C’ +A’ B’C’ +AB’C+A BC </li></ul><ul><li>Sol) (A+A’) BC +(A+A’) B’C’ +AB’C=BC+ B’ C’+A B’ C =BC+B’(C’+AC)=BC+B’(C’+A)=BC+B’C’+AB’ </li></ul><ul><li>Ex 4-11) Simplify the following Boolean expression </li></ul><ul><li>(AB +AC)’+A’B’C </li></ul><ul><li>Sol) (AB)’(AC)’+A’B’C=(A’+ B’)(A’+C’)+ A’ B’C =A’+A’B’ +A’C’+B’C+A’B’C =A’(1+B’+C’+B’C)+B’C=A’+B’C’ </li></ul>
  32. 33. Standard Forms of Boolean Expressions <ul><li>The Sum-of-Products(SOP) Form </li></ul><ul><li>Ex) AB+ABC, ABC+CDE+B’CD’ </li></ul><ul><li>The Product-of-Sums(POS) Form </li></ul><ul><li>Ex) (A+B)(A+B+C), (A+B+C)(C+D+E)(B’+C+D’) </li></ul><ul><li>Principle of Duality : SOP  POS </li></ul><ul><li>Domain of a Boolean Expression </li></ul><ul><ul><li>The set of variables contained in the expression </li></ul></ul><ul><ul><li>Ex) A’B+AB’C : the domain is {A, B, C} </li></ul></ul>
  33. 34. <ul><li>Implementation of a SOP Expression </li></ul><ul><ul><li>AND-OR logic </li></ul></ul><ul><li>Conversion of General Expression to SOP Form </li></ul><ul><ul><li>A(B+CD)=AB +ACD </li></ul></ul><ul><li>Ex 4-12) Convert each of the following expressions to SOP form: (a) AB+B(CD+EF) (b) (A+B)(B+C+D) </li></ul><ul><ul><li>Sol) (a) AB+B(CD+EF)=AB+BCD+BEF </li></ul></ul><ul><ul><li> (b) (A+B)(B+C+D)=AB+AC+AD+ BB+BC+BD =B(1+A+C+D)+ AC+AD=B+AC+AD </li></ul></ul>
  34. 35. Standard SOP Form (Canonical SOP Form) <ul><ul><li>For all the missing variables, apply (x+x’)=1 to the AND terms of the expression </li></ul></ul><ul><ul><li>List all the min-terms in forms of the complete set of variables in ascending order </li></ul></ul><ul><li>Ex 4-13) Convert the following expression into standard SOP form: AB’C+A’B’+ABC’D </li></ul><ul><li>Sol) domain={A,B,C,D}, AB’C(D’+D)+A’B’(C’+C)(D’+D)+ABC’D =AB’CD’+AB’CD+A’B’C’D’+A’B’C’D+A’B’CD’+A’B’CD+ABC’D =1010+1011+0000+0001+0010+0011+1101 =0+1+2+3+10+11+13 =  (0,1,2,3,10,11,13) </li></ul>
  35. 36. Product-of-Sums Form <ul><li>Implementation of a POS Expression </li></ul><ul><ul><li>OR-AND logic </li></ul></ul>
  36. 37. Standard POS Form (Canonical POS Form) <ul><ul><li>For all the missing variables, apply (x’x)=0 to the OR terms of the expression </li></ul></ul><ul><ul><li>List all the max-terms in forms of the complete set of variables in ascending order </li></ul></ul><ul><li>Ex 4-15) Convert the following expression into standard POS form: (A+B’+C)(B’+C+D’)(A+B’+C’+D) </li></ul><ul><li>Sol) domain={A,B,C,D}, (A+B’+C)(B’+C+D’)(A+B’+C’+D) =(A+B’+C+D’D)(A’A+B’+C+D’)(A+B’+C’+D) = (A+B’+C+D’) (A+B’+C+D) (A’+B’+C+D’) (A+B’+C+D’)(A+B’+C’+D)=(0100) )(0101)(0110)(1101)=  (4,5,6,13) </li></ul>
  37. 38. Converting Standard SOP to Standard POS <ul><li>Step 1. Evaluate each product term in the SOP expression. Determine the binary numbers that represent the product terms </li></ul><ul><li>Step 2. Determine all of the binary numbers not included in the evaluation in Step 1 </li></ul><ul><li>Step 3. Write in equivalent sum term for each binary number Step 2 and expression in POS form </li></ul><ul><li>Ex 4-17) Convert the following SOP to POS </li></ul><ul><li>Sol) SOP= A’B’C’+A’BC’+A’BC+AB’C+ABC=0+2+3+5+7 =  (0,2,3,5,7) </li></ul><ul><li>POS=(1)(4)(6) =  (1, 4, 6) (=(A+B+C’)(A’+B+C)(A’+B’+C)) </li></ul>
  38. 39. Boolean Expressions and Truth Tables <ul><li>Converting SOP Expressions to Truth Table Format </li></ul><ul><li>Ex 4-18) A’B’C+AB’C’+ABC =  (1,4,7) </li></ul>ABC 1 1 1 1 0 1 1 0 0 1 0 1 AB’C’ 1 1 0 0 0 0 1 1 0 0 1 0 A’B’C 1 0 0 1 0 0 0 0 Product Term Output X Inputs A B C
  39. 40. <ul><li>Converting POS Expressions to Truth Table Format </li></ul><ul><li>Ex 4-19) (A+B+C)(A+B’+C)(A+B’+C’)(A’+B+C’)(A’+B’+C) = (000)(010)(011)(101)(110) =  (0,2,3,5,6) </li></ul>1 1 1 1 A’+B’+C 0 1 1 0 A’+B+C’ 0 1 0 1 1 1 0 0 A+B’+C’ 0 0 1 1 A+B’+C 0 0 1 0 1 0 0 1 A+B+C 0 0 0 0 Sum Term Output X Inputs A B C
  40. 41. <ul><li>Ex 4-20) Determine standard SOP and POS from the truth table </li></ul><ul><li>Sol) (a) Standard SOP </li></ul><ul><li>F=A’BC+AB’C’+ABC’+ABC </li></ul><ul><li>(b) Standard POS </li></ul><ul><li>F=(A+B+C)(A+B+C’)(A+B’+C) </li></ul><ul><li>(A’+B+C’) </li></ul>1 1 1 1 1 1 1 0 0 1 0 1 1 1 0 0 1 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Output X Inputs A B C
  41. 42. Boolean Expression Truth Table Logic Diagram
  42. 43. Karnaugh Map <ul><li>Simplification methods </li></ul><ul><ul><li>Boolean algebra(algebraic method) </li></ul></ul><ul><ul><li>Karnaugh map(map method)) </li></ul></ul><ul><ul><li>Quine-McCluskey(tabular method) </li></ul></ul>XY+XY  =X(Y+Y  )=X
  43. 45. Three- and Four-input Kanaugh maps Gray code
  44. 48. Gray code sequence generation
  45. 49. F(X,Y,Z)=  m(0,1,2,6) =(XY  +YZ)  =X’Y’ + YZ’
  46. 50. <ul><li>Example) F(X,Y,Z)=  m(2,3,4,5) =X  Y+XY  </li></ul>0 1 3 2 4 5 7 6
  47. 51. Example) F(X,Y,Z)=  m(0,2,4,6) = X  Z  +XZ  =Z  (X  +X)=Z 
  48. 52. <ul><li>Four-Variable Map </li></ul><ul><ul><li>16 minterms : m 0 ~ m 15 </li></ul></ul><ul><ul><li>Rectangle group </li></ul></ul><ul><ul><li>2-squares(minterms) : 3-literals product term </li></ul></ul><ul><ul><li>4-squares : 2-literals product term </li></ul></ul><ul><ul><li>8-squares : 1-literals product term </li></ul></ul><ul><ul><li>16-squares : logic 1 </li></ul></ul>
  49. 55. F(W, X,Y,Z)=  m(0,2,7,8,9,10,11) = WX’ + X’Z’ + W’XYZ
  50. 56. Karnaugh Map SOP Minimization <ul><li>Mapping a Standard SOP Expression </li></ul>
  51. 57. <ul><li>Ex 4-21) Ex 4-22) </li></ul>
  52. 58. <ul><li>Mapping a Nonstandard SOP Expression </li></ul><ul><ul><li>Numerical Expression of a Nonstandard Product Term </li></ul></ul><ul><ul><li>Ex 4-23) A’+AB’+ABC’ </li></ul></ul><ul><ul><li>A’ AB’ ABC’ </li></ul></ul><ul><ul><li>0 00 10 0 110 </li></ul></ul><ul><ul><li>0 01 10 1 </li></ul></ul><ul><ul><li>0 10 </li></ul></ul><ul><ul><li>0 11 </li></ul></ul>
  53. 59. <ul><li>Ex 4-24) B’C’+AB’+ABC’+AB’CD’+A’B’C’D+AB’CD </li></ul><ul><li>B’C’ AB’ ABC’ AB’CD’ A’B’C’D AB’CD </li></ul><ul><li>0000 1000 1100 1010 0001 1011 </li></ul><ul><li>0001 1001 1101 </li></ul><ul><li>1000 1010 </li></ul><ul><li>1001 1011 </li></ul>
  54. 60. Karnaugh Map Simplification of SOP Expressions <ul><li>Group 2 n adjacent cells including the largest possible number of 1s in a rectangle or square shape, 1<=n </li></ul><ul><li>Get the groups containing all 1s on the map for the expression </li></ul><ul><li>Determine the minimum SOP expression form map </li></ul>
  55. 61. <ul><li>Ex 4-26) F=B+A’C+AC’D </li></ul>
  56. 62. <ul><li>Ex 4-27) (a) AB+BC+A’B’C’ (b) B’+AC+A’C’ </li></ul><ul><li> (c) A’C’+A’B+AB’D (d) D’+BC’+AB’C </li></ul>
  57. 63. <ul><li>Ex 4-28) Minimize the following expression </li></ul><ul><li>AB’C+A’BC+A’B’C+A’B’C’+AB’C’ </li></ul><ul><li>Sol) B’+A’C </li></ul>
  58. 64. <ul><li>Ex 4-29) Minimize the following expression </li></ul><ul><li>B’C’D’ +A’BC’D’+ABC’D’+A’B’CD+AB’CD+A’B’CD’+A’BCD’ +ABCD’+AB’CD’ </li></ul><ul><li>Sol) D’+B’C </li></ul>
  59. 65. Mapping Directly from a Truth Table
  60. 66. Don’t Care Conditions <ul><li>it really does not matter since they will never occur(its output is either ‘0’ or ‘1’) </li></ul><ul><li>The don’t care terms can be used to advantage on the Karnaugh map </li></ul>
  61. 67. Karnaugh Map POS Minimization <ul><li>Use the Duality Principle </li></ul><ul><ul><li>F(A,A  ,  , + , 1,0)  F * (A,A  , + ,  ,0,1) </li></ul></ul><ul><ul><li>SOP  POS </li></ul></ul>
  62. 68. <ul><li>Ex 4-30) (A’+B’+C+D)(A’+B+C’+D’)(A+B+C’+D) (A’+B’+C’+D’)(A+B+C’+D’) </li></ul><ul><li>Sol) </li></ul>
  63. 69. <ul><li>Ex 4-31) (A+B+C)(A+B+C’)(A+B’+C)(A+B’+C’)(A’+B’+C) </li></ul><ul><li>Sol) (0+0+0)(0+0+1)(0+1+0)(0+1+1)(1+1+0)=A(B’+C) </li></ul><ul><li> AC+AB’=A(B’+C) </li></ul>
  64. 70. <ul><li>Ex 4-32) (B+C+D) (A+B+C’+D)(A’+B+C+D’)(A+B’+C+D)(A’+B’+C+D) </li></ul><ul><li>Sol) (B+C+D)=(A’A+B+C+D)=(A’+B+C+D)(A+B+C+D) </li></ul><ul><li>(1+0+0+0)(0+0+0+0)(0+0+1+0)(1+0+0+1)(0+1+0+0)(1+1+0+0) </li></ul><ul><li> F=(C+D)(A’+B+C)(A+B+D) </li></ul>
  65. 71. Converting Between POS and SOP Using the K-map <ul><li>Ex 4-33) (A’+B’+C+D)(A+B’+C+D)(A+B+C+D’)(A+B+C’+D’) (A’+B+C+D’)(A+B+C’+D) </li></ul><ul><li>Sol) </li></ul>
  66. 73. Five/Six –Variable K-Maps <ul><li>Five Variable K-Map : {A,B,C,D,E} </li></ul>0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 16 17 19 18 20 21 23 22 28 29 31 30 24 25 27 26 00 01 11 10 00 01 11 10 BC DE A=0 A=1
  67. 74. <ul><li>Six Variable K-Map : {A,B,C,D,E,F} </li></ul>0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 16 17 19 18 20 21 23 22 28 29 31 30 24 25 27 26 00 01 11 10 00 01 11 10 CD EF AB 32 33 35 34 36 37 39 38 44 45 47 46 40 41 43 42 48 49 51 50 52 53 55 54 60 61 62 63 56 57 59 58 00 10 01 11
  68. 75. <ul><li>Ex 4-34) </li></ul><ul><li>Sol) A’D’E’+B’C’D’+BCD+ACDE </li></ul>
  69. 76. Programmable Logic: PALs and GALs <ul><li>Basic PAL Operation </li></ul><ul><ul><li>Programmable array of AND gates </li></ul></ul><ul><ul><li>Fixed OR gate </li></ul></ul>
  70. 77. <ul><li>Implementing a Sum-of-Product Expression </li></ul>
  71. 79. <ul><li>Ex 4-35) Show how a PAL is programmed for the following function : X=AB’C+A’BC’+A’B’+AC </li></ul><ul><li>Sol) </li></ul>
  72. 80. PAL Block Diagram
  73. 81. PAL Output Combinational Logic X  0=X X  1=X’
  74. 82. A Specific PAL Figure 4-50 Block diagram of the PAL16L8 .
  75. 83. Basic GAL Operation <ul><li>Reprogrammable AND array </li></ul><ul><li>Electrically Erasable CMOS(E 2 CMOS) technology </li></ul>
  76. 84. Figure 4-52 GAL implementation of a sum-of-products expression.
  77. 85. <ul><li>Ex 4-36) Show how a GAL is programmed for the function: X=A’BC’+A’BC+BC+AB’ </li></ul><ul><li>Sol) </li></ul>
  78. 86. The GAL Block Diagram <ul><li>OLMCs(Output Logic Macrocells) </li></ul><ul><ul><li>OR array and programmable output logic </li></ul></ul><ul><ul><li>Typically m and n >= 8 </li></ul></ul>
  79. 88. GAL20V8 High Performance E2CMOS PLD Generic Array Logic™
  80. 89. Boolean Expressions with VHDL <ul><li>Boolean Algebra in VHDL Programming </li></ul><ul><ul><li>VHDL Optimization </li></ul></ul><ul><li>Ex 4-37) Write a VHDL grogram for the following function: X=(AC+(BC’)’+D)’+((BC)’)’ </li></ul>-- Program X=(AC+(BC’)’+D)’+((BC)’)’ entity alogicft is port(A, B, C, D: in bit; X: out bit); end entity alogicft; architecture expaft of alogicft is begin X<=not((A and C) or not(B and not C) or D) or not(not B and C); end architecture expaft;
  81. 90. -- Program X=(AC+(BC’)’+D)’+((BC)’)’=(A’+C’)(BC’)D’+BC -- =A’BC’D’+BC’D’+BC=(A’+1)BC’D’+BC = BC’D’+BC entity alogicft is port(B, C, D: in bit; X: out bit); end entity alogicft; architecture expaft of alogicft is begin X<= (B and not C and not D) or (B and C); end architecture expaft;
  82. 91. Levels of Abstraction for sequential logic circuits VHDL (1) Behavioral approach : state diagram or truth table (2) Data flow approach : Boolean expression or function (3) Structure approach : logic diagram or schematic describing logic function
  83. 92. Digital System Application : 7-Segment LED Driver Seven-Segment LED driver
  84. 93. A B C D <ul><li>0 1 3 2 </li></ul><ul><li>4 5 7 6 </li></ul><ul><li>13 15 14 </li></ul><ul><li>8 9 11 10 </li></ul>g = m(2,3,4,5,6,8,9) =A+BC’+B’C+CD’ CD AB
  85. 94. Figure 4-59 Karnaugh map minimization of the segment- a logic expression.
  86. 95. Figure 4-60 The minimum logic implementation for segment a of the 7-segment display.
  87. 96. -- Program 7-segment driver entity sevensegdrv is port(A, B, C, D: in bit; a,b,c,d,e,f,g: out bit); end entity sevensegdrv; architecture segment of sevensegdrv is begin a<= B or D or (A and C) or (not A and not C); -- B +D+AC+A’C’ • • • • • • • • • g<= A or B and C’ or not B and C or C and not D; -- A+BC’+B’C+CD’ end architecture segment; VHDL for 7-Segment Driver
  88. 97. Summary <ul><li>Gate symbols </li></ul><ul><li>Duality Principle </li></ul><ul><ul><li>F(A,A  ,  , + , 1,0)  F * (A,A  , + ,  ,0,1) </li></ul></ul><ul><li>DeMorgan’s Theorem </li></ul><ul><ul><li>F  (A,A  ,  , + , 1,0) = F(A  , A, + ,  ,0,1) </li></ul></ul>
  89. 98. The relationship between a single variable X, its complement X  , and the binary constants 0 and 1
  90. 99. <ul><li>Sum-of-Product(SOP) form  Product-of-Sums(POS) form </li></ul><ul><li>Standard(canonical) SOP form  Standard POS form </li></ul><ul><li>Universal gates: NAND, NOR </li></ul><ul><li>Don’t care conditions </li></ul><ul><li>Karnaugh map(3, 4, 5, 6 variables) </li></ul><ul><li>PLDs: PAL, GAL </li></ul><ul><li>VHDL for logic expressions </li></ul>
  91. 100. Boolean Expression Truth Table Logic Diagram VHDL (HDL)
  92. 101. End of Ch. 4

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