THIS DOCUMENT CONTAINS THE DIGITAL ELECTRONICS DESIGN OF 3 BIT MAJORITY CIRCUIT. IN THIS DOCUMENT THERE IS A BRIEF EXPLANATION ABOUT THE CIRCUIT HOW TO DESIGN AND IMPLEMENTATION OF CIRCUIT AND THE THEORETICAL CALCULATIONS,TRUTH TABLES ARE ALSO DONE IN THIS DOCUMENT AND THIS IS USEFUL FOR THE ELECTRONICS STUDENTS

1. A lab-based project
Report on
Design of 3 Bit Majority Circuit
Submitted in the partial fulfillment of the requirements for the award of degree of
BACHELOR OF TECHNOLOGY
IN
ELECTRICAL AND ELECTRON ICS ENGINEERING
By
P.SANJAY KUMAR(18981A0241)
Under the esteemed guidance of
M R .D . BHASKAR A R AO
Associate Professor
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
RAGHU ENGINEERING COLLEGE (autonomous)
(Permanently affiliated to JNTU- Kakinada, Approved by A.I.C.T.E - New Delhi)
Dakamarri, Visakhapatnam
JULY 2020
RAGHU ENGINEERING COLLEGE
Department of Electrical and Electronics Engineering

2. CERTIFICATE
This is to certify that this Digital Electronics Lab based work entitled as “DESIGN OF 3
BIT MAJORITY CIRCUIT ” submitted by P.SANJAY KUMAR (18981A0241) in partial
fulfillment of the requirements for the award of degree of Bachelor of Technology in
Electrical & Electronics Engineering at Raghu Engineering College during academic
year 2019-20.
We also declare that this minor project is our own effort and it has not been submitted to
any another university for award of any degree.
Signature of labincharge Signature of HOD
ACKN OWLED GEM EN T
I take this opportunity to express my sincere gratitude towards my respected
Mr.D.Bhaskara Rao we also grateful towards their support and continuous encouragement

3. ,which were the constant source of inspiration for the completion of the research work
.Furthermore for the great enthusiasm they always shown for our work and also their
careful reading of this report have improved its quality considerably.
We sincerely appreciate their pronounced individualities, humanistic and warm
personal approach which has given us strength to carry out this work on steady and
smooth course. I humbly acknowledge a lifetime gratitude to their contribution.
Our special sincere thanks are due to K. Rahul Verma, Director and Raghu,
Chairman of Raghu Engineering College for their constant source of assurance and
strength to us during the entire period of this work.
Place: Visakhapatnam.
Date:
Contents:
Objective
Introduction
Majority Circuit
SOP
POS
Design of Circuits

4. Conclusion
References
Objective:
To Design a 3 Bit Majority Circuit
3 Bit -Majority Circuit:
A majority gate is a logical gate used in circuit complexity and other
applications of Boolean circuits. A majority gate returns true if and only
if more than 50% of its inputs are true.
Truth Table:

5. Sum Of Products:
The sum-of-products (SOP) form is a method (or form) of simplifying the Boolean
expressions of logic gates. In this SOP form of Boolean function representation, the variables
are operated by AND (product) to form a product term and all these product terms are
summed or added together to get the final function.
The sum-of-products form is also called as Disjunctive Normal Form as the product terms
are together and Disjunction operation is logical OR. Sum-of-products form is also called as
Standard SOP.
Ex: Boolean expression for majority function F = A’BC + AB’C + ABC ‘ + ABC
Truth table:

6. Now write the input variables combination with high output. F = AB + BC + AC
Checking
By Idempotence law, we know that
([ABC + ABC)] + ABC) = (ABC + ABC) = ABC
Now the function F = A’BC + AB’C + ABC’ + ABC
= A’BC + AB’C + ABC’ + ([ABC + ABC)] + ABC)
= (ABC + ABC ‘) + (ABC + AB’C) + (ABC + A’BC)
= AB (C + C ‘) + A (B + B’) C + (A + A’) BC
= AB + BC + AC.
Product Of Sums:
The product of sums form is a method (or form) of simplifying the Boolean expressions of
logic gates. In this POS form, all the variables are ORed, i.e. written as sums to form sum
terms.
All these sum terms are ANDed (multiplied) together to get the product-of-sum form. This
form is exactly opposite to the SOP form. So this can also be said as “Dual of SOP form”.
The product-of-sums form is also called as Conjunctive Normal Form as the sum terms are
ANDed together and Conjunction operation is logical AND. Product-of-sums form is also
called as Standard POS.
Example:
(A+B) * (A + B + C) * (C +D)
(A+B) ̅ * (C + D + E ̅)
POS form can be obtained by
Writing an OR term for each input combination, which produces LOW output.
Writing the input variables if the value is 0, and write the complement of the variable if its
value is 1.
AND the OR terms to obtain the output function.
Ex:

7. Boolean expression for majority function F = (A + B + C) (A + B + C ‘) (A + B’ + C) (A’ +
B + C)
Ex:
Now write the input variables combination with high output. F = AB + BC + AC.
Checking
By Idempotence law, we know that
[(A + B + C) (A + B + C)] (A + B + C) = [(A + B + C)] (A + B + C) = (A + B + C)
Now the function
F = (A + B) (B + C) (A + C)
= (A + B + C) (A + B + C ‘) (A + B’ + C) (A’ + B + C)
= [(A + B + C) (A + B + C)] (A + B + C) (A + B + C ‘) (A + B’ + C) (A’ + B + C)
= [(A + B + C) (A + B + C ‘)] [(A + B + C) (A’ + B + C)] [(A + B + C) (A + B’ + C)]
= [(A + B) + (C * C ‘)] [(B + C) + (A * A’)] [(A + C) + (B * B’)]
= [(A + B) + 0] [(B + C) + 0] [(A + C) + 0] = (A + B) (B + C) (A + C)
Designing of circuits:
SOP EXPRESSION:
From the truth table
WE CAN WRITE SOP FOR HIGH OUTPUTS
SOP is a two level network, 1ST level consist of AND GATE ,2ND level consistof OR
GATE.
Q = A’BC+AB’C+ABC’+ABC
AND WE CAN MINIMISE THE EXPRESSION
BY USING BOOLEAN EXPRESSION
Q = A’BC+AB’C+AB(C’+C)
Q = A’BC+AB’C+AB (1)
Q = A’BC+A(B’C+B)
Q = A’BC+A(B+C)
NAND - NAND REALIZATION: Q = A’BC+A(B+C)

8. From the truth table
WE CAN WRITE POS FOR LOW OUTPUTS
SOP is a two level network, 1ST level consist of OR GATE ,2ND level consist of AND
GATE.
Q = ABC+ABC’+AB’C+A’BC
AND WE CAN MINIMISE THE EXPRESSION
BY USING BOOLEAN EXPRESSION
Q = (A+B) (C+C’)(A+B’+C) ( A’+B+C)
Q=(A+B) [AA’+AB+AC+A’B’+BN’+B’C+A’C+BC+CC]
Q= (A+B) [AB+AC+A’B’+B’C+A’C+BC+1]
Q = (A+B)[A(B+C)+A’(B’+C)+C(B’+B)+1]
Q= (A+B)[(A+A’){B+C+B’+C}+C+1]
Q=(A+B)[(B+B’+C+C’)+(1+C)]
Q=(A+B)[(1)+(1+C)]
Q= (A+B)(1+C)

9. POS:
y = (a+b)(1+c)

10. NOR-NOR Realization:
OBSERVATIONS:
From the above designs , we observed that when the inputs given to the circuit we get
majority of the inputs , which is more then 50% of the input.
Hence the 3 Bit Majority circuit is designed…
y = (a+b) (1+c)