logic

1. Combinational logic
STATIC CMOS GATES
no clock design
Can Be Made pipelined By Inserting Latches
in between
Combinational logic
STATIC CMOS GATES
no clock design
Can Be Made pipelined By Inserting Latches
in between

2. Design Styles
Full Static CMOS or complementary logic

3. NAND NOR

4. XOR/ XNOR
DRAWBACK
complementary signals
are required

5. F = D + A. (B+C)F = D + A. (B+C)

6. static CMOS gate
VTC--Input data dependent

9. Tphl--Delay computation –NAND
state of intermediate nodes matter --worst case

10. Drawback of static cmos
• 2N devices required
• Prop delay inc with increase in fanin
because of inc in Cint, large series chain

11. Uniform transistor sizing
• For the gate, Find equivalent inverter
model
• Find the required transistor w/L
• Hence estimate w/L of each transistor
• For the gate, Find equivalent inverter
model
• Find the required transistor w/L
• Hence estimate w/L of each transistor

13. Influence of fan-in / fanout
on propagation delay

14. Other delay reduction techniques
• Progressive transistor sizing
• Input reordering
• Logic restructuring

16. Reduce power consumption
Reduce switching activity

17. Power consumption due to glitches

18. Power reduction—balanced signal
path for glitch reduction

19. Logic restructuring for lowering
switching activity

20. Power reduction- Input reordering
affects

21. Power reduction- Time multiplexing of
resources—area reduces, activity increases
Very low switching activity Very high switching activity as bus
toggles between 0 and 1

22. Other design styles--Pseudo
NMOS

23. DCVSL

24. Xor/ Xnor
ADVANTAGE---TRANSISTOR SHARING
DCVSL is advantageous for
full adder implementation
Then static CMOS
DCVSL is advantageous for
full adder implementation
Then static CMOS

25. NAND/ AND

27. Adder

29. Other logic design styles
Switch logic