Shift registers can be used for converting serial data to parallel form and for delaying digital signals. An 8-bit serial-in serial-out shift register with a 40 MHz clock can delay a signal by 200 ns as the delay for each clock cycle is 25 ns and there are 8 cycles. Shift-register counters include ring counters where the output of the last flip-flop is fed to the input of the first flip-flop, and Johnson counters where the inverted output of the last flip-flop is connected to the first flip-flop, allowing them to require fewer flip-flops than ring counters for a given count.