Latch Introduction & RS Latch You can watch my lectures at: Digital electronics playlist in my youtube channel: https://www.youtube.com/channel/UC_fItK7wBO6zdWHVPIYV8dQ?view_as=subscriber My Website : https://easyninspire.blogspot.com/

1. Latch Introduction &
RS Latch

2. • Latch
• Flip flop
Memory Elements
Async. Sequential circuits
Sync. Sequential circuits

3. Today's Topic
Combinational Logic Circuits
• Latches

4. Storage Elements
• A storage element in a digital circuit can maintain a binary state as
long as power is delivered to the circuit
• It maintains state until directed by an input signal to switch states.
Bistable circuit:
 A circuit which has two stable states.
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A
B
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X
Y
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5. Storage elements
• That operate with signal levels are referred to as latches
• Those controlled by a clock transition are flip-flops .
• The two types of storage elements are related because latches
are the basic circuits from which all flip-flops are constructed.

6. Latches
• Latches are basic storage elements that operate with signal levels
• Latches are useful for the design of the asynchronous sequential
circuit.
• Latches are level-sensitive/ Level triggered devices.
• Triggering means making a circuit active.
• In level triggering the circuit will become active when the gating /
input is on a particular level.
Types of Latches:
• RS Latch
• D latch

7. RS Latch
Reset - Set Latch
• The SR (or) RS latch is a circuit with two cross-coupled NOR gates or
two cross-coupled NAND gates
• Two inputs labeled S for set and R for reset.
RS latch using NAND gates
RS latch using NOR gates

8. • RS Latch using NOR gates:
• Possible RS combinations are
R S Qp Qp’
0 0
0 1
1 0
1 1
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
NOR truth table
Qp is the Output (Present state)
Qp’ is the compl. of output (Present state)

9.  S=0 , R=1
Qp = 0 Qp’ = 1
• S=0 , R=0
Qp = 0 Qp’ = 1
------------------------------------------
 S=1 , R=0
Qp = 1 Qp’ = 0
• S=0 , R=0
Qp = 1 Qp’ = 0
Used to RESET the o/p
Used to SET the o/p to 1
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
NOR :
It is clear that S=0 , R=0 condition is used as a memory/storage

10.  S=1 , R=1
Qp = 0 Qp’ = 0
This is a wrong condition.
• S=0 , R=0
Qp = 1 Qp’ = 0
• S=0 , R=0
Qp = 0 Qp’ = 1
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
NOR :
For the same condition S=0 , R=0 we have diff. outputs. (This is not good)
S=1 , R=1 is NOT USED

11. • Truth table for SR (or) RS latch using NOR gates
S R Qp Qp’ State
0 0 Qp Qp’ Memory / No change state
0 1 0 1 RESET
1 0 1 0 SET
1 1 - - Invalid/ Forbidden state

12. RS Latch using NAND gates:
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
NAND truth table
S R Qp State
0 0 Qp Invalid/ Forbidden state
0 1 1 SET
1 0 0 RESET
1 1 - Memory / No change state

13. In Next Class
• D Lacth

14. • A