This document discusses latches and flip-flops. It explains that gates perform logic operations while flip-flops can store binary values. There are two types of sequential logic circuits: combinational using gates and sequential using flip-flops like the SR, D, JK, and T flip-flops. Flip-flops change state based on clock pulses in synchronous circuits or independent of clocks in asynchronous circuits.

1. Latches and flip-flops

2. Gates and flip-flops
Gates are the building block of the logic
circuits. Their primary function is to perform
decision making operations.
Flip-flops are the building blocks of the digital
circuits. Their primary function is to store the
binary bits.

3. LOGIC CIRCUITS
Logic circuits are classified into two groups:
Combinational logic circuits
Basic building
blocks include:
Sequential logic circuits
Basic building blocks
include FLIP-FLOPS:
Logic gates make decisions
Flip Flops have memory

4. Synchronous and Asynchronous Sequential Logic:-
Synchronous
– the timing of all state transitions is controlled
by a common clock
– changes in all variables occur simultaneously
Asynchronous
– state transitions occur independently of any
clock and normally dependent on the timing of
transitions in the input variables
– changes in more than one output do not
necessarily occur simultaneously

5. clock period
Clock:-
A clock is a special device that whose output
continuously alternates between 0 and 1.
The time it takes the clock to change from 1 to
0 and back to 1 is called the clock period, or
clock cycle time.
The clock frequency is the inverse of the clock
period. The unit of measurement for
frequency is the hertz.
Clocks are often used to synchronize circuits.

6. Triggering
Sequential circuits are dependant on clock pulses
applies to their inputs.
The result of flip-flop responding to a clock input is
called clock pulse triggering, of which there are
four types. Each type responds to a clock pulse in
one of four ways :-
1. High level triggering
2. Low level triggering
3. Positive edge triggering
4. Negative edge triggering

11. Latch
Latch are the bi-stable devices which responds
to the change of input logic levels as they occur.
Latch Inputs
Q Complementory output
Q
Q is the primary output
Q is its complemetory
It is said to be in SET state if output Q is high
It is said to be in RESET state if output Q is low

12. R-S Latch using NOR gate
The two inputs, S and R
denote ``set'' and
``reset'' respectively.
The latch has memory,
and the present output
is dependent on the
state of the latch
R S Q Q comment
0 0 Qn Qn Previous
state
0 1 1 0 SET state
1 0 0 1 RESET state
1 1 Not
defined
Not
defined
Not
defined

13. R-S Latch using NAND gate
R S Q Q comment
1 1 Qn Qn Previous
state
0 1 1 0 SET state
1 0 0 1 RESET
state
0 0 Not
defined
Not
defined
Not
defined
R
Q
S Q’

14. Level-Sensitive/ Gated RS-Latch
• “Q” only changes when CLK is high (i.e. level-sensitive)
• When CLK is high, behavior same as RS latch
E S R
0 X X No change
1 0 0
1 0 1
1 1 0
1 1 1
Q
No change
0
1
Undefined
Race condition

15. Level-Sensitive D-Latch
Make level-sensitive D-latch
from level-sensitive RS-latch
by connecting S = D and R =
not D
Due to NOT gate ,S and R will
always be the complements
of each other. hence S=R=0
or S=R=1, these inputs will
never appear. This will avoid
the problems associated
with SR=00 and SR=11
conditions
D
E
Q
Q
Normal
Comple-mentary
FF
E D Q Q comments
0 X Q Q No change
1 0 0 1 Reset
1 1 1 0 Set

16. CLOCKED R-S FLIP-FLOP
Set
Reset
S
R
Q
Q
FF
ASYNCHRONOUS
Outputs of logic circuit can
change state anytime one
or more input changes
Set
Reset
S
R
Q
Q
FF
Clock
CLK
SYNCHRONOUS
Clock signal determines
exact time at which any
output can change state

17. Flip-flops
A flip-flop is a bi-stable device, with inputs,
that remains in a given state as long as power
is applied and until input signals are applied to
cause its output to change.
 There are four basic different types of flip-flops:
 SR
 D
 JK
 T

18. CLOCKED R-S FLIP-FLOP
Symbols:
Truth Table:
Set
Reset
S
R
Q
Q
Normal
Comple-mentary
FF
Clock
CLK
Clk S R Qn Qn
0 0 No change
0 1 0 1
1 0 1 0
1 1 Race Race

19. POSITIVE EDGE TRIGGERED
R-S FLIP-FLOP
TIMING DIAGRAMS
CLK R S Q
0
0
0 NO CHG
1
1 0
1 1
SET
RESET
ILLEGAL

20. NEGATIVE EDGE TRIGGERED
R-S FLIP-FLOP
CLK R S Q
0
0
0 NO CHG
1
1 0
1 1
SET
RESET
ILLEGAL

22. D Flip-Flop

23. J-k latch
J
K
Q
Q
J-k
latch
E
E S R Qn Qn
1 0 0 No change
1 0 1 0 1
1 1 0 1 0
1 1 1 Qn Qn Toggle
Race around
condition

24. Race around condition
This condition occur when j=k=1 i.e when the
latch is in toggle mode.
This can be avoided by
Using edge triggering J-k flip-flop
Using master slave flip-flop

25. J-K flip-flop
Clk J k Qn Qn
0 0 No change
0 1 0 1
1 0 1 0
1 1 Qn Qn Toggle

26. Master slave flip-flop

27. Master slave flip-flop
Clk j k Qn Qn
0 0 No change
0 1 0 1
1 0 1 0
1 1 Qn Qn Toggle

28. T flip flop
clk T Q Q comments
0 Q Q No change
1 Q Q toggle

29. Excitation table
SR flip-flop:-
Excitation table:-
Clk S R Qn Qn
0 0 No change
0 1 0 1
1 0 1 0
1 1 Race Race
Present state of
Q o/p
Next state of Q
o/p
Sn Input Rn input
0 0 0 ×
0 1 1 0
1 0 0 1
1 1 × 0

30. JK flip-flop:-
Excitation table:-
Present state of
Q o/p
Clk J k Qn Qn
0 0 No change
0 1 0 1
1 0 1 0
1 1 Qn Qn
Next state of Q
o/p
Jn Input Kn input
0 0 0 ×
0 1 1 ×
1 0 × 1
1 1 × 0

31. D flip-flop:-
Excitation table:-
Present state of
Q o/p
Clk D Q
0 0
1 1
Next state of Q
o/p
Dn Input
0 0 0
0 1 1
1 0 0
1 1 1

32. T flip-flop:-
Excitation table:-
Present state of
Q o/p
Clk T Q
0 No change
1 toggle
Next state of Q
o/p
Tn Input
0 0 0
0 1 1
1 0 1
1 1 0