Synchronous Sequential Circuits Guide

UNIT III
SYNCHRONOUS SEQUENTIAL CIRCUITS
• Sequential Circuits
• Storage Elements: Latches , Flip-Flops
• Analysis of Clocked Sequential Circuits -State Reduction
and Assignment
• Design Procedure
• Registers and Counters
• HDL Models of Sequential Circuits.

Introduction
• Sequential or Finite State Machine (FSM)
Memory elements are connected to the
combinational circuit as a feedback path.
• The information stored in the memory
elements at any given time defines the
present state of the sequential circuit.
• The present state and external inputs
determine the outputs and the next state of
the sequential circuit.
• The memory element used in sequential
circuits is a flip-flop which is capable of
storing 1-bit binary information.
Next state
Present state

Difference between Combinational and Sequential logic circuits
Combinational Circuits Sequential Circuits
Outputs depend only on present
inputs.
Outputs depend on both present inputs
and present state.
Feedback path is not present. Feedback path is present.
Memory elements are not required. Memory elements are required.
Clock signal is not required. Clock signal is required.
Easy to design. Difficult to design.

Clock
• A clock signal is a particular type of signal that oscillates between a high and a
low state and is utilized to co-ordinate actions of circuits.
• It is produced by clock generator.
• The most common clock signal is in the form of a square wave with a 50%
duty cycle, usually with a fixed, constant frequency.
• Circuits using a clock signal for synchronization may become active at either
the rising edge, falling edge or in the case of double data rate, both in the
rising and in the falling edges of the clock cycle.
• The time required to complete one cycle is called ‘clock period’ or ‘clock
cycle’.

One-Bit Memory Cell
• The outputs Q and 𝑄 are always complementary.
• The circuit has two stable states. The state correspond to Q=1 is referred to as 1 state or Set
state and state corresponds to Q=0 is referred to as 0 state or reset state.
• If the circuit is in the set (1) state, it will remain in the set state and if the circuit is in the
reset (0) state, it will remain in the reset state. This property of the circuit shows that it can
store 1-bit of digital information. Therefore, the circuit is called a 1-bit memory cell.
• The 1-bit information stored in the circuit is locked or latched in the circuit. Therefore, this
circuit is also referred to as a latch.

Latches:
SR Latch/RS Latch:
Case 1: S=R=0 (No change in the state)
(a)S=R=0,Q=0Q=0
(b)S=R=0,Q=1Q=1
Case 2: S=1 & R=0 (Set state)
(a)S=1 & R=0,Q=0Q=1
(b) S=1 & R=0,Q=1Q=1
Case 3: S=0 & R=1 (Reset state)
(a)S=0 & R=1,Q=0Q=0
(b) S=0 & R=1,Q=1Q=0
Case 4: S=1 & R=1
When S=R=1,both the outputs Q and 𝑄 try to become 1 which is not allowed and
therefore, this input condition is prohibited.

Gated SR Latch
EN S R 𝑸𝒏 𝑸𝒏+𝟏 State
1 0 0 0 0
No Change (NC)
1 0 0 1 1
1 0 1 0 0
Reset
1 0 1 1 0
1 1 0 0 1
Set
1 1 0 1 1
1 1 1 0 X
Indeterminate
1 1 1 1 X
0 X X 0 0 No Change (NC)
0 X X 1 1

Gated D Latch
• For SR latch, when both inputs are same the output either does not change or it is invalid.
• In many practical applications, these input conditions are not required.
• These input conditions can be avoided by making them complement of each other.
• This modified SR latch is known as D latch.
EN D 𝑸𝒏 𝑸𝒏+𝟏 State
1 0 X 0 Reset
1 1 X 1 Set
0 X X 1 𝑸𝒏

Flip-Flops
Level and Edge Triggering:
Level Triggering:
In the level triggering, the output state is allowed
to change according to input(s) when active level
(either positive or negative) is maintained at the
enable input.
There are two types of level triggered latches:
Positive level triggered: The output of flip-flop
responds to the input changes only when its enable
input is 1 (HIGH).
Negative level triggered: The output of flip-flop
responds to the input changes only when its enable
input is 0 (LOW).

Edge Triggering:
In the edge triggering, the output responds
to the changes in the input only at the
positive or negative edge of the clock pulse
at the clock input.
There are two types of edge triggering.
Positive edge triggering:
Here, the output responds to the changes in
the input only at the positive edge of the
clock pulse at the clock input.
Negative edge triggering:
Here, the output responds to the changes in
the input only at the negative edge of the
clock pulse at the clock input.

SR Flipflop:
Positive edge triggered SR Flipflop:
• The circuit is similar to SR latch except enable signal is replaced by the
clock pulse (CP) followed by the positive edge detector circuit.

CP S R 𝑸𝒏 𝑸𝒏+𝟏 State
0 0 0 0
No Change (NC)
0 0 1 1
0 1 0 0
Reset
0 1 1 0
1 0 0 1
Set
1 0 1 1
1 1 0 X
Indeterminate
1 1 1 X
0 X X 1 1
𝑸𝒏+𝟏 = 𝑺 + 𝑹𝑸𝒏
Logic Symbol
Truth Table for Positive edge triggered clocked SR Flip-flop
Input and Output waveforms
Characteristic Equation

Negative edge triggered SR Flipflop:
CP S R 𝑸𝒏 𝑸𝒏+𝟏 State
0 0 0 0
No Change (NC)
0 0 1 1
0 1 0 0
Reset
0 1 1 0
1 0 0 1
Set
1 0 1 1
1 1 0 X
Indeterminate
1 1 1 X
0 X X 1 1
Truth Table for Negative edge triggered clocked SR Flip-flop
Logic Symbol

Realize SR flip-flop using NOR gates.

CP D 𝑸𝒏 𝑸𝒏+𝟏
0 0 0
0 1 0
1 0 1
1 1 1
0 X 0 0
0 X 1 1
Truth Table
𝑸𝒏+𝟏 = 𝑫
Logic Symbol
Toggling

Negative Edge Triggered D Flip-Flop
CP D 𝑸𝒏 𝑸𝒏+𝟏
0 0 0
0 1 0
1 0 1
1 1 1
0 X 0 0
0 X 1 1
Truth Table
Logic Symbol

JK Flip-Flop
• The uncertainty in the state of an SR flip-flop when S=R=1
can be eliminated by converting it into a JK flip-flop.
Case 1: J=K=0Output does not change.
Case 2: J=1 & K=0Q=1 i.e., Set State.
Case 3: J=1=0 & K=1Q=0 i.e., Reset State
Case 4: J=1 & K=1toggles the flip-flop output.

J K 𝑸𝒏 𝑸𝒏+𝟏 State
0 0 0 0
No Change (NC)
0 0 1 1
0 1 0 0
Reset
0 1 1 0
1 0 0 1
Set
1 0 1 1
1 1 0 1
Toggle
1 1 1 0
J K 𝑸𝒏+𝟏
0 0 𝑸𝒏
0 1 0
1 0 1
1 1 𝑸𝒏
𝑸𝒏+𝟏 = 𝑱𝑸𝒏 + 𝑲𝑸𝒏
Logic Symbol
Truth Table JK Flip-Flop

Race-around Condition
• In JK flip flop, when J=K=1 , the output toggles (output changes either from 0 to 1 or
from 1 to 0).
• Consider that initially Q=0 and J=K=1. After a time interval ∆t equal to the propagation
delay through two NAND gates in series, the output will change to Q=1 and after another
time interval of ∆t the output will go back to Q=0. This toggling will continue until the
flipflop is enabled and J=K=1. At the end of clock pulse the flip flop is disabled and the
value of Q is uncertain. This condition is referred to as the race-around condition.

Master-Slave SR Flip Flop
• A master-slave flip-flop is constructed from two flip-flops.
• One circuit saves as a master and the other as a slave, and the overall circuit is
referred to as master-slave flip-flop.
• The clock pulse of master slave flip-flop is not edge triggered.

T Flip-Flop
• T flip-flop is also known as “Toggle flip-flop”.
• The T flip-flop is a modification of the JK flip-flop, obtained by connecting both inputs J
and K together.
T 𝑸𝒏 𝑸𝒏+𝟏
0 0 0
0 1 1
1 0 1
1 1 0
T 𝑸𝒏+𝟏
0 𝑸𝒏
1 𝑸𝒏
𝑸𝒏+𝟏 = 𝑻𝑸𝒏 + 𝑻𝑸𝒏

State Transition diagrams of flip-flops

Flip-Flop Excitation Table
SR Flip-Flop:
S R 𝑸𝒏+𝟏
0 0 𝑄𝑛
0 1 0
1 0 1
1 1 *
𝑄𝑛 𝑄𝑛+1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
S R 𝑸𝒏 𝑸𝒏+𝟏
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X
Truth Table of SR Flip-flop
Excitation of SR Flip-flop

JK flip-flop
J K 𝑸𝒏+𝟏
0 0 𝑸𝒏
0 1 0
1 0 1
1 1 𝑸𝒏
𝑸𝒏 𝑸𝒏+𝟏 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
J K 𝑸𝒏 𝑸𝒏+𝟏
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Truth Table of JK Flip-flop
Excitation of JK Flip-flop
𝑄𝑛 𝑄𝑛+1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0

D 𝑸𝒏 𝑸𝒏+𝟏
0 0 0
0 1 0
1 0 1
1 1 1
𝑸𝒏 𝑸𝒏+𝟏 D
0 0 0
0 1 1
1 0 0
1 1 1
T 𝑸𝒏 𝑸𝒏+𝟏
0 0 0
0 1 1
1 0 1
1 1 0
𝑸𝒏 𝑸𝒏+𝟏 T
0 0 0
0 1 1
1 0 1
1 1 0
Truth Table of D Flip-flop Excitation of D Flip-flop
Truth Table of T Flip-flop Excitation of T Flip-flop

Realization of one flip-flop using other flip-flop
1. Conversion of SR flip-flop to D flip-flop:
Step 1: Excitation table
Step 3: Logic Diagram
Step 2: K-map simplification
Input
Present
State
Next State Flip-flop inputs
D 𝑸𝒏 𝑸𝒏+𝟏 S R
0 0 0 0 X
0 1 0 0 1
1 0 1 1 0
1 1 1 X 0
𝑸𝒏
D 0 1
0 0 0
1 1 X
S=D
𝑸𝒏
D 0 1
0 X 1
1 0 0
R=𝑫

2. Convert SR Flip-Flop to JK Flip-Flop
Step 1: Excitation table Step 2: K-map simplification
Inputs
Present
state
Next
state
Flip-Flop inputs
J K 𝑸𝒏 𝑸𝒏+𝟏 S R
0 0 0 0 0 X
0 0 1 1 X 0
0 1 0 0 0 X
0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 1 X 0
1 1 0 1 1 0
1 1 1 0 0 1
𝑺 = 𝑱𝑸𝒏
𝑹 = 𝑲𝑸𝒏

D Flip-Flop to SR Flip-Flop
Step 1: Excitation table Step 2: K-map simplification
Inputs
Present
state
Next
state
Flip-Flop
inputs
S R 𝑸𝒏 𝑸𝒏+𝟏 D
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 0
1 0 0 1 1
1 0 1 1 1
1 1 0 X X
1 1 1 X X
D=𝑹𝑸𝒏 + 𝑺

Analysis & Design of Clocked Sequential Circuits
• Sequential circuits are further classified depending on the timing of their signals: Synchronous
sequential circuits and asynchronous sequential circuits.
• In synchronous sequential circuits, signals can affect the memory elements only at discrete instants
of time.
• In asynchronous sequential circuits change in input signals can affect memory element at any
instant of time.
Synchronous sequential circuits Asynchronous sequential circuits
Memory elements are clocked flip flops
Memory elements are either unclocked flip flops or
time delay elements.
The change in input signals can affect memory
element upon activation of clock signal.
The change in input signals can affect memory
element at any instant of time.
Maximum operating speed of clock depends on time
delays involved.
It operates faster than synchronous circuits.
Easier to design More difficult to design

Clocked Sequential Circuits
• In synchronous or clocked sequential circuits, clocked flip-flops are used as
memory elements, which change their individual states in synchronism with the
periodic clock signal.
• Therefore, the change in states of flip-flops and change in state of the entire circuit
occurs at the transition of the clock signal.
• The states of the output of the flip-flop in the sequential circuit gives the state of
the sequential circuit.
• Present State: The status of all state variables, at some time t, before the next
clock edge, represents condition called present state.
• Next State: The status of all state variables, at some time, t+1, represents a
condition called next state.
• The synchronous or clocked sequential circuits are represented by two models.
Moore model: The output depends only on the present state of the flip-flops.
Mealy model: The output depends on both the present state of the flip-flops and on the
input(s).

Moore Model
• When the output of the sequential circuit depends only on the present
state of the flip-flop, the sequential circuit is referred to as Moore
Model.
Example of Moore model

Moore circuit model with an output decoder

Mealy Model
• When the output of the sequential circuit depends on both the present
state of the flip-flop(s) and on the input(s), the sequential circuit is
referred to as Mealy Model.
Example of Mealy model

Difference between Moore and Mealy Circuit
Models
Moore Model Mealy model
Its output is a function of present state only.
Its output is a function of present state as well
as present input.
Input changes does not affect the output.
Input changes may affect the output of the
circuit.
Moore model requires more number of states
for implementing same function.
It requires less number of states for
implementing same function.

Representation of Sequential Circuits
State Diagram:
For Mealy circuit:
State diagram is a pictorial representation of a behaviour
of a sequential circuit.
The state is represented by the circle and the transition
between states is indicated by directed lines connecting
the circles.
A directed line connecting a circle with itself indicates
that next state is same as present state.
The state variable inside each circle identifies the state
represented by the circle.
The directed lines are labelled with two binary numbers
separated by a symbol ‘/’. The input value that causes the
state transition is labelled first and the output value
during the present state is labelled after the symbol ‘/’.

For Moore circuit:
• In case of Moore circuit, the directed lines are
labelled with only one binary number
representing the state of the input that causes
the state transition.
• The output state is indicated within the circle,
below the present state because output state
depends only on present state and not on the
input.

State Table
• Representation of state machine using
relationship between input(s), present
state, next state and the output(s) in
tabular form is known as state table.
• The present state designates the state of
flip-flops before the occurrence of a
clock pulse.
• The next state is state of the flip-flop
after the application of a clock pulse,
and the output section gives the values
of the output variables during the present
state.
• Both the next state and output sections
have two columns representing two
possible input conditions: X=0 and X=1.
• In case of Moore circuit the output
section has only one column since
output does not depend on input.
Present
State
Next State Output
X=0 X=1 X=0 X=1
AB AB AB Y Y
a a c 0 0
b b a 0 0
c d c 0 1
d b d 0 0
Present
State
Next State Output
X=0 X=1
Y
AB AB AB
a a c 0
b b a 0
c d c 1

Transition Table
• A transition table takes the state table one step further. The state diagram and state
table represent state using symbols or names.
• In the transition table specific state variable values are assigned to each state.
• Assignment of values to state variables is called State assignment.
• Like state table transition table also represents relationship between input, output
and flip-flop states.
Present
State
Next State Output
X=0 X=1 X=0 X=1
A B AB AB Y Y
0 0 00 10 0 0
0 1 11 00 0 0
1 0 10 01 0 1
1 1 00 10 0 0

Analysis of Clocked Sequential Circuits
• Determine the flip-flop input equations and the output equations from the
sequential circuit.
• Derive the transition equation.
• Derive the state table
(a) plot the next-state map for flip-flop
(b) plot the transition table
(c)Draw the state table
• Draw the state diagram

A sequential circuit with 2 D-flip-flops A and B and input X and output Y is specified by the following next
state and output equations. A(t+1)=AX+BX; B(t+1)=A′X ; Y=(A+B)X′
i)Draw the logic diagram of the circuit.
ii) Derive the state table.
iii) Derive the state diagram.
Solution:
(i) Logic Diagram

(ii) State Table
Step 1: Plot the next-state map for each flip-flop
X
AB
0 1
00 0 0
01 0 1
10 0 1
11 0 1
For 𝑨+ = 𝑨𝑿 + 𝑩𝑿
X
AB
0 1
00 0 1
01 0 1
10 0 0
11 0 0
For 𝑩+
= 𝑨𝑿
X
AB
0 1
00 0 0
01 1 0
10 1 0
11 1 0
For 𝒀 = (𝑨 + 𝑩)𝑿

Step 2:Plot the transition table
(iii) State diagram
Step 3: Draw the state table
Assume: a=00, b=01, c=10 and d=11
Present
State
Next state Output Y
A B
X=0 X=1
X=0 X=1
𝑨+
𝑩+
𝑨+
𝑩+
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0
Present
state
Next state Output Y
X=0 X=1 X=0 X=1
a a b 0 0
b a d 1 0
c a c 1 0
d a c 1 0

Construct the transition table, state table and state diagram for the Moore sequential circuit given.
Solution:
1. Determine the flip-flop input equations and the output equations from the sequential
circuit.
𝑭 = 𝑨⨁𝑩
𝑱𝑨 = 𝑩 𝑱𝑩 = 𝑿
𝑲𝑨 = 𝑿𝑩 𝑲𝑩 = 𝑿⨁𝑨

2. Derive the transition equations.
The transition equations for JK flip-flops can be derived from the characteristic equation of JK flip-flop as follows:
We know that for JK flip-flop: 𝑄+
= 𝐽𝑄 + 𝐾𝑄
𝐴+
= 𝑄𝐴
+
= 𝐽𝐴𝑄𝐴 + 𝐾𝐴𝑄𝐴 = 𝐵𝑄𝐴 + 𝑋𝐵𝑄𝐴 = 𝐵𝑄𝐴 + 𝑋 + 𝐵 𝑄𝐴 = B𝐴 + 𝑋 + 𝐵 A
𝐵+
= 𝑄𝐵
+
= 𝐽𝐵𝑄𝐵 + 𝐾𝐵𝑄𝐵 = 𝑋𝑄𝐵 + 𝑋⨁𝐴𝑄𝐵 = 𝑋𝐵 + 𝑋⨁𝐴𝐵
3. Plot the next-state maps for each flip-flop
X
AB
0 1
00 0 0
01 1 1
10 1 1
11 0 1
For 𝑨+ = B𝐴 + 𝑋 + 𝐵 A
X
AB
0 1
00 1 0
01 1 0
10 1 0
11 0 1
For 𝑩+ = 𝑋𝐵 + 𝑋⨁𝐴𝐵

4. Plot the transition table
6. State diagram
5. Draw the state table
Assume: a=00, b=01, c=10 and d=11
Present
State
Next state
Output
A B
X=0 X=1
𝑨+
𝑩+
𝑨+
𝑩+
𝑭 = 𝑨⨁𝑩
0 0 0 1 0 0 0
0 1 1 1 1 0 1
1 0 1 1 1 0 1
1 1 0 0 1 1 0
Prese
nt
state
Next state
Output
X=0 X=1
a b a 0
b d c 1
c d c 1
d a d 0

Design of Clocked Sequential Circuits
• First obtain the state table from the given circuit information such as a state
diagram, a timing diagram or other pertinent information.
• The number of states may be reduced by state reduction technique if the
sequential circuit can be categorized by input-output relationships
independent of the number of states.
• Assign binary values to each state in the state table, i.e., state assignment.
• Determine the number of flip-flops needed and assign a letter symbol to
each.
• Choose the type of flip-flop to be used.
• From the state table, derive the circuit excitation and output tables.
• Using the K-map or any other simplification method, derive the circuit
output functions and the flip-flop input functions.
• Draw the logic diagram.

State reduction
• The state reduction technique basically avoids the introduction of redundant
states.
• The reduction in redundant states reduce the number of required flip-flops and
logic gates, reducing the cost of the final circuit.
• The two states are said to be redundant or equivalent, if every possible set of
inputs generate exactly same output and same next state.
• When two states are equivalent, one of them can be removed without altering
the input-output relationship.

Step 1: Determine the state table for given state diagram
Present
State
Next State Output
X=0 X=1 X=0 X=1
a b c 0 0
b d e 1 0
c c d 0 1
d a d 0 0
e c d 0 1
Step 2: Find equivalent states / Reduced State table
Present
State
Next State Output
X=0 X=1 X=0 X=1
a b c 0 0
b d c 1 0
c c d 0 1
d a d 0 0
Step 3: Reduced State diagram

• Reduce the number of states in the following state diagram. Tabulate the reduced state table and draw
the reduced state diagram.
Present
state
Next State Output
X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1
Equivalent states
Present
state
Next State Output
X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f e f 0 1
Equivalent states
Present
state
Next State Output
X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
Reduced state
diagram

1. Design a sequential circuit using RS flip flops for the state table given below using
minimum number of flip flops.
Present
state
Next state Output Z
X=0 X=1 X=0 X=1
A A B 0 0
B C D 0 0
C A D 0 0
D E F 0 1
E A F 0 1
F G F 0 1
G A F 0 1
Present
state
Next state,
Output Z
X=0 X=1
A A,0 B,0
B C,0 D,0
C A,0 D,0
D E,0 F,1
E A,0 F,1
F G,0 F,1
G A,0 F,1
Equivalent states

Present
state
Next state,
Output Z
X=0 X=1
A A,0 B,0
B C,0 D,0
C A,0 D,0
D E,0 F,1
E A,0 F,1
F E,0 F,1
Equivalent states
Present
state
Next state,
Output Z
X=0 X=1
A A,0 B,0
B C,0 D,0
C A,0 D,0
D E,0 D,1
E A,0 D,1
Minimized State Table
Excitation Table
Present
state
Next state Flip-flop inputs Output
X=0 X=1 X=0 X=1
X=0 X=1
A B C A+ B+ C+ A+ B+ C+ 𝑅𝐴 𝑆𝐴 𝑅𝐵 𝑆𝐵 𝑅𝐶 𝑆𝐶 𝑅𝐴 𝑆𝐴 𝑅𝐵 𝑆𝐵 𝑅𝐶 𝑆𝐶
A 0 0 0 0 0 0 0 0 1 X 0 X 0 X 0 X 0 X 0 0 1 0 0
B 0 0 1 0 1 0 0 1 1 X 0 0 1 1 0 X 0 0 1 0 X 0 0
C 0 1 0 0 0 0 0 1 1 X 0 1 0 X 0 X 0 0 X 0 1 0 0
D 0 1 1 1 0 0 0 1 1 0 1 1 0 1 0 X 0 0 X 0 X 0 1
E 1 0 0 0 0 0 0 1 1 1 0 X 0 X 0 1 0 0 1 0 1 0 1
Assignment states
A=000
B=001
C=010
D=011
E=100

K-map Simplification:
𝑅𝐴 = 𝐵
𝑆𝐴 = 𝐴𝐶𝑋
𝑅𝐵 = 𝑋𝐵
𝑆𝐵 = 𝑋𝐴 + 𝐵𝐶
𝑅𝐶 = 𝑋
𝑆𝐶 = 𝑋

1. Design a synchronous sequential circuit using JK for the given state diagram.
Solution:
Step 1: Since N=4. Number of flip-flops needed=2
Step 2: Flip-flops to be used: JK
Step 3: Determine the excitation table.
Present State Input Next State Flip-Flop Inputs
A B X A+ B+ 𝑱𝑨 𝑲𝑨 𝑱𝑩 𝑲𝑩
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X
0 1 0 1 0 1 X X 1
0 1 1 0 1 0 X X 0
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1

Step 4: K-map Simplification
𝐽𝐴 = 𝐵𝑋
𝐾𝐴 = 𝐵𝑋
𝐽𝐵 = 𝑋
𝐾𝐵 = 𝐴𝑋 + 𝐴𝑋

Design with unused states
• Design the sequential circuit for the state diagram shown using JK flip-flops

Step 1: Derive excitation table
Present State Input Next State Flip-flop inputs Output
A B C X A+ B+ C+ 𝐽𝐴 𝐾𝐴 𝐽𝐵 𝐾𝐵 𝐽𝐶 𝐾𝐶 Y
0 0 1 0 0 1 0 0 X 1 X X 1 1
0 0 1 1 0 1 1 0 X 1 X X 0 1
0 1 0 0 0 0 1 0 X X 1 1 X 0
0 1 0 1 0 1 0 0 X X 0 0 X 1
0 1 1 0 1 0 0 1 X X 1 X 1 1
0 1 1 1 1 1 0 1 X X 0 X 1 0
1 0 0 0 1 1 0 X 0 1 X 0 X 0
1 0 0 1 0 0 1 X 1 0 X 1 X 1
1 1 0 0 1 1 0 X 0 X 0 0 X 1
1 1 0 1 0 1 0 X 1 X 0 0 X 0

Step 2: K-map simplification
𝐽𝐴 = 𝐵𝐶
𝐾𝐴 = 𝑋 + 𝐶
𝐽𝐵 = 𝑋
𝐾𝐵 = 𝐴𝑋
𝐽𝐶 = 𝐴𝑋 + 𝐵𝑋
𝐾𝐶 = 𝐵 + 𝑋
Y=AB 𝑋+A 𝐶𝑋 + 𝐵𝑋 + 𝐶𝑋
Step 3: Logic diagram

Registers
• A group of flip-flops can be used to store a word, which is called register.
• A flip-flop can store 1-bit information. So an n-bit register has a group of a flip-flops
and is capable of storing any binary information / number containing n-bits.
Buffer Register:
In this register, four D flip-flops are used. So it can store 4-bit binary information.
Thus the number of flip-flop stages in a register determines its total storage capacity.

Controlled Buffer Register
• We can control input and output of the register by connecting tri-state devices at the
input and output sides of register, so this register is called “controlled buffer register”.
• Hence, tri-state switches are used to control the operation.
• 𝐿𝑂𝐴𝐷/𝑊𝑅 store data in the register
• 𝑅𝐷 read data at the output
• Controlled buffer registers are commonly used for temporary storage of data within a
digital system.

Shift Registers
• The binary information in a register can be moved from stage to stage within the register or into or out of the
register upon application of clock pulses.
• This type of bit movement or shifting is essential for certain arithmetic and logic operations used in
microprocessors.
• This gives rise to group of registers called shift registers.

Types of Shift Registers
• Serial In Serial Out (SISO) shift register:
• Shift Left mode:

• Serial In Parallel Out (SIPO) Shift Register:
The data bits are entered serially into the register but the output is taken in parallel.
• Parallel In Serial Out (PISO) Shift Register:
In this type, the bits are entered in parallel i.e simultaneously into their respective stages on parallel lines.
SHIFT/LOAD is the control input which allows shifting or loading data operation of the register.

• Parallel In Parallel Out Shift Register (PIPO):
• In “parallel in parallel out register”, there is simultaneous entry of all
data bits and bits appear on parallel outputs simultaneously.

Bidirectional Shift Register
This type of register allows shifting of data either to the left or to the right side. It
can be implemented by using logic gate circuitry that enables the transfer of data
from one stage to the next stage to the right or to the left, depending on the level of a
control line.
𝑅𝐼𝐺𝐻𝑇/𝐿𝐸𝐹𝑇 is the control input signal which allows data shifting either towards
right or towards left.

Bidirectional Shift Register with Parallel Load:
When parallel load capability is added to the shift register, the data entered in parallel can
be taken out in serial fashion by shifting the data stored in the register. Such a register is
called bidirectional shift register with parallel load.
𝑆𝐿1 𝑆𝐿0 Selected Source
0 0 Parallel input
0 1 Output of right adjacent FF
1 0 Output of left adjacent FF

Shift Register using JK Flip-Flops:

Universal Shift Register
• A register capable of shifting in one
direction only is a unidirectional shift
register.
• A register capable of shifting in both
directions is a bidirectional shift register.
• If the register has both shifts (right shift
and left shift) parallel load capabilities, it is
referred to as universal shift register.
• It consists of four flip-flops and four
multiplexers.
Mode Control Register
operation
𝑺𝟏 𝑺𝟎
0 0 No change
0 1 Shift right
1 0 Shift left
1 1
Parallel
load

Applications of Shift Registers
Delay line:
A Serial-In-Serial-Out (SISO) shift register can be used to introduce time delay Δt in
digital signals. The time delay can be given as
Δt=Nx(1/𝑓𝑐)
Serial-to-Parallel Converter:
A Serial-In-Parallel-Out (SIPO) shift register can be used to convert data in the
serial form to the parallel form.
Parallel-to-Serial Converter:
A Parallel-In-Serial-Out (PISO) shift register can be used to convert data in the
parallel form to the serial form.

Ring Counters
• The Q output of each stage is connected to the D input of the next stage and the output
of last stage is fed back to the input of first stage.
• The ring counter can be used for counting the number of pulses.
Clock
pulse
𝑄𝐴 𝑄𝐵 𝑄𝐶 𝑄𝐷
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1
4 1 0 0 0

Johnson or Twisting Ring or Switch Tail Counter
• In a Johnson counter, the Q output of each stage of flip-flop is connected to the D input of
the next stage.
• The single exception is that the complement output of the last flip-flop is connected back to
the D-input of the first flip-flop.
• Johnson counter can be implemented with SR or JK flip-flops as well.
Clock
Pulse
𝑸𝑨 𝑸𝑩 𝑸𝑪 𝑸𝑫
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1

Counters
• A counter is a register capable of counting the number of clock pulses arriving at its clock input.
• Count represents the number of clock pulses arrived.
• In case of down counter, on arrival of each clock pulse, it is decremented by one.
• External clock is applied to the clock input of the counter.
• Th counter can be positive edge triggered or negative edge triggered.
• The n-bit binary counter has n flip-flops and it has 2𝑛 distinct states of outputs.
• After reaching the maximum count the counter resets to 0 on arrival of the next clock pulse and it
starts counting again.

Synchronous Counter:
• When counter is clocked such that each flip-flop in the counter is triggered at the same time,
the counter is called synchronous counter.
Asynchronous Counter/ Ripple Counter:
• A binary asynchronous/ ripple counter consists of a series connection of complementing flip-
flops, with the output of each flip-flop connected to the clock input of the next higher-order
flip-flop.
• The flip-flop holding the least significant bit receives the incoming clock pulses.
Asynchronous Counter Synchronous Counter
In this type of counter flip-flops are connected in such
a way that output of first flip-flop drives the clock for
the next flip-flop.
In this type there is no connection between output of
first flip-flop and clock input of the next flip-flop.
All the flip-flops are not clocked simultaneously. All the flip-flops are clocked simultaneously.
Logic circuit is very simple even for more number of
states.
Design involves complex logic circuit as number of
states increases.
Main drawback of these counters is their low speed as
the clock is propagated through number of flip-flops
before it reaches last flip-flop.
As clock is simultaneously given to all flip-flops
there is no problem of propagation delay. Hence they
are high speed counters and are preferred when
number of flip-flops increases in the given design.

Modulus of counter
• The total number of counts or stable states a counter can indicate is called ‘Modulus’.
• The term ‘modulo’ is used to describe the count capability of counters.
• For example, mod-6 counter goes through states 0 to 5 and mod-4 counter goes through
states 0 to 3.
Draw the state diagram of MOD-10 Counter.

Ripple / Asynchronous Counters
• A binary asynchronous/ ripple counter consists of a series connection of complementing flip-
flops, with the output of each flip-flop connected to the clock input of the next higher-order
flip-flop.
• The flip-flop holding the least significant bit receives the incoming clock pulses.
• A complementing flip-flops can be obtained from a JK flip-flop with the J and K inputs tied
together or from a T flip-flop.
• The clock signal is connected to the clock input of only first stage flip-flop.
Two-bit asynchronous binary counter Timing diagram for the counter

1. Draw the logic diagram for 3-stage asynchronous counter with negative edge
triggered flip-flops.
Logic Diagram of 3-stage negative edge triggered counter
Timing diagram for the counter

Logic diagram of 4-stage positive edge triggered ripple counter:
Asynchronous / Ripple Down counter:
The down counter will count downward from a maximum count to zero.

Timing diagram of 4-bit asynchronous down counter

Asynchronous Up/Down counter
• To form an asynchronous up/down counter one control input, M is necessary to control the
operation of the up/down counter.
• When M=0, the counter will count down and M=1, the counter will count up. To achieve this
the M input should be used to control whether the normal flip-flop output (Q) or the inverted
flip-flop output (𝑄) is fed to drive the clock signal of the successive stage flip-flop.
Inputs Output
M Q 𝑸 Y
0 0 0 0
M=0, Y=𝑄 for
down counting
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
M=1, Y=𝑄 for
up counting
1 0 1 0
1 1 0 1
1 1 1 1

3-bit asynchronous up/down counter

Design a 4-bit up/down ripple counter with a control for up/down counting.

Design of Ripple (Asynchronous) Counters
Steps involved in the design of asynchronous counter:
1. Determine the number of flip-flops needed.
2. Choose the type of flip-flops to be used: T or JK. If T flip-flops are used connect
T input of all flip-flops to logic 1. If JK flip-flops are used connect both J and K
inputs of all flip-flops to logic 1. Such connection toggles the flip-flop output on
each clock transition.
3. Write the truth table for the counter.
4. Derive the reset logic by K-map simplification.
5. Draw the logic diagram.

2. Design BCD ripple counter using JK flip-flop.
Solution:
Step 1:Determine the number of flip-flop used. The BCD counter goes
through states 0-9,i.e., total 10 states. Thus N=10 and 2𝑛≥N, we need
n=4, i.e., 4 flip-flops required.
Step 2: Type of Flip-flops to be used: JK
Step 3: Write the truth table for the counter.
Step 4: Derive reset logic: 𝑌 = 𝐴 + 𝐵𝐶
Step 5: Draw the logic diagram
CLK A B C D
Output of
reset logic
Y
0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
- 1 0 1 0 0
- 1 0 1 1 0
- 1 1 0 0 0
- 1 1 0 1 0
- 1 1 1 0 0
- 1 1 1 1 0

Design mod 6 ripple counter using T flip-flops.
Solution:
Step 1:Determine the number of flip-flop used. The counter goes through states 0-5,i.e., total 6
states. Thus N=6 and 2𝑛≥N, we need n=3, i.e., 3 flip-flops required.
Step 2: Type of Flip-flops to be used: T
Step 3: Write the truth table for the counter.
Step 4: Derive reset logic: 𝑌 = 𝐴 + 𝐵
CLK A B C
Output of
reset logic
Y
0 0 0 0 1
1 0 0 1 1
2 0 1 0 1
3 0 1 1 1
4 1 0 0 1
5 1 0 1 1
- 1 1 0 0
- 1 1 1 0

Synchronous Counters
• When counter is clocked such that each flip-flop in the counter is triggered at the
same time, the counter is called synchronous counter.
2-bit Synchronous Binary Up Counter:
CP 𝑄𝐵 𝑄𝐴
0 0 0
1 0 1
2 1 0
3 1 1

3-bit Synchronous Binary Up Counter
CP 𝑄𝐶 𝑄𝐵 𝑄𝐴
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
Timing Diagram for 3-bit synchronous binary counter
State Sequence for 3-bit synchronous binary counter

4-bit Synchronous Binary Up Counter

Design of Synchronous Counters
1. Determine the number of flip-flops needed. If n represents number of flip-flops
2𝑛≥number of states in the counter.
2. Choose the type of flip-flops to be used.
3. Using excitation table for selected flip-flop determine the excitation table for the
counter.
4. Use K-map or any other simplification method to derive the flip-flop input
functions.
5. Draw the logic diagram.

Design a MOD-5 synchronous counter using JK flip-flops and implement it. Also draw
the timing diagram.
Solution:
Step 1: Determine the number of flip-flop needed. Flip-flops required are 2𝑛≥ N
N=5  n=3 i.e., three flip-flops are required.
Step 2: Type of flip-flop to be used: JK
Step 3: Determine the excitation table for the counter.
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Present State Next state Flip-flop inputs
QC QB QA QC+1 QB+1 QA+1 JC KC JB KB JA KA
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 0 0 0 X 1 0 X 0 X
1 0 1 X X X X X X X X X
1 1 0 X X X X X X X X X
1 1 1 X X X X X X X X X

Step 4: K-Map simplification
𝐽𝐶 = 𝑄𝐵𝑄𝐴
𝐾𝐶 = 1
𝐽𝐵 = 𝑄𝐴
𝐾𝐵 = 𝑄𝐴
𝐽𝐴 = 𝑄𝐶
𝐾𝐴 = 1
Step 5: Draw the logic diagram.

1. Design a MOD-10 synchronous counter using JK flip flops. Write the execution table and state table.
Step 1: N=10, 24>10; Flip flops needed = 4
Step 2: Flip flop used: JK
Present State Next State Flip flop inputs
A B C D A+ B+ C+ D+ JA KA JB KB JC KC JD KD
0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X
0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1
0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X
0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X
0 1 0 1 0 1 1 0 0 X X 0 1 X X 1
0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X
0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1
1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X
1 0 0 1 0 0 0 0 X 1 0 X 0 X X 1
1 0 1 0 X X X X X X X X X X X X
1 0 1 1 X X X X X X X X X X X X
1 1 0 0 X X X X X X X X X X X X
1 1 0 1 X X X X X X X X X X X X
1 1 1 0 X X X X X X X X X X X X
1 1 1 1 X X X X X X X X X X X X
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Step 4: K-Map Simplification
𝑱𝑩 = 𝑪𝑫
𝑲𝑩 = 𝑪𝑫
𝑱𝑨 = 𝑩𝑪𝑫
𝑲𝑨 = 𝑫
𝑱𝑪 = 𝑨𝑫
𝑲𝑪 = 𝑫
𝑱𝑫 = 𝟏
𝑲𝑫 = 𝟏

Design a three bit synchronous counter with T flip flop and draw the diagram.
• Step 1: N=7, 23>7; Flip flops needed = 3
• Step 2: Flip flop used: T
• Step 3: Excitation table
A B C A+ B+ C+ TA TB TC
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
𝑸𝒏 𝑸𝒏+𝟏 T
0 0 0
0 1 1
1 0 1
1 1 0
Step 4: K-map Simplification
𝑻𝑨 = 𝑩𝑪
𝑻𝑩 = 𝑪
𝑻𝑪 = 𝟏

Design a synchronous decade counter using D flip-flop.
Step 1: N=10, 24>10; Flip flops needed = 4
Step 2: Flip flop used: D
𝑸𝒏 𝑸𝒏+𝟏 D
0 0 0
0 1 1
1 0 0
1 1 1
Present State Next State Flip flop inputs
D C B A D+ C+ B+ A+ DD DC DB DA
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 0
0 0 1 0 0 0 1 1 0 0 1 1
0 0 1 1 0 1 0 0 0 1 0 0
0 1 0 0 0 1 0 1 0 1 0 1
0 1 0 1 0 1 1 0 0 1 1 0
0 1 1 0 0 1 1 1 0 1 1 1
0 1 1 1 1 0 0 0 1 0 0 0
1 0 0 0 1 0 0 1 1 0 0 1
1 0 0 1 0 0 0 0 0 0 0 0
1 0 1 0 X X X X X X X X
1 0 1 1 X X X X X X X X
1 1 0 0 X X X X X X X X
1 1 0 1 X X X X X X X X
1 1 1 0 X X X X X X X X
1 1 1 1 X X X X X X X X

Step 4: K-Map Simplification
𝑫𝑩 = 𝑨𝑩𝑫 + 𝑨𝑩 𝑫𝑫 = 𝑨𝑫 + 𝑨𝑩𝑪
𝑫𝑪 = 𝑩𝑪 + 𝑨𝑪 + 𝑨𝑩𝑪
𝑫𝑨 = 𝑨

Design a binary counter using JK flip flops to count in the following sequences:
• (i) 000,001,010,011,100,101,111,000
• Step 1: N=7, 23>7; Flip flops needed = 3
• Step 2: Flip flop used: JK
• Step 3: Excitation table
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
A B C A+ B+ C+ JA KA JB KB JC KC
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 1 X 0 1 X X 0
1 1 0 X X X X X X X X X
1 1 1 0 0 0 X 1 X 1 X 1

• Design a synchronous counter with states 0,1,2,3,0,1,….. using JK FFs.
• Design a 3-bit binary counter using T flip-flop that has a repeated sequence of
six states, 000-001-010-100-101-110.

HDL for Sequential Circuits
Verilog HDL code in behavioral model of a D latch.
module D_latch (D,control,Q);
input D;
input control;
output Q;
reg Q;
always@(control)
if(control)Q<=D;//if(control=1)
endmodule
Control D Q
1 0 0
1 1 1

Verilog HDL code for behavioral model of a JK flip-flop.
module JK_FF (J,K,CLK,Q,𝑄);
input J,K;
input CLK;
output Q,𝑄;
reg Q;
assign 𝑄=~Q;
always@(posedge CLK)
case({J,K})
2`b00:Q<=Q;
2`b01:Q<=1`b0;
2`b10:Q<=1`b1;
2`b11:Q<=~Q;
endcase
endmodule
J K 𝑸𝒏+𝟏
0 0 𝑸𝒏
0 1 0
1 0 1
1 1 𝑸𝒏

Verilog HDL code for given Moore state diagram using behavioral model.
module Moore_ckt(X,CLK,Reset,Y);
input X;
input CLK,Reset;
output Y;
reg[1:0]Prestate;
parameter a=2`b00;b=2`b01,c=2`b10,d=2`b11;
always@(posedge CLK or negedge Reset)
if(~Reset)Prestate=a;// Reset to state a
else
case(Prestate)
a:if(X)Prestate<=a; else prestate<=b;
b:if(X)Prestate<=c; else prestate<=d;
c:if(X)Prestate<=c; else prestate<=d;
d:if(X)Prestate<=d; else prestate<=a;
endcase
always@(prestate)//Determine output
case(Prestate)
a:Y<=0;
b:Y<=1;
c:Y<=1;
d:Y<=0;
endcase
endmodule

Write HDL code for the following Mealy state
diagram.
module Mealy_ckt(X,CLK,Reset,Y);
input X;
input CLK,Reset;
output Y;
reg Y;
reg[1:0]Prestate, Nextstate;
parameter a=2`b00;b=2`b01,c=2`b10,d=2`b11;
always@(posedge CLK or negedge Reset)
if(~Reset)Prestate<=a;
else Prestate<=Nextstate;
always@(Prestate or X)
case(Prestate)
a:if(X) Nextstate <=b
else Nextstate <=a;
b:if(X) Nextstate <=d
else Nextstate <=a;
c:if(X) Nextstate <=c
else Nextstate <=a;
d:if(X) Nextstate <=c
else Nextstate <=a;
endcase
always@(prestate or X)
case(Prestate)
a:Y<=0;
b:if(X) Y<=1`b0; else Y<=1`b1;
c:if(X) Y<=1`b0; else Y<=1`b1;
d:if(X) Y<=1`b0; else Y<=1`b1;
endcase
endmodule

Verilog HDL code in structural model of a buffer register.
module buf_reg(A,B,C,D,CP,QA,QB,QC,QD);
input A,B,C,D; //Parallel input
input CP; //Clock input
output QA,QB,QC,QD; //Parallel output
//Instantiate the four stages
STG STG0 (A,CP,QA);
STG STG1 (B,CP,QB);
STG STG2 (C,CP,QC);
STG STG3 (D,CP,QD);
endmodule
//One stage of D-flip-flop
module STG(D,CP,Q);
input D;
input CP;
output Q;
reg Q;
reg D;
always @(negedge CP)
Q<=D
endmodule

Verilog HDL code in structural model of a ripple counter.
module ripple_ctr(Count,Reset,A0,A1,A2,A3);
input Count, Reset;
output A0,A1,A2,A3;
//Instantiate complementing flip-flop
STG STG0(Count,Reset,A0);
STG STG1(A0,Reset,A1);
endmodule
//One stage of a counter
//Complementing flip-flop with delay
module STG(CLK,Reset,Q);
input CLK,Reset;
output Q;
reg Q;
always @(negedge CLK or negedge Reset)
If(~Reset)Q<=1’b0;
else Q<=#2(~Q); //Delay of 2 time units
endmodule

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