Slide deck of "Life Beyond Moore's Law"

1. 3D Memory with Shared Lithography Steps:
The memory industry’s plan to cram more components onto integrated circuits
Deepak C. Sekar
Rambus Labs
Invited Paper at the IEEE S3S Conference,
7th October 2014

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The past 50 years
Today
The future
“Reduce feature sizes and boost component density”
Is there an alternative paradigm to lower cost per transistor every generation?
YES
Topic of this presentation…

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Outline
Introduction
The Post-Scaling Plan for Storage
The Post-Scaling Plan for Memory
Conclusions and Thoughts
?
Vertical electrode
Memory cell
Horizontal
electrode

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Introduction

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The Memory Hierarchy
CPU
Memory
Fast CPU
waits for data
DRAM
Storage
•Slow CPU does not wait for data, changes process or thread
•10x lower cost per bit vs. memory ( or more) NAND flash/HDD

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Motivation for Post-Scaling Paradigms: (#1) Litho Cost
Difficult to work around wafer cost increases caused by multiple patterning

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Motivation for Post-Scaling Paradigms: (#2) Metrics of Memory Components Degrade on Scaling
Flash memories
The few electron problem
Lack of space to scale feature size of a wrap-around cell
Sources: Chipworks, K. Prall, et al., IEDM 2010
CG
FG
•Tunnel ox~6.7 nm, ~12 nm NONON inter-poly dielectric
•WL pitch ~38nm, BL ~52 nm, cell size ~0.0018 μm2.

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Motivation for Post-Scaling Paradigms: (#2) Metrics of Memory Components Degrade on Scaling
DRAM
Sources: Hynix, AMD
and, in general
Wire RC more of a challenge
DRAM Challenge: Capacitor

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The Post-Scaling Plan for Storage
The Post-Scaling Plan for Storage

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The Central Idea: 3D with Litho Steps Shared Among Multiple Memory Layers
Source: J. Jang, et al., VLSI 2009

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Benefits of the Shared Litho Approach
Source: H. Tanaka, et al., VLSI 2007

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Staircase Patterns for Contacts with a Shared Litho Step
Source: H. Tanaka, et al., VLSI 2007

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Write Operations for The 3D Flash Cell
Bulk erase using the substrate (above)
Program like conventional flash
Source: J. Jang, et al., VLSI 2009

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Chip-level benchmarks for 3D NAND
Memory Layers
Die capacity
8
16Gb
24
128Gb [6][7]
3D: 40nm, 133mm2
2D: 16nm, 173mm2
192
1Tb
Source: K-T. Park, et al., ISSCC 2014
•Bigger component sizes in 3D NAND improve electrical performance
•Die size quite competitive

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Commercial SSDs Now Shipping with 3D NAND
3D NAND SSD vs. 2D NAND SSD: ~10% higher performance, 10-38% lower power.
2x the lifetime.
Source: Samsung, Flash Memory Summit, 2014
PCMark7 benchmark

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The future, according to Samsung: 3D NAND with an Increased Number of Layers
Yes, we are starting to move into the post-scaling era
2D NAND
3D NAND
Source: Samsung, Flash Memory Summit, 2014

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The Post-Scaling Plan for Memory
Vertical electrode
Memory cell
Horizontal
electrode

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Can We Develop a Post-Scaling Approach for Memory? Shared Litho Steps Hard for 3D DRAM Due to Big Capacitor
Future memory system the industry is researching
Small amount of DRAM +
Large amount of 3D RRAM with shared litho steps
Minimum Required
Bit-level Endurance
109
Bit-level
Retention
5 days
Chip Latency
200ns-1μs
Cost per Bit
Between DRAM and Flash
CPU
Memory
Storage
DRAM
3D
RRAM
NAND
Flash
Source: ITRS

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What is RRAM?
Simple materials, but still good switching: Key reason for the excitement about RRAM
Single cell @ 45nm node
Phase Change Memory
STT-MRAM
RRAM
Materials
TiN/GeSbTe/TiN
Ta/PtMn/CoFe/Ru/CoFeB/MgO/CoFeB/Ta
TiN/Ti/HfOx/TiN
Write Power
300uW
60uW
50uW
Switching Time
100ns
4ns
5ns
Endurance
1012
>1014
1010
Retention
10 years, 85oC
10 years, 85oC
10 years, 85oC
Ref: PCM – Numonyx @ IEDM’09, MRAM: Literature from 2008-2010, RRAM – ITRI @ IEDM 2008, 2009

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RRAM Switching Mechanism
Filamentary switching with oxygen vacancies
Before FORM
After +4V FORM
After -2V RESET
After +2V SET
HfO2
Pt
TiN
HfO2
Pt
TiN
HfO2
Pt
TiN
HfO2
Pt
TiN
Ultra-high Z
>1GΩ
Low Z
~10kΩ
High Z
~1MΩ
Low Z
~10kΩ
Image of a filament
Ref: D-H. Kwon, et al., Nature Nanotechnology, 2010.
TiN

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Can 3D RRAM Meet Requirements for Memory Applications?
Endurance feasible.
Latency depends on architecture, so feasible
Can we get a chip with ALL THESE AT THE SAME TIME though?
Focus of active research.
Source: Panasonic
Minimum Required
Bit-level Endurance
109
Bit-level
Retention
5 days
Chip Latency
200ns-1μs
Cost per Bit
Between DRAM and Flash

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Architectures for 3D RRAM: (1) 3D Crosspoint Memory
Multiple layers of memory made with the same set of litho steps  keeps litho cost down
(eg) 32 layers of memory in a 8F2 footprint  0.25F2
The key challenge:
•Multiple memory devices share a transistor selector, so sneak leakage paths possible
•Makes read and write difficult
RRAM dielectric (eg) ZrO2
Top electrode (Local BL)
Deposit bilayers of WL
(eg. W) and SiO2
Hole etch
(Shared litho step)
Deposit RRAM
Dielectric
Deposit Top Electrode,
Which serves s the Local BL

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Architectures for 3D RRAM: (1) 3D Crosspoint Memory, from Rambus
While these silicon results look reasonable, significant work to do still (to get a product) Our memory device could tackle sneak paths and have sub-1μA write, but couldn’t meet 109 cycles endurance + 5 day retention
64Mb crosspoint chip, ISSCC 2010
Silicon results from our test chip Needed specially optimized memory devices and circuits to avoid sneak paths

24. Architectures for 3D RRAM: (2) 3D 1T-1R RRAM [D. Sekar, Z. Or-Bach, from MonolithIC 3D Inc.]
(a) Deposit multiple SiO2/poly Si layers. Or use ion- cut to make SiO2/c-Si layers.
(b) Pattern (shared litho step)
(c) Form gate of select transistors
(shared litho step)
(d) Pattern SL, then silicide
(shared litho step)
(e) Form RRAM dielectric and electrode for multi-level 1T-1R cells. (shared litho step)
(g) Form BLs

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Architectures for 3D RRAM: (2) 3D 1T-1R RRAM [D. Sekar, Z. Or-Bach, from MonolithIC 3D Inc.]
•At the 20nm node, effective cell size for 15 memory layers is 5x lower than DRAM.
•Early days for this architecture still… not yet proven in a prototype.
•Benefit is that it does not have sneak path issues (which place severe constraints on memory device optimization)
Junction-free transistor selector, like 3D NAND.

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?
Conclusions and Thoughts

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The Post-Scaling Era is Beginning…
Exciting opportunities exist to develop such concepts and products for non-storage applications:
•Memory
•Logic
Gave some examples for memory applications in this talk.
The new paradigm:
•3D stacking with litho steps shared among multiple layers
•Commercialized for flash storage

28. Thank You