Paper on "Life Beyond Moore's Law"

1. 3D Memory with Shared Lithography Steps:
The Memory Industry’s Plan to “Cram More Components onto Integrated Circuits”
Deepak C. Sekar
Rambus Labs
Invited Paper
In his 1965 paper titled “cramming more components onto integrated circuits” [1], Gordon Moore predicted the number of components on a chip would increase exponentially with time due to continual reduction of feature sizes. That paradigm has continued successfully for the past 50 years, but cracks are starting to appear. Lithography is becoming prohibitively expensive and component quality is expected to degrade significantly beyond the 7nm node. To lower cost per bit further without relying on feature size scaling, monolithic 3D flash memories are being introduced where lithography steps are shared among multiple memory layers. In this paper, I review the flash memory industry’s direction and describe 3D concepts that can scale other parts of the memory hierarchy.
I. INTRODUCTION
Systems for most enterprise and consumer markets use a memory hierarchy consisting of memory and storage components (Fig. 1). Memory components such as DRAM are relatively fast - the CPU waits for the requested data. Storage components such as NAND flash are slow and cheap - the CPU does not wait for data and changes the process or thread.
Figure 1: Memory hierarchy.
Historically, we have seen exponential improvements of cost per bit for memory and storage ICs with time. This was driven by shrinking feature sizes every 1-3 years. However, this paradigm seems to be hitting some severe challenges now.
Figure 2: Lithography cost no longer follows historical trends.
As Fig. 2 indicates, lithography cost for scaling ICs to smaller feature sizes no longer follows historical trends [2]. For memory and storage ICs which are driven by cost per bit, this can be a show-stopper. Component quality, namely the ability of components to meet application requirements, is considered an important challenge beyond the 10nm and 7nm nodes too [3]. DRAMs face difficult challenges with stacked capacitor scaling [3], while NAND flash faces difficult challenges with few electron effects and cell-to-cell interference [3]. It is clear that alternative paradigms to scale cost per bit for memory and storage ICs are required.
II. 3D STORAGE WITH SHARED LITHOGRAPHY STEPS
A new approach that allows continuous cost per bit reduction has recently gained traction for NAND flash memories. Innovative architectures have been developed that allow multiple 3D stacked memory layers to be patterned with a common set of lithography steps [4][5][6]. Fig. 3 shows an example, which uses charge trap NAND flash cells.
Figure 3: A 3D NAND flash architecture which uses shared lithography steps [5].
The process flow in Fig. 4 depicts how shared lithography steps can be used for defining such an architecture. Multiple oxide/nitride layers are deposited, following which shared lithography steps are used to form NAND flash memory strings with metal gates and charge trap dielectrics. Polysilicon is used as the channel material, but I-V characteristics are acceptable since the grain size is large compared to cell dimensions, and because the device structure is “gate-all-around”, with excellent electrostatic control.
Fig. 5 shows the architecture in Fig. 3 allows continuous cost per bit reduction by periodically increasing the number of memory layers. This puts the burden of cost per bit reduction

2. on processes such as high aspect ratio etch and deposition, which have more room for improvement vis-à-vis lithography. Compared to 2D NAND, one can use larger dimension cells but still get similar densities (Fig. 6). The use of larger cell sizes improves performance and endurance characteristics [6], as indicated by the threshold voltage distributions in Fig. 6. With commercial 3D NAND introduced recently [8], and several generations of improvement possible, it certainly looks like this “post-feature-size scaling” paradigm is here to stay.
.
Figure 4: Process flow for 3D NAND flash [5].
Figure 5: Charge trap dielectric and electrode definition [5].
Memory Layers
Die capacity
8
16Gb
24
128Gb [6][7]
3D: 40nm, 133mm2
2D: 16nm, 173mm2
192
1Tb
Figure 6: Scaling, distributions for 3D NAND [6].
III. 3D MEMORY WITH SHARED LITHOGRAPHY STEPS
Just like for storage, if one can have monolithic 3D architectures with shared lithography steps for memory, it would be quite beneficial. However, the high aspect ratio capacitor needed for conventional DRAM makes this difficult.
Fig. 7 shows an approach that is being researched by several organizations [9][10]. Emerging memories such as Resistive RAM (RRAM), Conductive Bridge RAM (CB-RAM) and others lend themselves to 3D stacking with shared lithography steps easier than capacitor-based DRAM. The “memory” layer of future systems could potentially be composed of two types of memory: a small amount of conventional DRAM and a large amount of 3D Resistive Memory made with shared lithography steps, as shown in Fig. 7.
Figure 7: A paradigm for continuing memory scaling.
The International Technology Roadmap for Semiconductors [3] gives requirements for this application (Fig. 7). A low- power memory device that can meet all the requirements in Fig. 7 is yet to be developed. However, there is promise. RRAMs are known to switch at less than 10ns [9], so the chip latency requirements in Fig. 7 are feasible. Endurance required at the bit-level is 109 cycles. As Fig. 8 indicates [11], endurance for RRAM has been improving as the technology matures, indicating 109 cycles may be feasible. Several avenues exist to improve endurance further. (1) RRAMs are conventionally optimized for 10 year retention. For the “memory application” in Fig. 7, memory devices and programming algorithms can be optimized for 5 day retention, which can improve endurance significantly. (2) Endurance fail modes for RRAM are still largely unknown. As endurance fail modes are understood, countermeasures can be developed. (3) Fast wear-leveling algorithms [12] can help too.
Figure 8: Endurance for RRAM has steadily improved [11].
.
Figure 9: Vertical crosspoint memory with shared litho steps.
Several architectures have been pursued for building monolithic 3D resistive memories with shared lithography steps. Fig. 9 shows a commonly pursued architecture, a vertical crosspoint memory, also called a 1T-many R memory
Quantity
Required
Bit Endurance
109
Bit Retention
5 days
Chip Latency
200ns- 500ns

3. [13]. Select transistors on the substrate are shared among multiple memory layers patterned with shared lithography steps. The key challenge with this architecture is that not every memory device has a selector of its own, leading to “sneak leakage paths” when memory arrays are built. Ways to reduce “sneak paths” include designing and smartly biasing memory devices with non-linear I-V curves [14], as well as circuit schemes to detect and compensate sneak paths. Fig. 9 shows ON and OFF state distributions of a 130nm crosspoint memory chip [14] from Rambus that successfully tackled sneak path issues, albeit with access times slower than Fig. 7.
Figure 10: An alternative 3D architecture [15] with shared lithography steps and multilayer 1T-1R cells.
The biggest challenge with vertical crosspoint memories is that it is difficult to develop a low-power memory cell with non-linear I-V characteristics which can meet all the requirements in Fig. 7. The multi-layer 1T-1R architecture in Fig. 10, invented by the author and Zvi Or-Bach [15], could be used to tackle this problem. It uses shared lithography steps and creates double gated junction-free transistors as selectors. Sneak paths are eliminated since each RRAM device has a selector of its own. Compared to DRAM, significant improvements in density, scalability and refresh power are possible (Fig. 10(h)).
Unlike the concepts in Section II, the monolithic 3D memory concepts in Section III are still in the research stage, with several unsolved challenges. It should be an exciting area for innovation for the next 5-10 years.
IV. SUMMARY
For the past 50 years, integrated circuits have seen tremendous improvements in cost, performance and power by scaling feature sizes of components every few years. We are now reaching feature sizes where lithography cost and component quality are posing serious limitations. In this paper, I described the strategy the memory industry is developing to tackle these limitations and move forward. It involves using monolithic 3D technology with lithography steps shared among multiple memory layers. 3D NAND flash chips built with these concepts are being introduced to the marketplace now [8], revealing the feasibility of this strategy. I described ways one could extend these monolithic 3D concepts beyond just storage chips, and showed ways to apply them to memory.
ACKNOWLEDGEMENTS
The author would like to thank Gary Bronner (Rambus) and Zvi Or-Bach (MonolithIC 3D Inc.) for helpful discussions.
REFERENCES
[1] Moore, Gordon E., "Cramming more components onto integrated circuits, Electronics, volume 38, number 8, April 19, 1965.
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[10] Burr, G.W.; Kurdi, B.N.; Scott, J.C.; Lam, C.H.; Gopalakrishnan, K.; Shenoy, R.S., "Overview of candidate device technologies for storage- class memory," IBM Journal of Research and Development , vol.52, no.4.5, pp.449,464, July 2008.
[11] Summarized by Panasonic, International Memory Workshop, 2012.
[12] Qureshi, M.K.; Karidis, J.; Franceschini, M.; Srinivasan, V.; Lastras, L.; Abali, B., "Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling,", Proc. MICRO, 2009
[13] Hong Sik Yoon; et al., "Vertical cross-point resistance change memory for ultra-high density non-volatile memory applications," VLSI Technology, 2009 Symposium on , vol., no., pp.26,27, 16-18 June 2009
[14] Chevallier, C.J.; et al., "A 0.13μm 64Mb multi-layered conductive metal-oxide memory," Proc. ISSCC, 2010
[15] D. C. Sekar, Z. Or-Bach, US Patent 8581349, Filed 2011, Issued 2013.