2. Agenda
1. Why Industry Wants Costly SCM
2. Why Conventional NAND is Slow
3. Building On-chip DRAM to Multiply Speed
4. Cell Structures: DRAM vs. NAND vs. HiNAND
5. 3D-NAND àAI-NAND array with J-fold performance
improvement
3. Why The Industry Wants SCM?
• Computers need faster storage than NAND
o But SCM (3D XPoint, MRAM, ReRAM) will be expensive
• Today’s NAND performs worse than it needs to be
o High precharge & discharge RstringCBL
o Slower latency, Higher power consumption, Poorer data quality
o Each plane is limited to one R/P/E operation at a time
What if we could make NAND as fast as DRAM
without process change and refresh operation?
4. Conventional 3D-NAND Array Layouts
Samsung 3D V-NAND
Two Planes, 256Gb/TLC/48L
WD/Toshiba 3D BiCS-NAND
Two Planes, 512Gb/TLC/64L
Plane-0
Plane-1
Plane-0
Plane-1
Plane-2
Plane-3
Plane-0
Plane-1
Plane-2
Plane-3
Plane-0
Plane-1
SK-Hynix 3D-NAND
Four Planes, 128Gb
Maximum: 1-Task/Plane"
Micron/Intel 3D NAND
Four Planes/256Gb/MLC/32L
5. Solution: Building On-Chip J-Page DRAM
within NAND Array to Multiply Speed
• Turns prior NAND array into a novel Hierarchical array with
J divided-GBL/LBLs by adding one M3 GBL metal layer
• J divided M2 CLBLs form J-page N-bit DRAM without using
special capacitor process, where J ≥ 8 for J independent
task operations (Read/Program/Erase)
• N-bit CLBL can be used as a N-bit DRAM cache
• AI-NAND = DRAM (Fast Front-end) + NAND
(Low-cost Back-end)
