IEEE Embedded Project list

E2MATRIX
Opp. Phagwara Bus Stand
Parmar Complex, Phagwara
Punjab ( INDIA ).
Contact : +91 9041262727, 9779363902
email : support@e2matrix.com
web : www.e2matrix.com
E2MATRIX
Research Lab
E2MATRIX

E2MATRIX
Opposite bus stand parmar complex, Phagwara,Punjab, ( India )
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
support@e2matrix.com, e2matrixphagwara@gmail.com
Sr.No.
Project List (Tanner Eda
tool/cadence virtuoso)
year Publisher
1. 2GHZ PLL Frequency Synthesizer for
Zigbee Applications
2014 International Journal of
Innovative Research in Computer
and Communication Engineering
2. DESIGN AND SIMULATION OF
CMOS OTA WITH 1.0 V, 55db GAIN &
5PF LOAD
2014 International Journal of Managing
Public Sector Information and
Communication Technologies
(IJMPICT)
3. A Novel High Performance Enhanced
Pulse Triggered Flip Flop
2014 International Journal of scientific
research and management
(IJSRM)
4. Implementation of Adiabatic Flip Flop
And Sequential Circuits Based on CPAL
Circuits
2014 International Journal of Advanced
Research in Electrical,
Electronics and Instrumentation
Engineering
5. AN OPTIMAL FLIP FLOP DESIGN
FOR VLSI POWER MINIMIZATION
2014 International Journal of Advances
in Engineering & Technology,
6. VLSI DESIGN OF BARREL SHIFTER
USING COMPLEMENTARY AND
PSEUDO NMOS LOGIC
2014 Proceedings of 4th IRF
International Conference
7. Design of Low Power Combinational
Circuits Using Reversible Logic and
Realization in Quantum Cellular
Automata
2014 International Conference on
Innovations in Engineering and
Technology
8. Performance Analysis of Full Adder
Using Different CMOS Logics
2014 ijesc
9. An Improved Shannon Adder Based Low
Power Bough Wooley multiplier in
Switching Activities of Partial Products
Innovations in Scientific and
Engineering Research (IJISER)
10. Comparative Analysis of low area and
low power D Flip-Flop for Different
Logic Values
2014 International Journal Of
Engineering And Science (IJES)
11. High Performance 8x8 Bit Multiplier
Design Using Pass Transistor Logic
2014 International Journal of Trends in
Computer Science
12. Analysis of Conventional Sram6t at Low
Power and High Performance 32nm
Technologies
2014 Int. Journal of Engineering
Research and Applications
13. ESTIMATION OF STATIC AND
DYNAMIC PARAMETERS OF FLASH
ADC USING 180 NM TECHNOLOGY
2014 IJAICT

E2MATRIX
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
14. COMPARISON of SRAM CELLS AT
45nm, 32nm and 22nm TECHNOLOGY
2014 Progress In Science and
Engineering Research Journal
15. Compression and Decompression of
Signal Using CMOS Technology...A
Review
2014 International Journal of Advanced
Research in
Computer Science and Software
Engineering
16. Design and Analysis of Multipliers Using
Energy Recovery Adiabatic Logics
2014 International Journal of Emerging
Research in Management
&Technology
17. Design of Moderate Speed and Moderate
Resolution Successive Approximation
Analog to Digital Converter
2014 International Journal of Computer
Science and Mobile Computing
18. Power Efficient CMOS Full Adders with
Reduced
Transistor Count
Engineering Research &
Technology
19. A CMOS BANDGAP AND SUB-
BANDGAP VOLTAGE REFERENCE
CIRCUITS FOR NANOWATT POWER
LSIs
2014 INTERNATIONAL JOURNAL
OF RESEARCH IN COMPUTER
APPLICATIONS AND
ROBOTICS
20. Design of carry look head full adder
using CMOS technique
2014 IOSR Journal of Electronics and
Communication Engineering
21. Comparative Analysis Different Adder
Topologies using 180nm Technology
2014 International Journal for Science
and Emerging Technologies with
Latest Trends”
22. Design of Tunable 3rd Order Chebyshev
Low Pass Filter
based on Floating Inductor
2014 International Journal of Research
in Advent Technology
23. DESIGN OF 4-BIT FLASH ANALOG
TO DIGITAL CONVERTER
USING CMOS COMPARATOR IN
TANNER TOOL
Engineering and Applications
24. DESIGN OF 4-BIT FLASH ANALOG
TO DIGITAL CONVERTER USING
CMOS COMPARATOR IN TANNER
TOOL
2014 KIET International Journal of
Communications & Electronics
25. Design of Low Power Novel Viterbi
Decoder Using Multiple Threshold
CMOS Logic
2014 International Journal of Science
and Research (IJSR)
26. Design and Analysis of 2:1 Multiplexer
Using Low Power Adiabatic Technique
and Its Application in Nibble Multiplexer
2014 International Journal for
Scientific Research &
Development
27. POWER ANALYSIS OF 4T SRAM BY
STACKING TECHNIQUE USING
TANNER TOOL
2014 International Journal of Research
in Engineering and Technology

E2MATRIX
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
28. Low Power Design of Standard Digital
Gate Design Using Novel Sleep
Transistor Technique
2014 International OPEN ACCESS
Journal Of Modern Engineering
Research
29. Design and Implementation of Area
Optimized ALU using GDI Technique
2014 INTERNATIONAL
JOURNALOF INNOVATIVE
RESEARCHIN ELECTRICAL,
ELECTRONICS,
INSTRUMENTATION AND
CONTROL ENGINEERING
30. Study and Analysis of Universal Gates
Using Stacking Low Power Technique
Computer Science and
Information Technologies
31. Analysis and Design of High Speed Low
Power Comparator in ADC
Engineering Development and
Research
32. A Novel and High Performance
Implementation of 8x8 Multiplier based
on Vedic Mathematics using 90nm
Hybrid PTL /CMOS Logic
Applications
33. Design and Simulation of Low Power
CMOS Adder Cell at 180nm using
Tanner Tool
Applications
34.
Implementation and Performance
Analysis of a Vedic Multiplier Using
Tanner EDA Tool
2014 International Journal for
Scientific Research &
Development
35. Design and Analysis of Low Power
Multipliers and 4:2 Compressor Using
Adiabatic Logic
2014 International Journal of Emerging
Technology and Advanced
Engineering
36. A TRANSISTOR LEVEL ANALYSIS
FOR A 8-BIT VEDIC
MULTIPLIER
Electronics Signals and Systems

E2MATRIX
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
S.No. Project titles(VHDL/Verilog)
1. A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2
Modified Booth Algorithm.
2. An Efficient Architecture for 3-D Discrete Wavelet Transform.
3. The Design of FIR Filter Base on Improved DA Algorithm and its FPGA
Implementation.
4. Design of On-Chip Bus with OCP Interface.
5. Design of a Self-Motivated Arbitration Scheme for the Multilayer AHB Busmatrix.
6. Low Complexity and Fast Computation for Recursive MDCT and IMDCT
Algorithms
7. A Robust UART Architecture Based on Recursive Running Sum Filter for Better
Noise Performance
8. Single chip encryptor/ decryptor core implementation using AES algoritham
9. Implementation of IEEE 802.11 a WLAN Baseband Processor
10. Design of Simple Spectrum Analyzer
11. A Dual-Purpose Real/Complex Logarithmic Number System ALU
12. An Efficient Architecture for 2-D Lifting-based Discrete Wavelet Transform.

E2MATRIX
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
13. Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers
14. A Spurious-Power Suppression Technique for Multimedia/DSP Applications
15. DDR3 based lookup circuit for high-performance network processing.
16. Multiplication Acceleration Through Twin Precision
17. A Parallel Pipelined Algorithm for the Computation of MDCT and IMDCT
18. High speed parallel architecture for cyclic convolution based on FNT
19. Design and Implementation of Wi-Fi MAC Transmit Protocol using VHDL
20. Design and Implementation of a 64-bit RISC Processor using VHDL
21. Implementation of a visible water marking in a secure still digital camera using
VLSI design
22. Embedded a low area 32 bit AES for image encryption and decryption application
23. Design of AES (Advanced Encryption Standard) Encryption and Decryption)
24. 32-bit RISC CPU Based on MIPS
25. High Speed Hardware Implementation of 1D DCT/IDCT Efficient FPGA
implementation of convolution

E2MATRIX
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
26. Implementation of a visible Watermarking in a secure still digital Camera using
VLSI design
27. High Speed VLSI Architecture for General Linear Feedback Shift Register (LFSR)
Structures
28. Implementation of FFT/IFFT Blocks for OFDM METHODOLOGIES
29. Design of 8-bit Microcontroller using verilog
30.
Design and Synthesis of High speed CAM using Xilinx Spartan3E
31. A Versatile Multimedia Functional Unit Design Using the Spurious Power
Suppression Technique (Verilog)
32. Design and Implementation of Digital low power base band processor for RFID
Tags (Verilog)
33. Design and Implementation of Reversible Watermarking for JPEG2000 Standard
34. FPGA Implementation of 3D Discrete Wavelet Transform for Real-Time Medical
Imaging
35. Design and Implementation of High Speed DDR SDRAM (Dual Data Rate
Synchronously Dynamic RAM) Controller (VHDL)
36. High Performance Complex Number Multiplier Using Booth-Wallace Algorithm
37. High Speed Parallel CRC Implementation Based On Unfolding, Pipelining and
Retiming
38. A HIGH PERFORMANCE VLSI FFT ARCHITECTURE

E2MATRIX
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
39.
Design of an Bus Bridge between OCP and AHB Protocol (VHDL)
40. Design of Gigabit Ethernet MAC (Medium Access Control) Transmitter
41. Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
42. Design of Data Encryption Standard (DES)
43. Design of Distributed Arithmetic FIR Filter
44. Design of Universal Asynchronous Receiver Transmitter (UART)
45. Design of Triple Data Encryption Standard (DES)
46. Design of 16 Point Radix-4 FFT (Fast Fourier Transform) Algorithm
47. Design of Dual Elevator Controller
48. Design of an ATM (Automated Teller Machine) Controller
49. Design of 8-Bit Pico Processor
50. Design of JPEG Image compression standard
51. Design of Digital FM Receiver using PLL (Phase Locked Loop)

E2MATRIX
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
52. Design of 16-bit QPSK (Quadrature Phase Shift Keying)
53. Design of 16-bit QAM (Quadrature Amplitude Modulation) Modulator
54. Design of AES (Advanced Encryption Standard) Encryption Algorithm with 128-bits
Key Length
55. Design of RS-232 System Controller
56. Design of Floating-Point Multiplier using IEEE-754 Standard
57. Design and Implementation of OFDM Transmitter
58. Design and synthesis of ALU, Verification using Advanced design Verification
Technique
59. Design of CRC (Cyclic Redundancy Check) Generator
60. Design Synthesis and Verification of Simple All Digital FM Receiver using Xilinx
FPGA
61. Design and Verification of 8 bit Hamming Encoder and Decoder.
62. Design and Verification of PCI-Express Bus
63. Design of UART Simulation and Synthesis using Xilinx FPGA
64. Design and Verification of Modified Booths Algorithm-Synthesis using Xilinx ISE

E2MATRIX
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
65. 5x4Gbps 0.35 Micron CMOS CRC Generator Designed With Standard Cells
66. Design and Verification of CACHE COHERENCE MEMORY.
67. Design and Synthesis of MICRO UART using Xilinx spartan3E
68. IMPLEMENTATION OF ETHERNET TRIMODE MAC
69. Triple –DES Encryption and Decryption core using VHDL
70. Design, simulation and Synthesis of CPU 8086 using Xilinx FPGA
71. Design Synthesis and Verification of PCI EXPRESS using Xilinx FPGA
72. Design and Verification of ADAPTIVE FILTER
73. Design and Synthesis of DIGITAL INSTANTANEOUS FREQUENCY
MEASUREMENT PROCESSOR
74. Low Power Register Exchange Viterbi Decoder For Wireless Applications
75. Design and Verification of “ IMPROVING MULTIPLIER DESIGN BY USING
IMPROVED COLUMN COMPRESSION TREE AND OPTIMIZED FINAL
ADDER IN CMOS TECHNOLOGY
76. Double Precision Floating Point Core
77. Design and Synthesis of DIGITAL INSTANTANEOUS FREQUENCY
MEASUREMENT PROCESSOR

E2MATRIX
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
78. Implementation of frame synchronizer using verilog
79. Design and Verification of Bluetooth Base Band Controller
80. PPI - Programmable Peripheral Interface
81. Design of FIR Filter Design Based on Faithfully Rounded Truncated MCM
(VERILOG)
82. Implementation of JPEG2000 using DWT (VERILOG)
83. Constant and high speed adder design using QSD number system (VERILOG)
84. Built in generation of functional broadside tests using a fixed hardware
structure(VERILOG)
85. MDC FFT/IFFT Processor With Variable Length (VERILOG)
86. Multi bit Flip-Flop design for Area efficiency (VERILOG)
87. FPGA implementation of multi operand redundant adders(VERILOG)
88. Comparative analysis and optimization of active power and delay of 1-bit full adder
at 45nm technology (BACK END)
89. Digital-Serial FIR Filter Algorithms, Architecture and a CAD Tool (VERILOG)
90. A Common Boolean Logic(CBL) implementation for modified CSLA (VERILOG

E2MATRIX
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
91. High speed vedic multiplier using barrel shifter (VERILOG)
92. A new approach to design fault coverage circuit with efficient hardware utilization
for testing applications (VERILOG
93. Design of Parallel Carry-Save Pipelined RSFQ Multiplier (VERILOG)
94. Single phase clock distribution using VLSI technology for low power (VERILOG)
95. Design and implementation of efficient Quaternary Signed Digit Multiplier
(VERILOG)
96. High Speed FPGA implementation of FIR Filters for DSP Applications (VERILOG)
97. Design and implementation of Floating Point Multiplier based on Vedic
Multiplication Technique (VERILOG
98. A Novel Approach for parallel CRC generation FOR High Speed Application.
(VERILOG)
99. High speed Modified Booth Encoder multiplier for signed and unsigned numbers.
(VERILOG)
100. Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA
Implementation. (VERILOG)
101. Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block
Chaining concept using Verilog and FPGA (VERILOG)
102. Implementation of an Efficient Multiplier based on Urdhva Tiryakbhyam Sutra
(VERILOG)
103. Area Efficient parallel FIR Digital Filter Structures for Symmetric Convolution based
on Fast FIR Algorithm(VERILOG)

E2MATRIX
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
104. Measurement and evaluation of power analysis attacks on Asynchronous S-Box.
(VERILOG)
105. High Speed Booth Encoded Multiplier to Minimize the Computation
time(VERILOG)
106. Design Of Area Optimized AES 128 Algorithm Using Mix column Transformation.
(VHDL)
107. LUT Optimization for Memory-Based Computation (VERILOG)
108. A Floating point Fused Dot Product Unit (VERILOG)
109. VLSI design Of a Digital Clock Using GALS Technique (VERILOG)
110. Efficient Weighted Pattern Generation Technique with Low Hardware
Overhead(VERILOG)
111. SCA-FF and SCAh-FF design for single cycle access test (VERILOG)
112. Design and implementation of a high performance multiplier using HDL (VERILOG)
113. A VLSI Implementation of Modulo Multiplier By Using Radix-8 Modified Booth
Algorithm (VERILOG)
114. Platform-Independent Customizable UART Soft-Core (VHDL)
115. A Parallel Multiplier Accumulator Based On Radix 4 Modified Booth Algorithms by
Using Spurious Power Suppression Technique (VERILOG)
116. Using Self-Immunity Technique 64-bit Register File Immunity Improvement
(VERILOG)

E2MATRIX
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
117. A Novel Nanometric Parity Preserving Reversible Vedic Multiplier (VERILOG)
118. High Speed 3D DWT VLSI Architecture for Image Processing Using Lifting Based
wavelet Transform (VERILOG)
119. Design and Analysis of Low Power Parallel Prefix VLSI Adder (VERILOG)
120. Faster and Low Power Twin Precision Multiplier(VERILOG)
121. Pulse Triggered Flip-Flop Design for low power(BACK END)
122.
FPGA Implementation of Booth's and Baugh- Wooley Multiplier (VERILOG)
123. Implementation of Area Efficient 16bit Adder in FPGA(VERILOG)
124. Reliable and Higher Throughput Anti-Collision Technique for RFID UHF Tag
(VERILOG)
125. Implementation of Bus Bridge between AHB and OCP (VHDL
126. VLSI Implementation of OLS encoders (VERILOG)
127. An Efficient FPGA implementation of Double Precision floating Point Multiplier
(VHDL)
128. Implementation of OFDM System using IFFT and FFT (VHDL)
129. FPGA Based High Speed Parallel Cyclic Redundancy Check (VERILOG)

E2MATRIX
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
130. High speed carry save multiplier based linear convolution using Vedic mathematics
(VERILOG)
131. FPGA Implementation of 2-D DCT Architecture for JPEG Image Compression
(VERILOG)
132. Design of High Speed Vedic Square by using Vedic Multiplication Techniques
(VERILOG)
133. Realization of Basic Gates Using MUX in CMOS Design (BACK END)
134. Performance Evaluation of Complex Multiplier Using Advance Algorithm (VHDL)
135. A Verilog Model of Universal Scalable Binary Sequence Detector(VERILOG)
136. Hardware modeling of binary coded decimal adder in field programmable gate
array(VERILOG)
137. High-Performance High-Valency Ling Adders (VERILOG)
138. Short Bit-Width Twos Complement Multipliers (VERILOG)
139. Design and Implementation of Two Variable Multiplier Using KCM and Vedic
Mathematics. (VERILOG)
140. Implementatiom of traffic light controller using Vhdl.

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