1. Sudhir Kumar
4607 Griffith ave
Fremont, CA 94538
Sudhirk5@hotmail.com
510-468-2579 (cell)
Visa Status GC
O
Objective Seeking a challenging and rewarding career in Digital Design & Verification
Experience
Summary
Hardware Engineer with 15+ years of industry experience in ASIC Verification. Strong
problem solving skills using analytical approach Broad experience in all aspects of
semiconductor product development process Testbench Development for unit/system level
Functional Verification for unit, chip and system level Code Coverage and Functional
Coverage using HVL languages.
Strengths include leadership. adaptability, quick at learning new skills, good communication
skills and teamwork with local as well as multi-site and multi-discipline teams
Skill set • Languages : Verilog, System Verilog,VHDL, C, C++
• Simulators : DVE, VCS, Debussy, verdi
• Scripting Language : Perl
• Methodology : OVM, VMM, VERA
• VIP’s : model Synopsys AXI VIP, Denali Otg3, USB2, PCIe VIP, Arasan
SDIO
• Protocol experience : OCP, IOSF, AMBA AHB/APB, SPI, I2C, GPIO, OTG3,
USB2, SMBUS, PCII,
Good experience in Security AES128,256, HCU, RC4
Professional
Experience
11/21/2005-
Present
Intel, Corp
Santa Clara, CA
Senior Verification Engineer
Worked around 8 years on SoC and 3 yrs on IP project.
All these years works on OCP, AMBA AHB/APB, SPI, I2C, GPIO, Security Block,
Key Responsibility:
 IP / SoC verification using OVM/System Verilog.
 Responsible for verification architecture and methodology for IP and system level
 Responsible for Writing verification plans, tests, and building random/directed test
benches.
 Responsible for defining and analyzing functional coverage
 Responsible to debug test failures to find the root cause

2. Sudhir Kumar Page 2 of 2
 Provide technical help to other team members.
9/04-11/18 NEC Electronic, America, Inc
Santa Clara, CA
Senior Verification Engineer
Worked as a Verification Engineer with NEC Electronics America in R& D department
Responsible for creating the testbench for WUSB (Wireless USB2.0) Host using Vera.
Created the Device BFM in Vera using the RVM.
Used the VMT model of wired usb2.0 from Synopsys to verify the Device behind the Hub.
Used the PCI flex Model from Synopsys to verify the PCI Interface with Host.
Used the V850 star CPU from Synopsys to configure the Host.
Analyzed the functional coverage results from regression with designers and architects and
achieved 95% covered.
Developed the environment compatible with gate level simulation.
Helped and trained Junior level engineers to understand the verification environment and how
to debug the failures from regression.
5/04-9/04 Nexsil Communication Inc
Santa Clara, CA
Working as a Sr Verification Engineer.
Responsible for verification of Block Level of PCU(Include PPC microprocessor and
Microblaze processor)
1. Test plan creation and implementation
2. Develop the test bench and test cases
3. Writing tests as per the test-plan, debugging tests, filing bugs, and working with RTL
owners to fix bugs and verify fixes.
4. The module contains the PPC405 from IBM and Microblaze from Xilinx
5. Responsible for running Simulation at Block level as well as FC level
2/04 -4/04 Vitesse semiconductor
Responsible for the verification of PCI Express bus.(Transaction Layer) in VSC886 switch.
Which is a 16 x 16 advance switch device.
• Helping the team members to convert verification environment from e to Vera.
• Teaching Vera to other team members
• Responsible for the test plan creation of Transaction layer (PCI EXPRESS BUS)
• Responsible for creation of transactor of TL using vera
From 95 till
2003
Worked on different project in India.