Instruction pipeline processing system is good for arithmetic and logical instruction. And also, good for multiple tasking at a single time. But has some hazards. If can possible, avoid those hazards then get good benefited for instruction pipeline processing.

1. W E L C O M E T O O U R
P R E S E N TAT I O N

2. Our presentation topic is:
Pipeline processing and generation of
computer.

3. Latch
Segment 1
H1
Latch
Segment 2
H2
Latch
Segment 3
H3
Latch
Segment 4
H4Input Output
Clock
Fig: A four segment Pipeline
PIPELINE PROCESSING:

4. INSTRUCTION PIPELINE:
Fig: A five Segment Instruction Pipeline.
Latch
Latch
Latch
Latch
Latch
Latch
Instruction fetch unit
Instruction decode unit
Operand fetch unit
Operation execution unit
Result routing unit
Segment 1
Segment 4
Segment 5
Segment 2
Segment 3

5. 4TH GENERATION
The period of fourth generation was 1971-1980.The computers of
fourth generation used Very Large Scale Integrated (VLSI) circuits.

6. DEC 10
STAR 1000
PDP 11
CRAY-1(Super Computer)
4th generation Some applications:
Fully integrated IP solution “Anytime ,Anywhere”.
Some Computers of this Generation were:

7. THIRD GENERATION - TRANSISTOR
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Main Memory
Control Unit
Main
Memory
M
IO
Processor
(channel)
IO
Processor
(channel)
IO
devices
Four 64-bit
Floating point
registers
Floating-point
ALU
Fixed-point
ALU
Decimal
ALU
SR PCIR AR
Program status word PSW
Program
Control
Unit PCU
Instruction decoder
(may be micro
programmed)
Control
Signal
IO
devices
Data processing unit, DPU
Sixteen
32-bit
General
registers
Fig: Structure of IBM System/360

8. THE FIRST GENERATION COMPUTERS
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.
.
.
.
M (0)
M (1)
M (2)
M (4,096)
M (4,095)
1
2
3
4094
4095
Instruction
decoder
Program
Control
Unit (PCU)
AR
IBR PC
IR AR
DR
Arithmetic-logic unit
AC MQ
Data
Processing
Unit (DPU)
Main Memory M Fig: Organization of the CPU and
main memory of the IAS
computer.

9. THANK YOU.