Ch2 embedded processors-i

8/13/2012 Embedded Systems 1
Embedded Processors-I
DR. APARNA P.
Assistant Professor
EC Dept
NITK, Surathkal

Embedded Processor Categories
General Purpose Processor
Microcontrollers
Digital Signal Processor
Customized processors and FPGA can be included for
specific functionality.

Microprocessor

General Purpose Processors
Processor designed for a variety of computation tasks
“Off-the-shelf” -- pre-designed for a common task
Low unit cost, in part because manufacturer spreads
NRE over large numbers of units
Carefully designed since higher NRE is acceptable
Can yield good performance, size and power
Low NRE cost, short time-to-market/prototype, high
flexibility
User just writes software; no processor design

Basic Architecture
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control
/Status

Evolution
Intel Processors

-contd
1950s- IBM instituted a research program.
1964- Release of System/360
Mid-1970s improved measurement tools demonstrated on CISC
In 1971- Intel released first processor Intel 4004 for use in calculators.
In 1975 MC 6800 was released- First processor with Index registers.
1975-801 project initiated at IBM’s Watson Research Center.
1979- 32-bit RISC microprocessor (801) developed led by Joel Birnbaum
1979 MC 68000, 32 bit processor with 16 bit buses – With protected mode of operation.
1981 MIPS-I developed at Stanford, RISC-I at Berkeley.
1988 RISC processors had taken over high-end of the workstation market
Early 1990s IBM’s POWER (Performance Optimization With Enhanced RISC)
architecture introduced w/ the RISC System/6k
AIM (Apple, IBM, Motorola) alliance formed, resulting in PowerPC

Architectural Variants
Von Neumann vs Harvard Architecture:
Harvard allows two simultaneous memory fetches.
Most DSPs and embedded controllers use Harvard architecture for
streaming data:
greater memory bandwidth;
more predictable bandwidth
Most of the computers are von Neumann architecture
In certain embedded applications where the program is more-or-less
hard wired, the Harvard architecture is advantageous.
Processor
Program
memory
Data
memory
Processor
Memory
(program and data)
Harvard Von Neumann

-contd
RISC vs CISC
Complex instruction set computer (CISC):
many addressing modes
many operations.
Simple programming and Less program space.
Complex processor
control-store control unit
Reduced instruction set computer (RISC):
load/store architecture
Simple processor and pipelinable instructions.
Hardwired control unit.

Pipelining: Increasing Instruction Throughput
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Fetch-instr.
Decode
Fetch ops.
Execute
Store res.
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Wash
Time
Non-pipelined Pipelined
Time
Time
Pipelined
pipelined instruction
execution
non-pipelined Laundry pipelined Laundry
Instruction 1

-contd: Superscaler vs VLIW
Superscalar
-Fetches instructions in batches,
executes as many as possible
-May require extensive hardware
to detect independent
instructions
VLIW
-Each word in memory has multiple
independent instructions
-Relies on the compiler to detect
and schedule instructions
-Currently growing in popularity
Two Pipelines
Fetch-
instr.
Decode
Execute
1 2 3 4 5 6 7 8
Time
pipelined instruction
execution
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Multiple ALUs to support more than one instruction stream

Typical Processors-VIA C3

Architecture-VIA C3
VIA C3 is processor by VIA
technologies based on x86 ISA.
Compared to Pentium, these are
power efficient and hence more
suitable for embedded market.
Low power consumption and
effective heat dissipation.
Suitable for personal electronics
and mobile phones.
Good performance for Internet,
digital media applications, video
conferencing, web browsing.
Multiple Stages of Pipeline- 12
stages.
More than one Level of Cache
Memory.
Available in EBGA package .

Architectural Details
Instruction Fetch Unit
Fetches instruction from I-cache or the external bus.
Three pipeline stages exist in Instruction Fetch Unit that deliver aligned instructions into
the instruction decode buffers.
The instruction is predecoded as it comes out of the cache
Predecode is overlapped with other required operations and, thus, effectively takes no time.
The fetched instruction data is placed sequentially into multiple buffers.
TLB (Translation Look-aside Buffer) holds the address of the pages in the memory accessed
recently.
The TLB enables faster computing because it allows the address processing to take place
independent of the normal address-translation pipeline.

-contd
Converts instruction byte into internal execution format by 2 pipeline stages.
Branching operations are identified here and the processor starts getting new
instructions from a different location.
The F stage decodes and “formats” an instruction into an intermediate format.
The internal-format instructions are placed into a five-deep FIFO queue: the FIQ.
The X-stage, “translates” an intermediate-form instruction from the FIQ into the
internal microinstruction format.
Instruction fetch, decode, and translation are made asynchronous from execution
via a five-entry FIFO queue.
Instruction Decode Unit

-Contd
Branch Prediction (BP)- Branch History Table (BHT) & Branch Target Buffer (BTB)
IFU pre-fetches the instruction in to IF cache at different stages and sends them
for decoding. In case of Branch instruction all instrn are abandoned and new set
needs to be loaded.
Prediction of branch earlier in the pipeline can save time in flushing out the
current instructions and getting new instructions.
BP is a technique that attempts to infer the proper next instruction address,
knowing only the current one.
Typically it uses a BTB, a small, associative memory that watches the instruction
cache index and tries to predict which index should be accessed next, based on
branch history which stored in another set of buffers known as BHT. This is
carried out in the F stage.

-Contd
Decode stage (R): Micro-instructions are
decoded, integer register files are accessed
and resource dependencies are evaluated.
Addressing stage (A): Memory addresses
are calculated and sent to the D-cache (Data
Cache).
Cache Access stages (D, G): The D-cache
and D-TLB (Data Translation Look aside
Buffer) are accessed and aligned load data
returned at the end of the G-stage.
Execute stage (E): Integer ALU operations
are performed. All basic ALU functions take
one clock except multiply and divide.
Store stage (S): Integer store data is
grabbed in this stage and placed in a store
buffer.
Write-back stage (W): The results of
operations are committed to the register file.
Integer Unit

-Contd
Floating Point Unit (FPU)
Separate 80-bit floating-point execution unit that can execute floating-point
instructions (FPI) in parallel with integer instructions.
FPI are passed from the integer pipeline to the FPU thr’ a separate FIFO queue.
This queue, which runs at the processor clock speed, decouples the slower
running FP unit from the integer pipeline so that the integer pipeline can
continue to process instructions overlapped with FP instructions.
Basic arithmetic floating-point instructions (add, multiply, divide, square root,
compare, etc.) are represented by a single internal floating-point instruction.
Certain little-used and complex floating point instructions (sin, tan, etc.)
implemented in microcode and are represented by a long stream of instructions
coming from the ROM. These instructions “tie up” the integer instruction
pipeline such that integer execution cannot proceed until they complete.

-Contd
MMX & 3D Unit
Separate execution unit for the MMX-compatible instructions.
One MMX instruction can issue into the MMX unit every clock.
The MMX multiplier is fully pipelined and can start one non-dependent
MMX multiply[-add] instruction (which consists of up to four separate
multiplies) every clock.
Other MMX instructions execute in one clock.
Multiplies followed by a dependent MMX instruction require two clocks.
Separate execution unit for some specific 3D instructions.
These instructions provide assistance for graphics transformations SIMD
(Single Instruction Multiple Data) single-precision floating-point
capabilities.
One 3D instruction can issue into the 3D unit every clock.
The 3D unit has two single-precision floating-point multipliers and two
single-precision floating-point adders. Other functions such as
conversions, reciprocal, and reciprocal square root are provided.
The multiplier and adder are fully pipelined and can start any non-
dependent 3D instructions every clock.

VIA C3 processor uses the same x86 instruction set as Intel
processor
It is a pipelined architecture.
Because of the uncertainties associated with Branching the
overall instruction execution time is not fixed (therefore it is not
suitable for some of the real time applications which need
accurate execution speed)
It handles a very complex instruction set .
The overall power consumption because of the complexity of
the processor is higher.

Typical Processors-PowerPC- MPC601
POWER (Performance Optimization With
Enhanced RISC) is a RISC instruction set
architecture designed by IBM.
Created by the 1991 Apple-IBM-Motorola alliance,
known as AIM.
PowerPC is largely based on IBM's POWER
architecture.
The PowerPC architecture allows optimizing
compilers to schedule instructions to maximize
performance through efficient use of the
PowerPC instruction set and register model.
The multiple, independent execution units allow
compilers to maximize parallelism and
instruction throughput.
32-bit and 64-bit PowerPC processors have been a
favorite of embedded computer designers.
MPC601 was the first PowerPC processor with a
speed of 66MHz and 132 MIPS.

•High-performance superscalar MP
— As many as three instructions in execution
per clock
— Single clock cycle execution for most
instructions
— Pipelined FPU for all single-precision and
most double-precision operations
• Three independent execution units and two
register files
— BPU featuring static branch prediction
— A 32-bit IU
— Fully IEEE 754-compliant FPU for both
single- and double-precision operations.
— 32 GPRs for integer operands
— 32 FPRs for single- or double-precision
operands

High instruction and data throughput
Zero-cycle branch capability
Instruction unit capable of fetching eight instructions per clock from the
cache
An eight-entry instruction queue that provides look-ahead capability
Interlocked pipelines with feed-forwarding that control data
dependencies in hardware
Unified 32-Kbyte cache—eight-way set-associative, physically addressed;
LRU replacement
Memory unit with a two-element read queue and a three-element write
queue
Run-time reordering of loads and stores
BPU that performs condition register (CR) look-ahead operations
Address translation facilities for both Data and Instructions thr’ UTLB-
BTB and ITLB resp.
52-bit virtual address; 32-bit physical address

Summary

Ch2 embedded processors-i

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