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Sushant Mishra
Sushant Mishra

THIS IZ ABOUT FIN FETS ....

1 of 33
1 Presented by :- SUSHANT MISHRA EC-2 Under the guidance of :- FinFETs: From Circuit to Architecture
Talk Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],2
Why Double-gate Transistors ? ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],3 Non-Si nano devices Bulk CMOS Feature size 32 nm 10 nm DG-FETs Gap
What are FinFETs? ,[object Object],[object Object],4 Si Fin
Independent-gate FinFETs ,[object Object],[object Object],[object Object],[object Object],5 Back Gate Oxide insulation
FinFET Width Quantization ,[object Object],[object Object],[object Object],[object Object],6 FinFET structure Ananthan, ISQED’05
Talk Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Motivation: Power Consumption ,[object Object],[object Object],[object Object],[object Object],[object Object],† J. Kao, S. Narendra and A. Chandrakasan, “Subthreshold leakage modeling and reduction techniques,” in Proc. ICCAD, 2002.
Logic Styles: NAND Gates SG-mode NAND IG-mode NAND LP-mode NAND IG/LP-mode NAND pull up bias voltage pull down bias voltage IG-mode pull up LP-mode pull down
Comparing Logic Styles † Average leakage current for two-input NAND gate (V dd = 1.0V) Design Mode Advantages Disadvantages SG Fastest under all load conditions High leakage † (1 μ A) LP Very low leakage (85nA), low switched capacitance Slowest, especially under load. Area overhead (routing) IG Low area and switched capacitance Unmatched pull-up and pull-down delays. High leakage (772nA) IG/LP Low leakage (337nA), area and switched capacitance Almost as slow as LP mode
FinFET Circuit Power Optimization ,[object Object],[object Object],[object Object],† D. Chinnery and K. Keutzer, “Linear programming for sizing, V dd and V t assignment,” in Proc. ISLPED , 2005. Benchmark Minimum-delay synthesis in Design Compiler SG-mode netlist Power-optimized mixed-mode netlists SG+ IG/LP SG+IG SG+LP Linear programming based cell selection 32 nm PTM FinFET models Delay/power characterization in SPICE LP IG/LP IG SG Synopsys libraries 32 nm PTM inFET models FinFET models (UFDG, PTM) Logic gate designs Logic gate designs
Power Consumption of Optimized Circuits ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Estimated total power consumption for ISCAS’85 benchmarks V dd = 1.0V, α = 0.1, 32nm FinFETs Available modes
Talk Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Dual-V dd FinFET Circuits ,[object Object],[object Object],[object Object],[object Object],[object Object],1.08V 1V Leakage current Vin Reverse bias V gs =+0.08V Overdriven inverter Higher V th
[object Object],[object Object],[object Object],V th Control with Multiple V dd ’s (TCMS) V dd H V ss H V dd L V ss L TCMS buffer Symmetric threshold control for P and N V dd H 1.08V V dd L 1.0V V ss H -0.08V V ss L 0.0V
Exploratory Buffer Design ,[object Object],[object Object],[object Object],l opt S 1 S 2 V H dd V H ss V L ss V L dd S 1 S 2 V H dd V H ss V L ss V L dd i i’
Power Savings ,[object Object],[object Object],Power component Savings Dynamic power -29.8% Leakage power 57.9% Total power 50.4%
Fin-count Savings ,[object Object],[object Object]
TCMS Extension Delay-minimized netlist Power : 283.6uW Area: 538 fins Power-optimized netlist Power : 149.9uW Area: 216 fins
Power Reduction (ISCAS’85 Benchmarks)
Power-minimized vs Delay-minimized Netlists at 130% ATC TCMS TCMS (Single-Vth Dual-Vdd % reduction in dynamic power 53.3 49.8 51.4 % reduction in leakage power 95.8 95.7 95.8 % reduction in total power 67.6 65.3 66.3 % reduction in Fin-count 65.2 59.5 61.6
Talk Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Orion-FinFET ,[object Object],[object Object],[object Object],[object Object]
Router Microarchitecture & Pipeline Stages
Power Simulation Flow
Power Breakdown for SG/LP Modes ,[object Object],[object Object],[object Object],Router power breakdown Network power breakdown
Bulk CMOS vs. LP-mode FinFETs ,[object Object],[object Object]
Router Leakage Power vs. Temp. ,[object Object],[object Object]
Talk Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
FinFET SRAM and Embedded DRAM Design ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Extension of CACTI for FinFETs ,[object Object],[object Object],[object Object],[object Object]
FPGA vs. ASICs NATURE CMOS fabrication compatible Nano RAM on-chip storage Run-time reconfiguration Temporal logic folding Design flexibility Logic density ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Conclusions ,[object Object],[object Object],[object Object],[object Object],[object Object]

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Sushant

  • 1. 1 Presented by :- SUSHANT MISHRA EC-2 Under the guidance of :- FinFETs: From Circuit to Architecture
  • 2.
  • 3.
  • 4.
  • 5.
  • 6.
  • 7.
  • 8.
  • 9. Logic Styles: NAND Gates SG-mode NAND IG-mode NAND LP-mode NAND IG/LP-mode NAND pull up bias voltage pull down bias voltage IG-mode pull up LP-mode pull down
  • 10. Comparing Logic Styles † Average leakage current for two-input NAND gate (V dd = 1.0V) Design Mode Advantages Disadvantages SG Fastest under all load conditions High leakage † (1 μ A) LP Very low leakage (85nA), low switched capacitance Slowest, especially under load. Area overhead (routing) IG Low area and switched capacitance Unmatched pull-up and pull-down delays. High leakage (772nA) IG/LP Low leakage (337nA), area and switched capacitance Almost as slow as LP mode
  • 11.
  • 12.
  • 13.
  • 14.
  • 15.
  • 16.
  • 17.
  • 18.
  • 19. TCMS Extension Delay-minimized netlist Power : 283.6uW Area: 538 fins Power-optimized netlist Power : 149.9uW Area: 216 fins
  • 21. Power-minimized vs Delay-minimized Netlists at 130% ATC TCMS TCMS (Single-Vth Dual-Vdd % reduction in dynamic power 53.3 49.8 51.4 % reduction in leakage power 95.8 95.7 95.8 % reduction in total power 67.6 65.3 66.3 % reduction in Fin-count 65.2 59.5 61.6
  • 22.
  • 23.
  • 24. Router Microarchitecture & Pipeline Stages
  • 26.
  • 27.
  • 28.
  • 29.
  • 30.
  • 31.
  • 32.
  • 33.